JP4522213B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a semiconductor device having an outer dimension approximately the same as the outer dimension of a semiconductor chip and a method for manufacturing the same.

  In recent years, CSP (Chip Size Package) has attracted attention as a package technology. The CSP refers to a small package having an outer dimension substantially the same as the outer dimension of a semiconductor chip. Conventionally, a BGA type semiconductor device is known as a kind of CSP. In this BGA type semiconductor device, a plurality of ball-shaped conductive terminals made of a metal member such as solder are arranged in a grid pattern on one main surface of a package, and electrically connected to a semiconductor chip formed on the other surface of the package. Is connected to.

  When incorporating this BGA type semiconductor device into an electronic device, each conductive terminal is crimped to a wiring pattern on the printed circuit board, thereby electrically connecting the semiconductor chip and the external circuit mounted on the printed circuit board. Connected.

  Such a BGA type semiconductor device is provided with a larger number of conductive terminals than other CSP type semiconductor devices such as SOP (Small Outline Package) and QFP (Quad Flat Package) having lead pins protruding from the side. And has the advantage of being able to be downsized. This BGA type semiconductor device has an application as an image sensor chip of a digital camera mounted on a mobile phone, for example.

  FIG. 14 shows a schematic configuration of a conventional BGA type semiconductor device, and FIG. 14A is a perspective view of the surface side of the BGA type semiconductor device. FIG. 14B is a perspective view of the back side of the BGA type semiconductor device.

  In the BGA type semiconductor device 100, the semiconductor chip 101 is sealed between the first and second glass substrates 104a and 104b via resins 105a and 105b. On one main surface of the second glass substrate 104b, that is, on the back surface of the BGA type semiconductor device 100, a plurality of ball-shaped terminals (hereinafter referred to as conductive terminals 111) are arranged in a lattice shape. The conductive terminal 111 is connected to the semiconductor chip 101 via the second wiring 109. Aluminum wires drawn from the inside of the semiconductor chip 101 are connected to the plurality of second wirings 109, respectively, and electrical connection between each conductive terminal 111 and the semiconductor chip 101 is made.

  The cross-sectional structure of the BGA type semiconductor device 100 will be described in more detail with reference to FIG. FIG. 15 shows a cross-sectional view of the BGA type semiconductor device 100 divided into individual chips along the dicing line.

  A first wiring 103 is provided on the insulating film 102 disposed on the surface of the semiconductor chip 101. The semiconductor chip 101 is bonded to the first glass substrate 104a with a resin 105a. The back surface of the semiconductor chip 101 is bonded to the second glass substrate 104b with a resin 105b. One end of the first wiring 103 is connected to the second wiring 109. The second wiring 109 extends from one end of the first wiring 103 to the surface of the second glass substrate 104b. A ball-shaped conductive terminal 111 is formed on the second wiring 109 extending on the second glass substrate 104b.

The technique described above is described in Patent Document 1 below.
Patent Publication 2002-512436

  Since the semiconductor device described above uses two glass substrates, the semiconductor device becomes thicker and the cost increases. Therefore, a method of bonding the glass substrate only to the side where the first wiring is formed has been studied. In that case, since the side to which the glass substrate is not bonded becomes a semiconductor substrate, etching processing becomes easier as compared with the glass substrate. Taking advantage of this advantage, in order to connect the first wiring and the second wiring, the semiconductor substrate and the insulating film in the scribe region are etched to expose the first wiring. As a result, the contact area between the first wiring and the second wiring can be increased as compared with the method using two sheets of glass. Thereafter, a second wiring, a protective film, a conductive terminal, and the like are formed, and the glass substrate is finally cut to separate the semiconductor devices individually.

  On the other hand, after the first wiring is exposed, the scribe region is exposed to the insulating film formed when the circuit is formed on the semiconductor substrate. At this time, only the insulating film, resin, and glass substrate exist in the scribe region. Considering the thickness of each part, substantially all the semiconductor chips are supported only by the glass substrate. Further, since the coefficient of thermal expansion is different between the material of the semiconductor substrate and the glass substrate, the glass substrate is greatly warped. Therefore, a load such as a semiconductor chip bonded to the glass substrate is applied to the glass substrate by handling during the operation. As a result, as shown in FIG. 12, peeling 204 occurs between the semiconductor chip and a glass substrate (not shown) at the outer periphery of the semiconductor chip, or a crack 205 occurs on the glass substrate 202. As a result, there arises a problem that the yield and reliability of the semiconductor device are lowered.

  In the present invention, as shown in FIG. 13, only the portion where the first wiring is exposed is etched without etching the entire scribe region. Hereinafter, the portion where the first wiring is exposed is referred to as a window 303. As a result, most of the glass substrate (not shown) is kept in a state of being bonded to the semiconductor substrate 302 via a resin or an insulating film (not shown). In this state, an insulating film, a second wiring, and the like are formed, and finally, a region indicated by 304 in FIG. 13 is removed by dicing so that the semiconductor devices are individually separated.

  In the present invention, as shown in FIG. 10, when the semiconductor devices are individually separated, a cut 30 is formed along the entire cutting region 304 at the time of dicing, and the cut 30 is further formed into a second protective film. After covering with 10, dicing is performed.

Furthermore, in the present invention, as shown in FIG. 7, the first protective film 25 is formed so as to cover the second wiring 8 before the step of making the cuts 30.

The present invention has an effect of improving the yield and reliability of a semiconductor device by preventing the occurrence of cracks in the glass substrate and the peeling at the periphery of the semiconductor chip. Further, since the number of glass substrates is changed from two to one, the semiconductor device can be thinned and the cost can be reduced.

  Furthermore, since the protective film is formed so as to cover the second wiring before the cutting process, it is possible to prevent the second wiring from being contaminated with chips or the like. Moreover, the corrosion of the wiring by the cooling water of the blade used when making the cut 30 can be suppressed.

  Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to cross-sectional views of the semiconductor device of FIGS. 1 to 11 and a plan view of the semiconductor device of FIG.

  First, as shown in FIG. 1, a semiconductor substrate 1 is prepared. These semiconductor substrates 1 are obtained by forming, for example, a CCD image sensor or a semiconductor memory on the semiconductor substrate 1 by a semiconductor process. A first wiring having a predetermined gap in the vicinity of a boundary S (referred to as a dicing line or a scribe line) to be divided for each semiconductor chip later through the first insulating film 2 on the surface. 3 is formed. Here, the first wiring 3 is a pad extended from the bonding pad of the semiconductor device to the vicinity of the boundary S. That is, the first wiring 3 is an external connection pad and is electrically connected to a circuit (not shown) of the semiconductor device.

  Next, a glass substrate 4 used as a support is bonded to the semiconductor substrate 1 on which the first wiring 3 is formed using a resin 5 (for example, epoxy resin) as a transparent adhesive. Here, a glass substrate is used as a support and an epoxy resin is used as an adhesive. However, a silicon substrate, a plastic plate, or a tape-like material may be used as a support. An appropriate adhesive may be selected for the support.

  Thereafter, the surface of the semiconductor substrate 1 opposite to the surface to which the glass substrate 4 is bonded is back-ground to reduce the thickness of the substrate.

  Next, as shown in FIGS. 2A and 2B, a part of the first wiring 3 is formed on the surface of the semiconductor substrate 1 opposite to the surface to which the glass substrate 4 is bonded. Isotropic etching (or anisotropic etching) of the semiconductor substrate 1 is performed using a resist pattern (not shown) provided with an opening so as to be exposed as a mask. As a result, in the portion where the first wiring 3 exists, as shown in FIG. 2A, a window 20 which is an opening opening the semiconductor substrate 1 at the boundary S is formed, and the first insulating film is formed. 2 is exposed. On the other hand, in the portion where the first wiring 3 does not exist, the semiconductor substrate 1 remains as shown in FIG. As a result, when the semiconductor device of FIGS. 2A and 2B is viewed from the semiconductor substrate 1 side, the plan view of FIG. 13 is obtained. In FIG. 13, the first wiring is 301, the semiconductor substrate is 302, and the window is 303.

  As described above, by providing the window 20 that can expose only the position corresponding to the first wiring 3, the region where the semiconductor substrate 1 and the glass substrate 4 are bonded via the first insulating film 2 and the resin 5. Increase. Thereby, the support strength by the glass substrate 4 is raised. Moreover, the increase in the curvature of the glass substrate 4 by the difference in the thermal expansion coefficient of the semiconductor substrate 1 and the glass substrate 4 is reduced, and the crack and peeling which arise in a semiconductor device are reduced.

  Note that the etching may be performed by either dry etching or wet etching. In the description of the subsequent steps, as in FIGS. 2A and 2B, the sectional view of the portion where the window 20 is formed is the figure number (a), and the window 20 is not formed. A sectional view of the portion is shown as a drawing number (b).

  The etched surface of the semiconductor substrate 1 has in-plane irregularities, residues, and foreign matter. Further, as shown in circles 1a and 1b in FIG. It has a pointed shape.

  Therefore, as shown in FIGS. 3A and 3B, wet etching is performed to remove residues and foreign matters and to round off the tip of the sharp portion. As a result, the sharp portions of 1a and 1b circled in FIG. 2 (a) have a smooth shape as shown in 1a and 1b circled in FIG. 3 (a).

  Next, as shown in FIGS. 4A and 4B, the second insulating film 6 is formed on the surface of the semiconductor substrate 1 opposite to the surface to which the glass substrate 4 is bonded. I do. In this embodiment, a silane-based oxide film is formed to a thickness of about 3 μm.

  Next, a resist (not shown) is applied to the surface of the semiconductor substrate 1 opposite to the surface to which the glass substrate 4 is bonded, and patterning is performed so as to open a portion along the boundary S in the window 20. Then, a resist film is formed. Then, as shown in FIGS. 5A and 5B, the second insulating film 6 and the first insulating film 2 are etched using the resist film (not shown) as a mask, and the first wiring A part of 3 is exposed.

  Next, as shown in FIGS. 6A and 6B, a flexible buffer member 7 is formed so as to correspond to a position where the conductive terminal 11 will be formed later. Although the buffer member 7 has a function of absorbing the force applied to the conductive terminal 11 and relieving stress when the conductive terminal 11 is joined, the present invention does not limit the non-use of the buffer member 7. .

  Next, a second wiring layer is formed on the opposite surface of the glass substrate 4. Thereby, the first wiring 3 and the wiring layer are electrically connected.

Thereafter, a resist (not shown) is applied to the opposite surface of the glass substrate 4. Here, in a portion where the window 20 is formed, a resist film pattern is formed so as to open a portion along the boundary S in the window 20. On the other hand, in a portion where the window 20 is not opened, a resist film pattern is formed so as to expose the wiring layer. Then, etching is performed using the resist film (not shown) as a mask, and the wiring layer near the boundary S is removed. Further, the wiring layer in the portion where the window 20 is not formed is removed, and the second wiring 8 is formed.

Next, as shown in FIGS. 7A and 7B, a first protective film 25 is formed on the entire surface so as to cover the second wiring 8. In order to form the first protective film 25, a thermosetting organic resin is spray-coated with the opposite surface of the glass substrate 4 facing upward. Then, the first protective film 25 is formed by thermosetting the organic resin. The formation of the protective film 25 is not limited to the spray coating method described above, and a spin coating method may be used. However, the spray coating method can form a protective film having a more uniform film thickness. Therefore, since the protective film 25 of the present embodiment has a relatively uniform film thickness, the removal work when removing the protective film 25 in the subsequent steps is simplified. In the process of completing the semiconductor device without removing the protective film 25, the protective film 25 does not accumulate thickly at the bottom of the window 20, and warpage can be suppressed. That is, when the protective film 25 is thickly accumulated at the bottom of the window 20, the organic resin has the property of a viscous paste. There is a phenomenon that the semiconductor wafer is warped when the organic resin accumulated in the window 20 contracts more than the organic resin covering the other part of the semiconductor device. However, in the present invention, occurrence of such a problem can be suppressed.

Next, as shown in FIG. 8A and FIG. 8B, the glass substrate 4 is cut along the boundary S through the first protective film 25 to a depth of about 30 μm, for example. The notch 30 (inverted V-shaped groove) is formed.

  That is, in the portion where the first wiring 3 exists on the semiconductor substrate 1 (that is, the portion along the boundary S in the window 20), the first protective film 25, the resin 5 and a part of the glass substrate 4 are cut. Thus, the cut 30 is formed. At this time, it is necessary to use a blade having a width that does not contact the second wiring 8 in the window 20.

On the other hand, in the region where the first wiring 3 does not exist on the semiconductor substrate 1 (that is, the region where the window 20 is not formed), the first protective film 25, the second insulating film 6, the semiconductor substrate 1, the first insulating film. Part of the film 2, the resin 5, and the glass substrate 4 is cut to form the cuts 30.

Here, in the present embodiment, since the first protective film 25 is formed so as to cover the second wiring 8 before the step of cutting, the second wiring 8 is contaminated with chips or the like. Can be suppressed. Moreover, the corrosion of the wiring by the cooling water of the blade used when making the cut 30 can be suppressed.

In the present embodiment, the cut 30 has a wedge-shaped cross-sectional shape, but may have a rectangular cross-sectional shape.

  Next, as shown in FIGS. 9A and 9B, after removing the first protective film 25, an electroless plating process is performed on the opposite surface of the glass substrate 4, A Ni—Au plating film 9 is formed on the second wiring 8. Since this film is plated, it is formed only on the portion where the second wiring 8 exists.

  Next, as shown in FIGS. 10A and 10B, the second protective film 10 is formed on the opposite surface of the glass substrate 4. In the case of forming the second protective film 10, an organic resin is formed on the substrate surface in the same manner as the first protective film 25 is formed. Thereby, the second protective film 10 is formed on the back surface side of the semiconductor substrate 1 including the inner wall of the cut 30 formed along the boundary S.

  That is, in the portion where the first wiring 3 exists on the semiconductor substrate 1 (that is, the portion along the boundary S in the window 20), the resin 5 exposed on the inner wall of the notch 30 from the surface of the second insulating film 6. And the 2nd protective film 10 is formed so that the glass substrate 4 may be covered. On the other hand, in the region other than the portion where the first wiring 3 exists on the semiconductor substrate 1 (that is, the region where the window 20 is not formed), the second exposed from the surface of the second insulating film 6 on the inner wall of the cut 30. A second protective film 10 is formed so as to cover the exposed portions of the insulating film 6, the semiconductor substrate 1, the first insulating film 2, the resin 5, and the glass substrate 4.

  Thereafter, the portion of the second protective film 10 where the conductive terminal 11 is to be formed is removed by etching using a resist mask (not shown) (having an opening at a position corresponding to the buffer member 7). Conductive terminals 11 are formed at positions on the Ni—Au plating film 9 to be performed. The conductive terminal 11 is electrically connected to the second wiring 8 through the Ni—Au plating film 9. The conductive terminal 11 is made of a solder bump or a gold bump. In particular, when gold bumps are used, the thickness of the conductive terminal 11 can be reduced from 160 μm to several μm to several tens of μm.

  Then, as shown in FIGS. 11A and 11B, dicing is performed along the boundary S from the portion where the notch 30 is provided, and the semiconductor device is separated into each semiconductor chip. The width of the blade used for this dicing needs to be a width that can cut only the glass substrate 4 and the protective film 10 in the cut 30.

  As described above, according to the method for manufacturing a semiconductor device of this embodiment, two-stage dicing, that is, the cut 30 is formed, and the dicing is performed after the protective film 10 covering the cut 30 is formed. Thereby, when dicing the semiconductor device into individual semiconductor chips, the inner wall of the cut 30 formed along the boundary S (that is, the dicing line) is covered with the protective film 10, so that the glass substrate 4 and Separation can be performed by dicing only the protective film 10. That is, the blade does not come into contact with layers other than the glass substrate 4 and the protective film 10 (the resin 5 and the second wiring 8). Therefore, it is possible to suppress the separation of the separated semiconductor device, that is, the semiconductor chip due to the contact of the blade during dicing, as much as possible.

  As a result, the yield and reliability of the semiconductor device can be improved. In addition, since the semiconductor device of the present invention is composed of a single glass substrate, it is possible to reduce the thickness and reduce the cost of the semiconductor device.

  In the description of the present embodiment, the first protective film 25 is removed after the cuts 30 are formed, but this does not limit the removal of the first protective film 25. In the state where the Ni—Au plating film 9 is formed on the second wiring 8, the first protective film 25 is formed, and the notch 30 is made. Then, a region where the conductive terminal 11 is formed is removed from the first protective film 25 by etching using a resist mask, and the conductive terminal 11 is placed at a position on the Ni—Au plating film 9 corresponding to the buffer member 7. Is formed.

  In the present embodiment, the conductive terminal 11 electrically connected to the second wiring 8 is formed, but the present invention is not limited to this. That is, the present invention may be applied to a semiconductor device (for example, LGA: Land Grid Array type package) in which a conductive terminal is not formed.

It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a top view in the middle of manufacture of the semiconductor device which concerns on a prior art example. It is a top view in the middle of manufacture of the semiconductor device concerning the embodiment of the present invention. It is a perspective view of the semiconductor device which concerns on a prior art example. It is sectional drawing of the semiconductor device which concerns on a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 1st insulating film 3 1st wiring 4 Glass substrate 5 Resin 6 2nd insulating film 8 2nd wiring 10 2nd protective film 11 Conductive terminal 20 Window 25 1st protective film

Claims (4)

Bonding a support via an adhesive so as to cover the first wiring formed on the semiconductor substrate via the first insulating film;
Patterning a surface opposite to the surface of the semiconductor substrate to which the support is bonded to expose the first insulating film;
Forming a second insulating film on the surface of the semiconductor substrate from which the first insulating film is exposed;
Etching the first insulating film and the second insulating film to expose the first wiring;
Forming a second wiring electrically connected to the first wiring;
Forming a first protective film so as to cover the second wiring;
Cutting the surface of the semiconductor substrate through the first protective film;
Removing the first protective film after the incision step;
And a step of dicing from the cut surface to separate each semiconductor element. Bonding a support via an adhesive so as to cover the first wiring formed on the semiconductor substrate via the first insulating film;
Patterning a surface opposite to the surface of the semiconductor substrate to which the support is bonded to expose the first insulating film;
Forming a second insulating film on the surface of the semiconductor substrate from which the first insulating film is exposed;
Etching the first insulating film and the second insulating film to expose the first wiring;
Forming a second wiring electrically connected to the first wiring;
Forming a first protective film so as to cover the second wiring;
Processing to cut from the surface of the semiconductor substrate to the support through the first protective film;
And a step of dicing from the cut surface to separate each semiconductor element . 3. The semiconductor device according to claim 1, further comprising a step of covering the notch with a second protective film, wherein only the second protective film and the support are cut in the dicing process. 4. Manufacturing method. 4. The method of manufacturing a semiconductor device according to claim 1, wherein an organic resin is used as the first protective film .