JP2004088085A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
JP2004088085A
JP2004088085A JP2003178223A JP2003178223A JP2004088085A JP 2004088085 A JP2004088085 A JP 2004088085A JP 2003178223 A JP2003178223 A JP 2003178223A JP 2003178223 A JP2003178223 A JP 2003178223A JP 2004088085 A JP2004088085 A JP 2004088085A
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Japan
Prior art keywords
wiring
forming
semiconductor chip
insulating film
etching
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JP2003178223A
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JP4371719B2 (en
JP2004088085A5 (en
Inventor
Katsuhiko Kitagawa
Takashi Noma
Hiroyuki Shinoki
Nobuyuki Takai
Toshimichi Tokushige
北川 勝彦
徳重 利洋智
篠木 裕之
野間 崇
高井 信行
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Sanyo Electric Co Ltd
三洋電機株式会社
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Abstract

<P>PROBLEM TO BE SOLVED: To reduce the cost and improve the reliability of a BGA (Ball Grid Array) semiconductor device having ball-shaped conductive terminals. <P>SOLUTION: A film material 5a is stuck onto a first wiring 3 that is formed on a semiconductor chip 1 through a first insulation film 2 through a resin 4 made of an epoxy material as a supporting material. After the rear side of the semiconductor chip 1 is etched to expose the first wiring 3, a second wiring 9 is formed in such a manner as to contact the first wiring 3. Then, a conductive terminal 13 is formed on the second wiring 9. <P>COPYRIGHT: (C)2004,JPO

Description

【0001】
【発明の属する技術分野】
本発明は、ボール状の導電端子を有するBGA(Ball Grid Array)型の半導体装置に関するものである。
【0002】
【従来の技術】
近年、三次元実装技術として、また新たなパッケージ技術として、CSP(Chip Size Package)が注目されている。CSPとは、半導体チップの外形寸法と略同サイズの外形寸法を有する小型パッケージをいう。
【0003】
従来より、CSPの半導体装置の一種としてBGA型のものがあった。 Conventionally, there has been a BGA type as a kind of CSP semiconductor device. 当該半導体装置は、半田等の金属部材からなるボール状の導電端子をパッケージ基板の一主面上に格子状に複数配列し、基板の他の面上に搭載される半導体チップとボンディングしてパッケージするものである。 In the semiconductor device, a plurality of ball-shaped conductive terminals made of a metal member such as solder are arranged in a grid pattern on one main surface of a package substrate, and bonded to a semiconductor chip mounted on the other surface of the substrate to form a package. Is what you do. そして、電子機器に組み込まれる際には、各導電端子をプリント基板上の配線パターンに熱溶解し、半導体チップとプリント基板上に搭載される外部回路とを同時に電気的に接続する。 Then, when incorporated into an electronic device, each conductive terminal is thermally melted into a wiring pattern on the printed circuit board, and the semiconductor chip and the external circuit mounted on the printed circuit board are electrically connected at the same time.
【0004】 0004
このようなBGA型の半導体装置は、その側面に突出したリードピンを有するSOP(Small Outline Package)やQFP(Quad Flat Package)等の他のCSP型の半導体装置に比べて多数の接続端子を設置でき、小型化できるという長所を有する。 Such a BGA type semiconductor device can be provided with a large number of connection terminals as compared with other CSP type semiconductor devices such as SOP (Small Outline Package) and QFP (Quad Flat Package) having lead pins protruding from the side surface thereof. It has the advantage of being able to be miniaturized. このBGA型の半導体装置は、近年CCDイメージセンサの分野にも採用されて、小型化の要望の強い携帯電話機に搭載されるデジタルカメラのイメージセンサチップとして用いられている。 This BGA type semiconductor device has been adopted in the field of CCD image sensors in recent years, and is used as an image sensor chip for a digital camera mounted on a mobile phone, which has a strong demand for miniaturization.
【0005】 0005
図18は、従来のBGA型の半導体装置の概略構成を成すものであり、(A)、(B)はそれぞれ半導体装置の表面側、裏面側から投射した斜視図である。 FIG. 18 is a schematic configuration of a conventional BGA type semiconductor device, and FIGS. 18A and 18B are perspective views projected from the front surface side and the back surface side of the semiconductor device, respectively.
【0006】 0006
BGA型の半導体装置101はCCDイメージセンサチップであり、第1及び第2のガラス基板102、103の間に半導体チップ104がエポキシ材の樹脂105を介して封止されている。 The BGA type semiconductor device 101 is a CCD image sensor chip, and the semiconductor chip 104 is sealed between the first and second glass substrates 102 and 103 via an epoxy resin 105. 第2のガラス基板103の一主面上、即ち半導体装置101の裏面上には、ボール状の導電端子106が格子状に複数配置されている。 A plurality of ball-shaped conductive terminals 106 are arranged in a grid pattern on one main surface of the second glass substrate 103, that is, on the back surface of the semiconductor device 101. この導電端子106は配線107を介して半導体チップ104に接続される。 The conductive terminal 106 is connected to the semiconductor chip 104 via the wiring 107.
【0007】 0007
次に半導体装置101の製造工程を、図13乃至図17を参照しながら順次説明する。 Next, the manufacturing process of the semiconductor device 101 will be sequentially described with reference to FIGS. 13 to 17.
【0008】 0008
図13参照:複数の半導体チップ104を有する半導体ウエハを用意し、その表面上に絶縁膜108を介して第1の配線107を形成する。 See FIG. 13: A semiconductor wafer having a plurality of semiconductor chips 104 is prepared, and a first wiring 107 is formed on the surface of the semiconductor wafer via an insulating film 108. この第1の配線107は、後工程のダイシング工程を経て、各半導体チップ104毎に分断するための境界(スクライブライン)Sを跨るように形成される。 The first wiring 107 is formed so as to straddle a boundary (scribe line) S for dividing each semiconductor chip 104 through a dicing step in a subsequent process.
【0009】 0009
続いて、第1の配線107が形成された半導体チップ104の表面上に第1のガラス基板102を透明のエポキシ材の樹脂105を用いて接着する。 Subsequently, the first glass substrate 102 is adhered to the surface of the semiconductor chip 104 on which the first wiring 107 is formed by using the transparent epoxy resin 105. そして、半導体チップ104をバックグラインドしてチップ厚を薄くすると共に、半導体チップ104の裏面側から境界Sに沿ってエッチングし、第1の配線107を露出させる。 Then, the semiconductor chip 104 is back grinded to reduce the chip thickness, and the semiconductor chip 104 is etched from the back surface side along the boundary S to expose the first wiring 107.
【0010】 0010
図14参照:続いて、エッチング部分及び第1の配線107の露出部分を覆うようにエポキシ材の樹脂105を充填し、この樹脂105を接着剤として、半導体チップ104の裏面側に第2のガラス基板103を接着する。 See FIG. 14: Subsequently, an epoxy resin 105 is filled so as to cover the etched portion and the exposed portion of the first wiring 107, and the resin 105 is used as an adhesive on the back surface side of the semiconductor chip 104 as a second glass. The substrate 103 is adhered.
【0011】 0011
図15参照:次に半導体装置の裏面側から境界Sに沿って、例えば逆V字型にノッチング(チップ裏面側から鋸等の器具を用いて切削加工)を施してV字型溝を形成する。 See FIG. 15: Next, a V-shaped groove is formed by performing notching (cutting from the back surface side of the chip using an instrument such as a saw) in an inverted V shape along the boundary S from the back surface side of the semiconductor device. .. このとき、ノッチングは、第1の配線107を分断する程度まで行い、第1の配線107の一部(分断面)をノッチング表面に露出させる。 At this time, the notching is performed to the extent that the first wiring 107 is divided, and a part (divided cross section) of the first wiring 107 is exposed on the notching surface.
【0012】 [0012]
図16参照:続いて、第2のガラス基板103及びノッチングで形成された切削面(V字型溝)を覆うようにアルミニウム層を形成する。 See FIG. 16: Subsequently, an aluminum layer is formed so as to cover the second glass substrate 103 and the cutting surface (V-shaped groove) formed by notching. これにより、第1の配線107の露出面とアルミニウム層とが接続される。 As a result, the exposed surface of the first wiring 107 and the aluminum layer are connected. その後、アルミニウム層を所定の配線パターンとなるようにパターニングして第2の配線110を形成する。 After that, the aluminum layer is patterned so as to have a predetermined wiring pattern to form the second wiring 110.
【0013】 0013
図17参照:第2の配線110上に不図示の保護膜(ソルダーマスク)を形成し、半田等で形成されたボール状の導電端子106を所望位置に形成する。 See FIG. 17: A protective film (solder mask) (not shown) is formed on the second wiring 110, and a ball-shaped conductive terminal 106 formed of solder or the like is formed at a desired position. 続いて、境界Sに沿ってダイシングする。 Then, dicing is performed along the boundary S. これより、図18に示す従来のBGA型の半導体装置101が完成する。 As a result, the conventional BGA type semiconductor device 101 shown in FIG. 18 is completed.
【0014】 0014.
【特許文献1】 [Patent Document 1]
特表2002−512436号公報【0015】 Japanese Patent Application Laid-Open No. 2002-512436 [0015]
【発明が解決しようとする課題】 [Problems to be Solved by the Invention]
しかしながら、上述したBGA型の半導体装置101及びその製造プロセスにおいて、以下の課題が存在した。 However, the following problems have existed in the above-mentioned BGA type semiconductor device 101 and its manufacturing process.
【0016】 0016.
▲1▼従来のBGA型の半導体装置101は、半導体チップ104の表面側及び裏面側に支持材として、2枚のガラス基板(第1のガラス基板102と第2のガラス基板103)を有しており、ガラス材は比較的高価なものであり、安価な材質を用いた支持材を有する半導体装置が望まれていた。 (1) The conventional BGA type semiconductor device 101 has two glass substrates (first glass substrate 102 and second glass substrate 103) as support materials on the front surface side and the back surface side of the semiconductor chip 104. Therefore, the glass material is relatively expensive, and a semiconductor device having a support material using an inexpensive material has been desired. 加えて、ガラス基板を利用することにより、製造プロセスにおいてパーティクルが発生し易くなるという課題もあった。 In addition, there is also a problem that particles are likely to be generated in the manufacturing process by using the glass substrate.
【0017】 [0017]
▲2▼上記製造工程の図15において、逆V字型溝を形成するためにノッチングを行っている。 (2) In FIG. 15 of the above manufacturing process, notching is performed in order to form an inverted V-shaped groove. この結果、第1の配線107の端部における切削加工した断面に異常(例えば、異物混入やコンタミネーション(汚染)の生成等)が生じていた。 As a result, an abnormality (for example, foreign matter contamination, contamination (contamination) generation, etc.) occurred in the cut cross section at the end of the first wiring 107.
【0018】 0018
▲3▼また、図17において、第1の配線107と第2の配線110との接触面がわずか2〜3μm程度しか設けられず、いわゆる点接触であるため、外部からストレス等が加わった場合、その接続面が離間し、断線する可能性もあり、接続信頼性という点において不安があった。 (3) Further, in FIG. 17, the contact surface between the first wiring 107 and the second wiring 110 is provided only about 2 to 3 μm, which is so-called point contact, so that when stress or the like is applied from the outside. , The connection surface may be separated and the wire may be broken, and there was concern about the connection reliability.
【0019】 0019
本発明は、上記課題に鑑み成されたものであり、ノッチングを行うことなく、且つガラス基板に変わる支持材を用いることで低コスト化したBGA型の半導体装置を提供するものである。 The present invention has been made in view of the above problems, and provides a BGA type semiconductor device at low cost by using a support material that can be used instead of a glass substrate without notching. 加えて、第1の配線と第2の配線との接触面を増加し、その接続工程における信頼性を向上させるものである。 In addition, the contact surface between the first wiring and the second wiring is increased, and the reliability in the connection process is improved.
【0020】 0020
【課題を解決するための手段】 [Means for solving problems]
本発明の半導体装置の製造方法は、半導体チップ上に第1の絶縁膜を介して一定の離間距離を有するように第1の配線を形成する工程と、前記第1の配線上を含む前記半導体チップ上に接着剤を介して支持材を接着する工程と、前記半導体チップ裏面をエッチングすることで前記第1の配線及び当該離間箇所に充填された前記接着剤を露出させる工程と、前記半導体チップ裏面及び前記エッチング箇所に第2の絶縁膜を形成する工程と、前記第2の絶縁膜の所望位置をエッチングした後に前記第1の配線とコンタクトする第2の配線を形成する工程と、前記第2の配線上に導電端子を形成し、前記第1の配線の離間位置に沿ってダイシングする工程とを具備し、前記支持材がフィルム材、又は再生シリコン基板であることを特徴とするものである。 The method for manufacturing a semiconductor device of the present invention includes a step of forming a first wiring on a semiconductor chip via a first insulating film so as to have a certain separation distance, and the semiconductor including the first wiring. A step of adhering a support material onto the chip via an adhesive, a step of exposing the first wiring and the adhesive filled in the separated portion by etching the back surface of the semiconductor chip, and the semiconductor chip. A step of forming a second insulating film on the back surface and the etched portion, a step of forming a second wiring that contacts the first wiring after etching a desired position of the second insulating film, and the first step. It comprises a step of forming a conductive terminal on the wiring of No. 2 and dying along the separated position of the first wiring, and the support material is a film material or a recycled silicon substrate. is there.
【0021】 0021.
また、半導体チップ上に第1の絶縁膜を介して一定の離間距離を有するように第1の配線を形成する工程と、前記第1の配線上に絶縁物からなる支持材を形成する工程と、前記半導体チップ裏面をエッチングすることで前記第1の配線及びその離間箇所に配置された前記支持材を露出させる工程と、前記半導体チップ及び前記エッチング箇所に第2の絶縁膜を形成する工程と、前記第2の絶縁膜の所望位置をエッチングした後に前記第1の配線とコンタクトする第2の配線を形成する工程と、前記第2の配線上に導電端子を形成し、前記第1の配線の離間位置に沿ってダイシングする工程とを具備することを特徴とするものである。 Further, a step of forming the first wiring on the semiconductor chip so as to have a certain separation distance via the first insulating film, and a step of forming a support material made of an insulator on the first wiring. A step of exposing the first wiring and the support material arranged at the separated portion by etching the back surface of the semiconductor chip, and a step of forming a second insulating film on the semiconductor chip and the etched portion. A step of forming a second wiring that contacts the first wiring after etching a desired position of the second insulating film, and a step of forming a conductive terminal on the second wiring to form the first wiring. It is characterized by including a step of dying along the separated position of the above.
【0022】 0022.
更に、前記絶縁物が、透明性を有するエポキシ材又はポリイミド材からなることを特徴とするものである。 Further, the insulating material is characterized by being made of a transparent epoxy material or polyimide material.
【0023】 [0023]
また、半導体チップ上に第1の絶縁膜を介して一定の離間距離を有するように第1の配線を形成する工程と、前記第1の配線上を含む前記半導体チップ上に酸化膜を形成する工程と、前記半導体チップ裏面をエッチングすることで前記第1の配線及びその離間箇所に配置された前記酸化膜を露出させる工程と、前記半導体チップ及び前記エッチング箇所に第2の絶縁膜を形成する工程と、前記第2の絶縁膜の所望位置をエッチングした後に前記第1の配線とコンタクトする第2の配線を形成する工程と、前記第2の配線上に導電端子を形成し、前記第1の配線の離間位置に沿ってダイシングする工程とを具備することを特徴とするものである。 Further, a step of forming the first wiring on the semiconductor chip so as to have a certain separation distance via the first insulating film, and forming an oxide film on the semiconductor chip including the first wiring. A step of exposing the oxide film arranged at the first wiring and the separated portion by etching the back surface of the semiconductor chip, and forming a second insulating film at the semiconductor chip and the etched portion. A step, a step of forming a second wiring that contacts the first wiring after etching a desired position of the second insulating film, and a step of forming a conductive terminal on the second wiring, and the first It is characterized by including a step of dying along a separated position of the wiring of the above.
【0024】 0024
更に、前記酸化膜を低圧CVD法、又はプラズマCVD法によって形成することを特徴とするものである。 Further, the oxide film is formed by a low pressure CVD method or a plasma CVD method.
【0025】 0025
【発明の実施の形態】 BEST MODE FOR CARRYING OUT THE INVENTION
本発明の第1乃至第3の実施形態について詳細に説明する。 The first to third embodiments of the present invention will be described in detail. 本発明の各実施形態では、従来例に見られるように支持材として高価なガラス基板を用いずに半導体装置を完成している点で共通するものである。 Each embodiment of the present invention is common in that a semiconductor device is completed without using an expensive glass substrate as a support material as seen in conventional examples.
【0026】 0026
以下、本発明の第1の実施形態の製造方法について図1乃至図8を参照にしながら順次説明する。 Hereinafter, the production method of the first embodiment of the present invention will be sequentially described with reference to FIGS. 1 to 8.
【0027】 [0027]
図1参照:第1工程。 See FIG. 1: First step.
【0028】 [0028]
複数の半導体チップ1を有する半導体ウエハを用意する。 A semiconductor wafer having a plurality of semiconductor chips 1 is prepared. この半導体チップ1は、例えばCCDイメージセンサチップ等である。 The semiconductor chip 1 is, for example, a CCD image sensor chip or the like.
【0029】 [0029]
続いて、当該半導体チップ1上に第1の絶縁膜2を介して半導体チップ1の境界(ダイシングライン)Sを跨るように第1の配線3を一定の距離d1だけ離間して形成する。 Subsequently, the first wiring 3 is formed on the semiconductor chip 1 at a certain distance d1 so as to straddle the boundary (dicing line) S of the semiconductor chip 1 via the first insulating film 2. 尚、第1の配線3は、例えばアルミニウム、アルミニウム合金または銅から成る金属パッドで、半導体チップ1内の回路素子と電気的に接続されている。 The first wiring 3 is, for example, a metal pad made of aluminum, an aluminum alloy, or copper, and is electrically connected to a circuit element in the semiconductor chip 1. この第1の配線3は、複数の半導体チップ1の境界まで延在しているので、エクステンションパッドとも呼ばれる。 Since the first wiring 3 extends to the boundary of the plurality of semiconductor chips 1, it is also called an extension pad.
【0030】 [0030]
図2参照:第2工程。 See Figure 2: Second step.
【0031】 0031
続いて、図2に示すように前記第1の配線3を含む半導体ウエハ上に透明なエポキシ材の樹脂4を形成する。 Subsequently, as shown in FIG. 2, a transparent epoxy resin 4 is formed on the semiconductor wafer including the first wiring 3. そして、当該樹脂4を介して半導体ウエハ上に、透明で厚さ数百μmの有機系のフィルム材5aを貼り付ける。 Then, a transparent organic film material 5a having a thickness of several hundred μm is attached onto the semiconductor wafer via the resin 4. ここで、前記樹脂4は接着性を有したエポキシ樹脂で、距離d1だけ離間された第1の配線3の離間領域にも充填されている。 Here, the resin 4 is an epoxy resin having adhesiveness, and is also filled in a separated region of the first wiring 3 separated by a distance d1.
【0032】 [0032]
そして、半導体チップ1をバックグラインドしてチップ厚を薄くすると共に、半導体チップ1の裏面側から境界Sに沿って、半導体チップ1及び第1の絶縁膜2をエッチングして開口部を形成し、第1の配線3の一部、及び樹脂4の一部を露出させる。 Then, the semiconductor chip 1 is back grinded to reduce the chip thickness, and the semiconductor chip 1 and the first insulating film 2 are etched from the back surface side of the semiconductor chip 1 along the boundary S to form an opening. A part of the first wiring 3 and a part of the resin 4 are exposed.
【0033】 0033
本発明の特徴は、従来例に見られるように支持材に高価なガラス基板を用いるのではなく、低コストな別材料を用いることである。 A feature of the present invention is that instead of using an expensive glass substrate as a support material as seen in conventional examples, another low-cost material is used. 本実施形態では、フィルム材5aを支持材として用いた例を開示したが、再生シリコン基板を用いたものであってもよい。 In the present embodiment, an example in which the film material 5a is used as the support material has been disclosed, but a recycled silicon substrate may be used.
【0034】 0034
図3参照:第3工程。 See Figure 3: Third step.
【0035】 0035.
次に、前記開口部を含めた半導体チップ1の裏面に第2の絶縁膜6を形成する。 Next, a second insulating film 6 is formed on the back surface of the semiconductor chip 1 including the opening.
【0036】 0036
図4参照:第4工程。 See FIG. 4: Fourth step.
【0037】 0037
その後、第2の絶縁膜6の表面にレジスト7を塗布し、露光・現像して、所望のパターニング処理を行った後に、当該レジスト7をマスクとして異方性エッチングを行う。 Then, the resist 7 is applied to the surface of the second insulating film 6, exposed and developed, a desired patterning process is performed, and then anisotropic etching is performed using the resist 7 as a mask. これにより、第2の絶縁膜6はエッチングされて、開口部Aが形成される。 As a result, the second insulating film 6 is etched to form the opening A. 当該開口部Aの径をd2とする。 Let the diameter of the opening A be d2. ここで、径d2は図1の距離d1よりも大きく形成する。 Here, the diameter d2 is formed larger than the distance d1 in FIG. また、境界Sは当該開口部Aの略中央に配置されるように形成する。 Further, the boundary S is formed so as to be arranged substantially in the center of the opening A.
【0038】 [0038]
図5(a)、(b)参照:第5工程。 See FIGS. 5 (a) and 5 (b): Step 5.
【0039】 [0039]
そして、レジスト7を除去した後、第2の絶縁膜6上の所望位置に緩衝部材8を形成する。 Then, after removing the resist 7, the buffer member 8 is formed at a desired position on the second insulating film 6. その後、前記緩衝部材8の表面、第2の絶縁膜6の表面、第1の配線3の露出面、樹脂4の露出面を含めたチップ裏面にスパッタ法を用いてアルミニウム、アルミニウム合金または銅を形成し、後工程の配線パターニング処理を経て第2の配線9を形成する(図5(a)参照)。 After that, aluminum, aluminum alloy or copper is applied to the surface of the shock absorber 8, the surface of the second insulating film 6, the exposed surface of the first wiring 3, and the exposed surface of the resin 4 by a sputtering method. It is formed, and a second wiring 9 is formed through a wiring patterning process in a subsequent step (see FIG. 5A).
【0040】 0040
ここで、第1の配線3と第2の配線9との接触面積は10〜数100μm程度となるように形成する。 Here, the contact area between the first wiring 3 and the second wiring 9 is formed to be about 10 to several 100 μm. これは、従来例(図17)のような第1の配線107の側部部分での2〜3μm程度の接触に比べて広い面接触である。 This is a wider surface contact than the contact of about 2 to 3 μm at the side portion of the first wiring 107 as in the conventional example (FIG. 17). 従って、外部からストレス等が加わった場合でも、その接続面が離間し、断線する可能性が低減され、接続信頼性が向上する。 Therefore, even when stress or the like is applied from the outside, the connection surfaces are separated from each other, the possibility of disconnection is reduced, and the connection reliability is improved.
【0041】 [0041]
次に、レジスト10を第2の配線9上に塗布し、露光・現像してパターニング処理を行い、境界Sが中央にくるように開口部Bを設ける。 Next, the resist 10 is applied onto the second wiring 9, exposed and developed to perform patterning processing, and the opening B is provided so that the boundary S is in the center. ここで、当該開口部Bの径をd3とする。 Here, the diameter of the opening B is d3. このとき、径d3は図4の径d2よりも小さくなり、径d3と図1の距離d1とはほぼ一致するように形成する(図5(b)参照)。 At this time, the diameter d3 is smaller than the diameter d2 in FIG. 4, and the diameter d3 and the distance d1 in FIG. 1 are formed so as to be substantially the same (see FIG. 5B).
【0042】 [0042]
図6参照:第6工程。 See FIG. 6: Step 6.
【0043】 [0043]
そして、レジスト10をマスクとして、前記アルミニウム、アルミニウム合金または銅を異方性エッチングして第2の配線9をパターニングする。 Then, using the resist 10 as a mask, the aluminum, aluminum alloy, or copper is anisotropically etched to pattern the second wiring 9. これにより、前記第1の配線3にコンタクトする第2の配線9が形成される。 As a result, the second wiring 9 that contacts the first wiring 3 is formed.
【0044】 [0044]
図7参照:第7工程。 See FIG. 7: 7th step.
【0045】 0045
そして、第2の配線9上にNi,Auメッキを施した後に保護膜12(ソルダーマスク)を形成し、所望位置に開口部を形成してスクリーン印刷等により半田を塗布して、第2の配線9上に導電端子13を形成する。 Then, after plating Ni and Au on the second wiring 9, a protective film 12 (solder mask) is formed, an opening is formed at a desired position, and solder is applied by screen printing or the like to apply the second wiring. A conductive terminal 13 is formed on the wiring 9. この導電端子13は、例えばボール形状を成す。 The conductive terminal 13 has a ball shape, for example.
【0046】 [0046]
図8参照:第8工程。 See FIG. 8: Eighth step.
【0047】 [0047]
続いて、境界Sに沿ってダイシングすることで、個々の半導体装置(図8)に分割される。 Subsequently, by dicing along the boundary S, it is divided into individual semiconductor devices (FIG. 8).
【0048】 0048
以上より、本実施形態では支持材として、フィルム材5a又は再生シリコン基板を用いることで、高価なガラス基板を使わずに、低コストな半導体装置が実現できる。 From the above, by using the film material 5a or the recycled silicon substrate as the support material in the present embodiment, a low-cost semiconductor device can be realized without using an expensive glass substrate.
【0049】 [0049]
次に本発明の第2の実施形態(図9乃至図10)について説明する。 Next, a second embodiment of the present invention (FIGS. 9 to 10) will be described.
【0050】 0050
基本的に本実施形態は第1の実施形態の製造方法(図1乃至図7)と同じであるが、樹脂4を形成しない点で第1の実施形態と相違する。 This embodiment is basically the same as the manufacturing method of the first embodiment (FIGS. 1 to 7), but differs from the first embodiment in that the resin 4 is not formed.
【0051】 0051
以下、当該相違点を中心に第1の実施形態を参照しながら説明する。 Hereinafter, the differences will be described with reference to the first embodiment.
【0052】 [0052]
本実施形態では、図1の工程の後、第1の配線3及び第1の絶縁膜2を含む半導体ウエハ上に絶縁物5bを形成する。 In the present embodiment, after the step of FIG. 1, the insulator 5b is formed on the semiconductor wafer including the first wiring 3 and the first insulating film 2. この絶縁物5bは、透明で膜厚が500μm程度のものであり、例えばスクリーン印刷法によって形成された透明エポキシ材又は透明ポリイミド材である(図9参照)。 The insulator 5b is transparent and has a film thickness of about 500 μm, and is, for example, a transparent epoxy material or a transparent polyimide material formed by a screen printing method (see FIG. 9).
【0053】 [0053]
スクリーン印刷法とは、所望位置に予め開口させたマスクを用意し、半導体装置上に被せた当該マスク上から透明エポキシ材等を塗布することで、当該所望位置のみに透明エポキシ材等を形成する方法である。 In the screen printing method, a mask that has been opened in advance at a desired position is prepared, and a transparent epoxy material or the like is applied onto the mask that is placed on the semiconductor device to form a transparent epoxy material or the like only at the desired position. The method.
【0054】 0054
その後は、第1の実施形態の図3乃至図7の工程を経て、図10に示す半導体装置が完成する。 After that, the semiconductor device shown in FIG. 10 is completed through the steps of FIGS. 3 to 7 of the first embodiment.
【0055】 0055
以上より、本実施形態では支持材として、透明エポキシ材又は透明ポリイミド材を用いることで、高価なガラス基板を使わずに、低コストな半導体装置が実現できる。 From the above, by using a transparent epoxy material or a transparent polyimide material as the support material in the present embodiment, a low-cost semiconductor device can be realized without using an expensive glass substrate.
【0056】 0056
次に本発明の第3の実施形態(図11乃至図12)について説明する。 Next, a third embodiment of the present invention (FIGS. 11 to 12) will be described.
【0057】 [0057]
本実施形態では支持材として酸化膜5cを採用する点で、上述した第1、第2の実施形態と相違する。 This embodiment differs from the first and second embodiments described above in that the oxide film 5c is used as the support material.
【0058】 0058.
当該酸化膜5cは、例えば低圧CVD法によって、又はプラズマCVD法によって、数μm〜数百μm程度の膜厚を有するように形成される。 The oxide film 5c is formed to have a film thickness of about several μm to several hundred μm by, for example, a low pressure CVD method or a plasma CVD method. この結果、当該酸化膜5cの表面には、凹凸が形成される(図11(a)参照)。 As a result, irregularities are formed on the surface of the oxide film 5c (see FIG. 11A). また、離間した第1の配線3の間には、酸化膜5cを完全に充填させる。 Further, the oxide film 5c is completely filled between the separated first wirings 3.
【0059】 [0059]
その後、当該酸化膜5cをCMP(chemical mechanical polishing)法等を用いて研磨して、当該凹凸を平坦化する(図11(b)参照)。 Then, the oxide film 5c is polished by a CMP (chemical mechanical polishing) method or the like to flatten the unevenness (see FIG. 11B). 尚、酸化膜5cの表面をエッチングして、凹凸を平坦化するものであっても良い。 The surface of the oxide film 5c may be etched to flatten the unevenness.
【0060】 [0060]
その後は、第1の実施形態の図3乃至図7の工程を経て、図12に示す半導体装置が完成する。 After that, the semiconductor device shown in FIG. 12 is completed through the steps of FIGS. 3 to 7 of the first embodiment.
【0061】 [0061]
以上より、本実施形態では支持材として、酸化膜5cを形成し、その後CMP処理して平坦化することで、高価なガラス基板を使わずに、低コストな半導体装置が実現できる。 From the above, in the present embodiment, by forming an oxide film 5c as a support material and then performing CMP treatment to flatten it, a low-cost semiconductor device can be realized without using an expensive glass substrate.
【0062】 [0062]
上述したように、本発明の第1乃至第3の実施形態の共通した効果として、以下のものが挙げられる。 As described above, the following are common effects of the first to third embodiments of the present invention.
【0063】 [0063]
▲1▼本発明は、チップ表面側の支持材してフィルム材5a、再生シリコン基板、絶縁物5b、酸化膜5cを用いることで、様々なニーズに適応した安価な半導体装置が実現できる。 (1) According to the present invention, by using a film material 5a, a recycled silicon substrate, an insulator 5b, and an oxide film 5c as a support material on the chip surface side, an inexpensive semiconductor device suitable for various needs can be realized. また、ガラス基板を用いないため、製造プロセス、例えばダイシング工程時においてガラスの欠け等が発生することがない。 Further, since the glass substrate is not used, the glass is not chipped during the manufacturing process, for example, the dicing process. また、チップ裏面側のガラス基板も使用しないため、更に低コスト化が図れる。 Further, since the glass substrate on the back surface side of the chip is not used, the cost can be further reduced.
【0064】 [0064]
▲2▼従来例の図15に見られるような逆V字型溝を形成するノッチング工程に代わって、図2に示すように異方性エッチングを行うことで、ノッチング工程による第1の配線部の切削面への異物混入やコンタミネーション(汚染)が生成する等のトラブルを回避できる。 (2) Instead of the notching step of forming the inverted V-shaped groove as seen in FIG. 15 of the conventional example, the first wiring portion by the notching step is performed by performing anisotropic etching as shown in FIG. It is possible to avoid troubles such as foreign matter mixing on the cutting surface and contamination (contamination).
▲3▼第1の配線3と第2の配線9との接触面積が広くとれるため、半導体装置の外部からのストレスに対して、両配線が離間し、断線する可能性を著しく低減でき、接続信頼性が向上する。 (3) Since the contact area between the first wiring 3 and the second wiring 9 can be widened, the possibility that both wirings are separated from each other due to stress from the outside of the semiconductor device and the wiring is broken can be significantly reduced, and the connection can be made. Improves reliability.
【0065】 [0065]
【発明の効果】 【The invention's effect】
本発明によれば、従来技術にみられるような高価なガラス基板に代えて安価な材料から成る支持材を用いているため、低コスト化が図れる。 According to the present invention, since a support material made of an inexpensive material is used instead of the expensive glass substrate as seen in the prior art, the cost can be reduced.
【0066】 [0066]
また、逆V字型溝を形成するノッチング工程に代えて、異方性エッチングを行うことで、ノッチング工程による第1の配線部の切削面への異物混入やコンタミネーション(汚染)が生成する等のトラブルを回避できる。 Further, by performing anisotropic etching instead of the notching step of forming the inverted V-shaped groove, foreign matter is mixed into the cutting surface of the first wiring portion by the notching step and contamination (contamination) is generated. Trouble can be avoided.
【0067】 [0067]
更に、第1の配線と第2の配線とが広面積で接触できるため、外部からのストレス等によりその接続面が離間し、断線する可能性は著しく低減し、両者の接続信頼性が向上する。 Further, since the first wiring and the second wiring can come into contact with each other in a wide area, the possibility that the connection surface is separated due to external stress or the like and the wire is broken is remarkably reduced, and the connection reliability between the two is improved. ..
【図面の簡単な説明】 [Simple explanation of drawings]
【図1】本発明に係る第1の実施形態の製造方法を示す断面図である。 FIG. 1 is a cross-sectional view showing a manufacturing method of the first embodiment according to the present invention.
【図2】本発明に係る第1の実施形態の製造方法を示す断面図である。 FIG. 2 is a cross-sectional view showing a manufacturing method of the first embodiment according to the present invention.
【図3】本発明に係る第1の実施形態の製造方法を示す断面図である。 FIG. 3 is a cross-sectional view showing a manufacturing method of the first embodiment according to the present invention.
【図4】本発明に係る第1の実施形態の製造方法を示す断面図である。 FIG. 4 is a cross-sectional view showing a manufacturing method of the first embodiment according to the present invention.
【図5】本発明に係る第1の実施形態の製造方法を示す断面図である。 FIG. 5 is a cross-sectional view showing a manufacturing method of the first embodiment according to the present invention.
【図6】本発明に係る第1の実施形態の製造方法を示す断面図である。 FIG. 6 is a cross-sectional view showing a manufacturing method of the first embodiment according to the present invention.
【図7】本発明に係る第1の実施形態の製造方法を示す断面図である。 FIG. 7 is a cross-sectional view showing a manufacturing method of the first embodiment according to the present invention.
【図8】本発明に係る第1の実施形態の製造方法を示す断面図である。 FIG. 8 is a cross-sectional view showing a manufacturing method of the first embodiment according to the present invention.
【図9】本発明に係る第2の実施形態の製造方法を示す断面図である。 FIG. 9 is a cross-sectional view showing a manufacturing method of a second embodiment according to the present invention.
【図10】本発明に係る第2の実施形態の製造方法を示す断面図である。 FIG. 10 is a cross-sectional view showing a manufacturing method of a second embodiment according to the present invention.
【図11】本発明に係る第3の実施形態の製造方法を示す断面図である。 FIG. 11 is a cross-sectional view showing a manufacturing method of a third embodiment according to the present invention.
【図12】本発明に係る第3の実施形態の製造方法を示す断面図である。 FIG. 12 is a cross-sectional view showing a manufacturing method of a third embodiment according to the present invention.
【図13】従来の半導体装置の製造方法を示す断面図である。 FIG. 13 is a cross-sectional view showing a method of manufacturing a conventional semiconductor device.
【図14】従来の半導体装置の製造方法を示す断面図である。 FIG. 14 is a cross-sectional view showing a method of manufacturing a conventional semiconductor device.
【図15】従来の半導体装置の製造方法を示す断面図である。 FIG. 15 is a cross-sectional view showing a method of manufacturing a conventional semiconductor device.
【図16】従来の半導体装置の製造方法を示す断面図である。 FIG. 16 is a cross-sectional view showing a method of manufacturing a conventional semiconductor device.
【図17】従来の半導体装置の製造方法を示す断面図である。 FIG. 17 is a cross-sectional view showing a method of manufacturing a conventional semiconductor device.
【図18】従来の半導体装置を示す斜視図である。 FIG. 18 is a perspective view showing a conventional semiconductor device. [0001] [0001]
TECHNICAL FIELD OF THE INVENTION TECHNICAL FIELD OF THE Invention
The present invention relates to a BGA (Ball Grid Array) type semiconductor device having ball-shaped conductive terminals. The present invention relates to a BGA (Ball Grid Array) type semiconductor device having ball-shaped conductive terminals.
[0002] [0002]
[Prior art] [Prior art]
In recent years, CSP (Chip Size Package) has attracted attention as a three-dimensional packaging technology and a new packaging technology. The CSP refers to a small package having an outer size substantially the same as the outer size of a semiconductor chip. In recent years, CSP (Chip Size Package) has attracted attention as a three-dimensional packaging technology and a new packaging technology. The CSP refers to a small package having an outer size substantially the same as the outer size of a semiconductor chip.
[0003] [0003]
Conventionally, there has been a BGA type CSP semiconductor device. In the semiconductor device, a plurality of ball-shaped conductive terminals made of a metal member such as solder are arranged in a grid on one main surface of a package substrate, and are bonded to a semiconductor chip mounted on another surface of the substrate to form a package. Is what you do. Then, when incorporated into an electronic device, each conductive terminal is thermally melted into a wiring pattern on a printed board, and the semiconductor chip and an external circuit mounted on the printed board are simultaneously electrically connected. Conventionally, there has been a BGA type CSP semiconductor device. In the semiconductor device, a plurality of ball-shaped conductive terminals made of a metal member such as solder are arranged in a grid on one main surface of a package substrate, and are bonded To a semiconductor chip mounted on another surface of the substrate to form a package. Is what you do. Then, when incorporated into an electronic device, each conductive terminal is similarly melted into a wiring pattern on a printed board, and the semiconductor chip and an external circuit mounted on the printed board are simultaneously semiconductor connected.
[0004] [0004]
Such a BGA type semiconductor device can be provided with a larger number of connection terminals than other CSP type semiconductor devices such as SOP (Small Outline Package) and QFP (Quad Flat Package) having lead pins protruding from the side surface. It has the advantage that it can be miniaturized. This BGA type semiconductor device has recently been adopted also in the field of CCD image sensors, and is used as an image sensor chip of a digital camera mounted on a mobile phone which has a strong demand for miniaturization. Such a BGA type semiconductor device can be provided with a larger number of connection terminals than other CSP type semiconductor devices such as SOP (Small Outline Package) and QFP (Quad Flat Package) having lead pins enabling from the side surface. It has the advantage This BGA type semiconductor device has recently been adopted also in the field of CCD image sensors, and is used as an image sensor chip of a digital camera mounted on a mobile phone which has a strong demand for miniaturization.
[0005] [0005]
FIGS. 18A and 18B show a schematic configuration of a conventional BGA type semiconductor device, and FIGS. 18A and 18B are perspective views projected from the front side and the back side of the semiconductor device, respectively. 18A and 18B show a schematic configuration of a conventional BGA type semiconductor device, and FIGS. 18A and 18B are perspective views projected from the front side and the back side of the semiconductor device, respectively.
[0006] [0006]
The BGA type semiconductor device 101 is a CCD image sensor chip, and a semiconductor chip 104 is sealed between first and second glass substrates 102 and 103 via an epoxy resin 105. On one main surface of the second glass substrate 103, that is, on the back surface of the semiconductor device 101, a plurality of ball-shaped conductive terminals 106 are arranged in a lattice. The conductive terminal 106 is connected to the semiconductor chip 104 via the wiring 107. The BGA type semiconductor device 101 is a CCD image sensor chip, and a semiconductor chip 104 is sealed between first and second glass integrally 102 and 103 via an epoxy resin 105. On one main surface of the second glass substrate 103, that is, on The back surface of the semiconductor device 101, a plurality of ball-shaped conductive terminals 106 are arranged in a lattice. The conductive terminal 106 is connected to the semiconductor chip 104 via the wiring 107.
[0007] [0007]
Next, the manufacturing process of the semiconductor device 101 will be sequentially described with reference to FIGS. Next, the manufacturing process of the semiconductor device 101 will be sequentially described with reference to FIGS.
[0008] [0008]
Referring to FIG. 13, a semiconductor wafer having a plurality of semiconductor chips 104 is prepared, and a first wiring 107 is formed on the surface thereof via an insulating film 108. The first wiring 107 is formed so as to straddle a boundary (scribe line) S for dividing the semiconductor chip 104 into each semiconductor chip 104 through a dicing process in a later process. 13, a semiconductor wafer having a plurality of semiconductor chips 104 is prepared, and a first wiring 107 is formed on the surface thereof via an insulating film 108. The first wiring 107 is formed so as to straddle a boundary (scribe) line) S for dividing the semiconductor chip 104 into each semiconductor chip 104 through a dicing process in a later process.
[0009] [0009]
Subsequently, the first glass substrate 102 is adhered to the surface of the semiconductor chip 104 on which the first wiring 107 is formed, using a transparent epoxy resin 105. Then, the semiconductor chip 104 is back-ground to reduce the chip thickness, and is etched along the boundary S from the back surface side of the semiconductor chip 104 to expose the first wiring 107. Thus, the first glass substrate 102 is adhered to the surface of the semiconductor chip 104 on which the first wiring 107 is formed, using a transparent epoxy resin 105. Then, the semiconductor chip 104 is back-ground to reduce the chip thickness, and is plated along the boundary S from the back surface side of the semiconductor chip 104 to expose the first wiring 107.
[0010] [0010]
Referring to FIG. 14, subsequently, an epoxy resin 105 is filled so as to cover the etched portion and the exposed portion of the first wiring 107, and the resin 105 is used as an adhesive to form a second glass on the back surface of the semiconductor chip 104. The substrate 103 is bonded. 14, subsequently, an epoxy resin 105 is filled so as to cover the semiconductor portion and the exposed portion of the first wiring 107, and the resin 105 is used as an adhesive to form a second glass on the back surface of the semiconductor chip 104. The substrate 103 is bonded.
[0011] [0011]
See FIG. 15: Next, notching (cutting using a tool such as a saw from the back surface of the chip) is performed on the back surface side of the semiconductor device along the boundary S, for example, to form a V-shaped groove. . At this time, the notching is performed to such an extent that the first wiring 107 is divided, and a part (partition section) of the first wiring 107 is exposed on the notched surface. See FIG. 15: Next, notching (cutting using a tool such as a saw from the back surface of the chip) is performed on the back surface side of the semiconductor device along the boundary S, for example, to form a V-shaped groove .. At this time, the notching is performed to such an extent that the first wiring 107 is divided, and a part (partition section) of the first wiring 107 is exposed on the notched surface.
[0012] [0012]
FIG. 16: Subsequently, an aluminum layer is formed so as to cover the second glass substrate 103 and the cut surface (V-shaped groove) formed by notching. Thereby, the exposed surface of the first wiring 107 is connected to the aluminum layer. After that, the aluminum layer is patterned so as to have a predetermined wiring pattern, and the second wiring 110 is formed. FIG. 16: therefore, an aluminum layer is formed so as to cover the second glass substrate 103 and the cut surface (V-shaped groove) formed by notching. Thus, the exposed surface of the first wiring 107 is connected to the aluminum layer After that, the aluminum layer is patterned so as to have a predetermined wiring pattern, and the second wiring 110 is formed.
[0013] [0013]
Referring to FIG. 17, a protection film (solder mask) (not shown) is formed on the second wiring 110, and the ball-shaped conductive terminals 106 formed of solder or the like are formed at desired positions. Subsequently, dicing is performed along the boundary S. Thus, the conventional BGA type semiconductor device 101 shown in FIG. 18 is completed. 17, a protection film (solder mask) (not shown) is formed on the second wiring 110, and the ball-shaped conductive terminals 106 formed of solder or the like are formed at desired positions. Thus, dicing is performed along the boundary S. Thus, the conventional BGA type semiconductor device 101 shown in FIG. 18 is completed.
[0014] [0014]
[Patent Document 1] [Patent Document 1]
Japanese Unexamined Patent Publication No. 2002-512436 Japanese Unexamined Patent Publication No. 2002-512436
[Problems to be solved by the invention] [Problems to be solved by the invention]
However, in the above-mentioned BGA type semiconductor device 101 and its manufacturing process, the following problems exist. However, in the above-mentioned BGA type semiconductor device 101 and its manufacturing process, the following problems exist.
[0016] [0016]
(1) The conventional BGA type semiconductor device 101 has two glass substrates (a first glass substrate 102 and a second glass substrate 103) on the front side and the back side of the semiconductor chip 104 as support materials. Glass materials are relatively expensive, and a semiconductor device having a supporting material using an inexpensive material has been desired. In addition, the use of a glass substrate has a problem that particles are easily generated in a manufacturing process. (1) The conventional BGA type semiconductor device 101 has two glass integrally (a first glass substrate 102 and a second glass substrate 103) on the front side and the back side of the semiconductor chip 104 as support materials. Glass materials are relatively expensive, And a semiconductor device having a supporting material using an inexpensive material has been desired. In addition, the use of a glass substrate has a problem that particles are easily generated in a manufacturing process.
[0017] [0017]
{Circle around (2)} In FIG. 15 of the above manufacturing process, notching is performed to form an inverted V-shaped groove. As a result, an abnormality (for example, entry of foreign matter or generation of contamination (contamination) or the like) has occurred in the cut cross section at the end of the first wiring 107. {Circle around (2)} In FIG. 15 of the above manufacturing process, notching is performed to form an inverted V-shaped groove. As a result, an abnormality (for example, entry of foreign matter or generation of contamination (contamination)) or the like) has occurred in the cut cross section at the end of the first wiring 107.
[0018] [0018]
{Circle around (3)} In FIG. 17, the contact surface between the first wiring 107 and the second wiring 110 is only about 2 to 3 μm, and is a so-called point contact. However, there is a possibility that the connection surfaces may be separated and the wires may be disconnected, and there is a concern about connection reliability. {Circle around (3)} In FIG. 17, the contact surface between the first wiring 107 and the second wiring 110 is only about 2 to 3 μm, and is a so-called point contact. However, there is a possibility that the connection surfaces may be separated and the wires may be disconnected, and there is a concern about connection reliability.
[0019] [0019]
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and provides a BGA type semiconductor device that is reduced in cost by using a supporting material instead of a glass substrate without performing notching. In addition, the contact surface between the first wiring and the second wiring is increased, and the reliability in the connection process is improved. MUST OF THE FIGURE The present invention has been made in view of the above problems, and provides a BGA type semiconductor device that is reduced in cost by using a supporting material instead of a glass substrate without performing notching. In addition, the contact surface between the first wiring and the second wiring is increased, and the reliability in the connection process is improved.
[0020] [0020]
[Means for Solving the Problems] [Means for Solving the Problems]
In the method of manufacturing a semiconductor device according to the present invention, a step of forming a first wiring on a semiconductor chip via a first insulating film so as to have a predetermined separation distance, and the semiconductor including the first wiring A step of bonding a support material on the chip via an adhesive, a step of exposing the first wiring and the adhesive filled in the space by etching the back surface of the semiconductor chip, and a step of exposing the semiconductor chip Forming a second insulating film on the back surface and the etching location, forming a second wiring contacting with the first wiring after etching a desired position of the second insulating film; Forming a conductive terminal on the second wiring, and dicing along the separated position of the first wiring, wherein the support material is a film material or a recycled silicon substrate. That. In the method of manufacturing a semiconductor device according to the present invention, a step of forming a first wiring on a semiconductor chip via a first insulating film so as to have a predetermined separation distance, and the semiconductor including the first wiring A step of bonding a support material on the chip via an adhesive, a step of exposing the first wiring and the adhesive filled in the space by joining the back surface of the semiconductor chip, and a step of exposing the semiconductor chip Forming a second insulating film on the back surface and the transmitting location, forming a second wiring contacting with the first wiring after joining a desired position of the second insulating film; Forming a conductive terminal on the second wiring, and dicing along the separated position of the first wiring, wherein the support material is a film material or a recycled silicon substrate. That.
[0021] [0021]
A step of forming a first wiring on the semiconductor chip via a first insulating film with a certain distance therebetween, and a step of forming a support member made of an insulator on the first wiring. Exposing the first wiring and the support material disposed at the space separated from the first wiring by etching the back surface of the semiconductor chip; and forming a second insulating film on the semiconductor chip and the etching location. Forming a second wiring in contact with the first wiring after etching a desired position of the second insulating film; forming a conductive terminal on the second wiring; Dicing along the separated position. Exposing the first wiring and the support material disposed at the A step of forming a first wiring on the semiconductor chip via a first insulating film with a certain distance similarly, and a step of forming a support member made of an insulator on the first wiring. Forming a second wiring in contact with the first wiring after signaling a desired position of the second insulating space separated from the first wiring by relating the back surface of the semiconductor chip; and forming a second insulating film on the semiconductor chip and the transmitting location. film; forming a conductive terminal on the second wiring; Dicing along the separated position.
[0022] [0022]
Further, the insulator is made of a transparent epoxy material or polyimide material. Further, the insulator is made of a transparent epoxy material or polyimide material.
[0023] [0023]
Forming a first wiring on the semiconductor chip so as to have a fixed distance via a first insulating film; and forming an oxide film on the semiconductor chip including on the first wiring. A step of exposing the first wiring and the oxide film disposed at a location separated from the first wiring by etching the back surface of the semiconductor chip; and forming a second insulating film on the semiconductor chip and the etching location. Forming a second wiring in contact with the first wiring after etching a desired position of the second insulating film; forming a conductive terminal on the second wiring; Dicing along the wiring separation position. Forming a first wiring on the semiconductor chip so as to have a fixed distance via a first insulating film; and forming an oxide film on the semiconductor chip including on the first wiring. A step of exposing the first wiring and the oxide film disposed at a location separated from the first wiring by relating the back surface of the semiconductor chip; and forming a second insulating film on the semiconductor chip and the transmitting location. Forming a second wiring in contact with the first wiring after communicating a desired position of the second insulating film; forming a conductive terminal on the second wiring; Dicing along the wiring separation position.
[0024] [0024]
Further, the oxide film is formed by a low pressure CVD method or a plasma CVD method. Further, the oxide film is formed by a low pressure CVD method or a plasma CVD method.
[0025] [0025]
BEST MODE FOR CARRYING OUT THE INVENTION BEST MODE FOR CARRYING OUT THE Invention
The first to third embodiments of the present invention will be described in detail. Embodiments of the present invention have a common feature in that a semiconductor device is completed without using an expensive glass substrate as a support material as seen in a conventional example. The first to third embodiments of the present invention will be described in detail. Embodiments of the present invention have a common feature in that a semiconductor device is completed without using an expensive glass substrate as a support material as seen in a conventional example.
[0026] [0026]
Hereinafter, the manufacturing method according to the first embodiment of the present invention will be sequentially described with reference to FIGS. Recently, the manufacturing method according to the first embodiment of the present invention will be sequentially described with reference to FIGS.
[0027] [0027]
See FIG. 1: First step. See FIG. 1: First step.
[0028] [0028]
A semiconductor wafer having a plurality of semiconductor chips 1 is prepared. The semiconductor chip 1 is, for example, a CCD image sensor chip or the like. A semiconductor wafer having a plurality of semiconductor chips 1 is prepared. The semiconductor chip 1 is, for example, a CCD image sensor chip or the like.
[0029] [0029]
Subsequently, a first wiring 3 is formed on the semiconductor chip 1 at a predetermined distance d1 so as to cross a boundary (dicing line) S of the semiconductor chip 1 via a first insulating film 2. The first wiring 3 is a metal pad made of, for example, aluminum, an aluminum alloy, or copper, and is electrically connected to a circuit element in the semiconductor chip 1. Since the first wiring 3 extends to the boundary between the plurality of semiconductor chips 1, it is also called an extension pad. Gradually, a first wiring 3 is formed on the semiconductor chip 1 at a predetermined distance d1 so as to cross a boundary (dicing line) S of the semiconductor chip 1 via a first insulating film 2. The first wiring 3 is a metal pad made of, for example, aluminum, an aluminum alloy, or copper, and is electrically connected to a circuit element in the semiconductor chip 1. Since the first wiring 3 extends to the boundary between the plurality of semiconductor chips 1, it is also called an extension pad.
[0030] [0030]
See FIG. 2: Second step. See FIG. 2: Second step.
[0031] [0031]
Subsequently, a transparent epoxy resin 4 is formed on the semiconductor wafer including the first wiring 3 as shown in FIG. Then, a transparent organic film material 5a having a thickness of several hundred μm is attached onto the semiconductor wafer via the resin 4. Here, the resin 4 is an epoxy resin having an adhesive property, and is filled also in a separation area of the first wiring 3 separated by a distance d1. Then, a transparent organic film material 5a having a thickness of several hundred μm is attached onto the semiconductor wafer via the resin 4. Here, a transparent epoxy resin 4 is formed on the semiconductor wafer including the first wiring 3 as shown in FIG. , the resin 4 is an epoxy resin having an adhesive property, and is filled also in a separation area of ​​the first wiring 3 separated by a distance d1.
[0032] [0032]
Then, the semiconductor chip 1 is back-ground to reduce the chip thickness, and the semiconductor chip 1 and the first insulating film 2 are etched along the boundary S from the back surface side of the semiconductor chip 1 to form an opening, A part of the first wiring 3 and a part of the resin 4 are exposed. Then, the semiconductor chip 1 is back-ground to reduce the chip thickness, and the semiconductor chip 1 and the first insulating film 2 are sintered along the boundary S from the back surface side of the semiconductor chip 1 to form an opening, A part of the first wiring 3 and a part of the resin 4 are exposed.
[0033] [0033]
The feature of the present invention is not to use an expensive glass substrate as a support material as in the conventional example, but to use another low-cost material. In the present embodiment, an example in which the film material 5a is used as a support material is disclosed, but a material using a recycled silicon substrate may be used. The feature of the present invention is not to use an expensive glass substrate as a support material as in the conventional example, but to use another low-cost material. In the present embodiment, an example in which the film material 5a is used as a support material is disclosed, but a material using a recycled silicon substrate may be used.
[0034] [0034]
See FIG. 3: Third step. See FIG. 3: Third step.
[0035] [0035]
Next, a second insulating film 6 is formed on the back surface of the semiconductor chip 1 including the opening. Next, a second insulating film 6 is formed on the back surface of the semiconductor chip 1 including the opening.
[0036] [0036]
See FIG. 4: Fourth step. See FIG. 4: Fourth step.
[0037] [0037]
Thereafter, a resist 7 is applied to the surface of the second insulating film 6, exposed and developed, and a desired patterning process is performed. Then, anisotropic etching is performed using the resist 7 as a mask. Thereby, the second insulating film 6 is etched, and the opening A is formed. The diameter of the opening A is d2. Here, the diameter d2 is formed to be larger than the distance d1 in FIG. Further, the boundary S is formed so as to be disposed substantially at the center of the opening A. Then, anisotropic etching is performed using the resist 7 as a mask. Thus, the second insulating film 6 is applied to the surface of the second insulating film 6, exposed and developed, and a desired patterning process is performed. Is etched, and the opening A is formed. The diameter of the opening A is d2. Here, the diameter d2 is formed to be larger than the distance d1 in FIG. Further, the boundary S is formed so as to be disposed substantially at the center of the opening A.
[0038] [0038]
5 (a) and 5 (b): Fifth step. 5 (a) and 5 (b): Fifth step.
[0039] [0039]
Then, after removing the resist 7, a buffer member 8 is formed at a desired position on the second insulating film 6. Then, aluminum, aluminum alloy or copper is sputtered on the back surface of the chip including the surface of the buffer member 8, the surface of the second insulating film 6, the exposed surface of the first wiring 3, and the exposed surface of the resin 4 by using a sputtering method. Then, the second wiring 9 is formed through a wiring patterning process in a later step (see FIG. 5A). Then, after removing the resist 7, a buffer member 8 is formed at a desired position on the second insulating film 6. Then, aluminum, aluminum alloy or copper is sputtered on the back surface of the chip including the surface of the buffer member 8 , the surface of the second insulating film 6, the exposed surface of the first wiring 3, and the exposed surface of the resin 4 by using a sputtering method. Then, the second wiring 9 is formed through a wiring patterning process in a later step (see FIG. 5A).
[0040] [0040]
Here, the contact area between the first wiring 3 and the second wiring 9 is formed so as to be about 10 to several 100 μm. This is a wider surface contact than a contact of about 2 to 3 μm at the side portion of the first wiring 107 as in the conventional example (FIG. 17). Therefore, even when stress or the like is applied from the outside, the connection surfaces are separated and the possibility of disconnection is reduced, and connection reliability is improved. Here, the contact area between the first wiring 3 and the second wiring 9 is formed so as to be about 10 to several 100 μm. This is a wider surface contact than a contact of about 2 to 3 μm at the side portion of the first wiring 107 as in the conventional example (FIG. 17). Therefore, even when stress or the like is applied from the outside, the connection surfaces are separated and the possibility of disconnection is reduced, and connection reliability is improved.
[0041] [0041]
Next, a resist 10 is applied on the second wiring 9, exposed and developed to perform a patterning process, and an opening B is provided so that a boundary S is located at the center. Here, the diameter of the opening B is d3. At this time, the diameter d3 is smaller than the diameter d2 in FIG. 4, and the diameter d3 is formed so as to substantially coincide with the distance d1 in FIG. 1 (see FIG. 5B). Next, a resist 10 is applied on the second wiring 9, exposed and developed to perform a patterning process, and an opening B is provided so that a boundary S is located at the center. Here, the diameter of the opening B is d3. At this time, the diameter d3 is smaller than the diameter d2 in FIG. 4, and the diameter d3 is formed so as to substantially coincide with the distance d1 in FIG. 1 (see FIG. 5B).
[0042] [0042]
See FIG. 6: sixth step. See FIG. 6: sixth step.
[0043] [0043]
Then, using the resist 10 as a mask, the second wiring 9 is patterned by anisotropically etching the aluminum, aluminum alloy or copper. As a result, a second wiring 9 contacting the first wiring 3 is formed. Then, using the resist 10 as a mask, the second wiring 9 is patterned by anisotropically etching the aluminum, aluminum alloy or copper. As a result, a second wiring 9 contacting the first wiring 3 is formed.
[0044] [0044]
See FIG. 7: seventh step. See FIG. 7: seventh step.
[0045] [0045]
Then, after applying Ni and Au plating on the second wiring 9, a protective film 12 (solder mask) is formed, an opening is formed at a desired position, and solder is applied by screen printing or the like. The conductive terminal 13 is formed on the wiring 9. The conductive terminal 13 has, for example, a ball shape. Then, after applying Ni and Au plating on the second wiring 9, a protective film 12 (solder mask) is formed, an opening is formed at a desired position, and solder is applied by screen printing or the like. The conductive terminal 13 is formed on the wiring 9. The conductive terminal 13 has, for example, a ball shape.
[0046] [0046]
See FIG. 8: Eighth step. See FIG. 8: Eighth step.
[0047] [0047]
Subsequently, the semiconductor device is divided into individual semiconductor devices (FIG. 8) by dicing along the boundary S. Gradually, the semiconductor device is divided into individual semiconductor devices (FIG. 8) by dicing along the boundary S.
[0048] [0048]
As described above, in the present embodiment, by using the film material 5a or the recycled silicon substrate as the support material, a low-cost semiconductor device can be realized without using an expensive glass substrate. As described above, in the present embodiment, by using the film material 5a or the recycled silicon substrate as the support material, a low-cost semiconductor device can be realized without using an expensive glass substrate.
[0049] [0049]
Next, a second embodiment (FIGS. 9 and 10) of the present invention will be described. Next, a second embodiment (FIGS. 9 and 10) of the present invention will be described.
[0050] [0050]
This embodiment is basically the same as the manufacturing method of the first embodiment (FIGS. 1 to 7), but differs from the first embodiment in that the resin 4 is not formed. This embodiment is basically the same as the manufacturing method of the first embodiment (FIGS. 1 to 7), but differs from the first embodiment in that the resin 4 is not formed.
[0051] [0051]
Hereinafter, the difference will be mainly described with reference to the first embodiment. Embodied, the difference will be mainly described with reference to the first embodiment.
[0052] [0052]
In the present embodiment, after the step of FIG. 1, an insulator 5b is formed on a semiconductor wafer including the first wiring 3 and the first insulating film 2. The insulator 5b is transparent and has a thickness of about 500 μm, and is, for example, a transparent epoxy material or a transparent polyimide material formed by a screen printing method (see FIG. 9). In the present embodiment, after the step of FIG. 1, an insulator 5b is formed on a semiconductor wafer including the first wiring 3 and the first insulating film 2. The insulator 5b is transparent and has a thickness of about 500 μm, and is , for example, a transparent polyimide material or a transparent polyimide material formed by a screen printing method (see FIG. 9).
[0053] [0053]
The screen printing method is to prepare a mask previously opened at a desired position and apply a transparent epoxy material or the like from the mask over the semiconductor device to form a transparent epoxy material or the like only at the desired position. Is the way. The screen printing method is to prepare a mask previously opened at a desired position and apply a transparent epoxy material or the like from the mask over the semiconductor device to form a transparent epoxy material or the like only at the desired position. Is the way.
[0054] [0054]
Thereafter, the semiconductor device shown in FIG. 10 is completed through the steps of FIGS. 3 to 7 of the first embodiment. 10 is completed through the steps of FIGS. 3 to 7 of the first embodiment.
[0055] [0055]
As described above, in this embodiment, by using a transparent epoxy material or a transparent polyimide material as the support material, a low-cost semiconductor device can be realized without using an expensive glass substrate. As described above, in this embodiment, by using a transparent polyimide material or a transparent polyimide material as the support material, a low-cost semiconductor device can be realized without using an expensive glass substrate.
[0056] [0056]
Next, a third embodiment (FIGS. 11 and 12) of the present invention will be described. Next, a third embodiment (FIGS. 11 and 12) of the present invention will be described.
[0057] [0057]
This embodiment is different from the above-described first and second embodiments in that an oxide film 5c is used as a support material. This embodiment is different from the above-described first and second embodiments in that an oxide film 5c is used as a support material.
[0058] [0058]
The oxide film 5c is formed to have a thickness of about several μm to several hundred μm by, for example, a low-pressure CVD method or a plasma CVD method. As a result, irregularities are formed on the surface of the oxide film 5c (see FIG. 11A). The oxide film 5c is completely filled between the separated first wirings 3. The oxide film 5c is formed to have a thickness of about several μm to several hundred μm by, for example, a low-pressure CVD method or a plasma CVD method. As a result, irregularities are formed on the surface of the oxide film 5c (see FIG. 11A). The oxide film 5c is completely filled between the separated first wirings 3.
[0059] [0059]
After that, the oxide film 5c is polished by a CMP (chemical mechanical polishing) method or the like to flatten the irregularities (see FIG. 11B). The surface of the oxide film 5c may be etched to flatten the irregularities. After that, the oxide film 5c is polished by a CMP (chemical mechanical polishing) method or the like to flatten the irregularities (see FIG. 11B). The surface of the oxide film 5c may be plated to flatten the irregularities.
[0060] [0060]
Thereafter, the semiconductor device shown in FIG. 12 is completed through the steps of FIGS. 3 to 7 of the first embodiment. 12 is completed through the steps of FIGS. 3 to 7 of the first embodiment.
[0061] [0061]
As described above, in the present embodiment, a low-cost semiconductor device can be realized without using an expensive glass substrate by forming the oxide film 5c as a support material and then planarizing the oxide film 5c by a CMP process. As described above, in the present embodiment, a low-cost semiconductor device can be realized without using an expensive glass substrate by forming the oxide film 5c as a support material and then planarizing the oxide film 5c by a CMP process.
[0062] [0062]
As described above, the following effects are provided as common effects of the first to third embodiments of the present invention. As described above, the following effects are provided as common effects of the first to third embodiments of the present invention.
[0063] [0063]
(1) According to the present invention, an inexpensive semiconductor device adapted to various needs can be realized by using the film material 5a, the recycled silicon substrate, the insulator 5b, and the oxide film 5c as the support material on the chip surface side. Further, since a glass substrate is not used, chipping of the glass does not occur in a manufacturing process, for example, in a dicing step. Further, since the glass substrate on the back side of the chip is not used, the cost can be further reduced. (1) According to the present invention, an inexpensive semiconductor device adapted to various needs can be realized by using the film material 5a, the recycled silicon substrate, the insulator 5b, and the oxide film 5c as the support material on the chip surface side Further, since a glass substrate is not used, chipping of the glass does not occur in a manufacturing process, for example, in a dicing step. Further, since the glass substrate on the back side of the chip is not used, the cost can be further reduced.
[0064] [0064]
{Circle over (2)} Instead of the notching step of forming a reverse V-shaped groove as shown in FIG. 15 of the conventional example, anisotropic etching is performed as shown in FIG. Troubles such as generation of foreign matter and contamination (contamination) on the cutting surface can be avoided. {Circle over (2)} Instead of the notching step of forming a reverse V-shaped groove as shown in FIG. 15 of the conventional example, anisotropic etching is performed as shown in FIG. Troubles such as generation of foreign matter and contamination ( contamination) on the cutting surface can be avoided.
{Circle over (3)} Since the contact area between the first wiring 3 and the second wiring 9 can be made large, the possibility that the two wirings are separated and disconnected due to stress from the outside of the semiconductor device can be significantly reduced. Reliability is improved. {Circle over (3)} Since the contact area between the first wiring 3 and the second wiring 9 can be made large, the possibility that the two wirings are separated and disconnected due to stress from the outside of the semiconductor device can be significantly reduced . Reliability is improved.
[0065] [0065]
【The invention's effect】 [The invention's effect]
According to the present invention, since a support member made of an inexpensive material is used instead of an expensive glass substrate as seen in the related art, cost reduction can be achieved. According to the present invention, since a support member made of an inexpensive material is used instead of an expensive glass substrate as seen in the related art, cost reduction can be achieved.
[0066] [0066]
Also, by performing anisotropic etching in place of the notching step of forming the inverted V-shaped groove, foreign matter is mixed into the cut surface of the first wiring portion due to the notching step, and contamination (contamination) is generated. Trouble can be avoided. Also, by performing anisotropic etching in place of the notching step of forming the inverted V-shaped groove, foreign matter is mixed into the cut surface of the first wiring portion due to the notching step, and contamination (contamination) is generated. Trouble can be avoided.
[0067] [0067]
Further, since the first wiring and the second wiring can be in contact with each other over a wide area, the connection surface is separated by external stress or the like, the possibility of disconnection is significantly reduced, and the connection reliability between the two is improved. . Further, since the first wiring and the second wiring can be in contact with each other over a wide area, the connection surface is separated by external stress or the like, the possibility of disconnection is significantly reduced, and the connection reliability between the two is improved ..
[Brief description of the drawings] [Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a manufacturing method according to a first embodiment of the present invention. FIG. 1 is a cross-sectional view illustrating a manufacturing method according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating a manufacturing method according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view illustrating a manufacturing method according to the first embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating the manufacturing method according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view illustrating the manufacturing method according to the first embodiment of the present invention.
FIG. 4 is a cross-sectional view illustrating the manufacturing method according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view illustrating the manufacturing method according to the first embodiment of the present invention.
FIG. 5 is a sectional view showing the manufacturing method according to the first embodiment of the present invention; FIG. 5 is a sectional view showing the manufacturing method according to the first embodiment of the present invention;
FIG. 6 is a sectional view showing the manufacturing method according to the first embodiment of the present invention; FIG. 6 is a sectional view showing the manufacturing method according to the first embodiment of the present invention;
FIG. 7 is a sectional view showing the manufacturing method according to the first embodiment of the present invention; FIG. 7 is a sectional view showing the manufacturing method according to the first embodiment of the present invention;
FIG. 8 is a sectional view illustrating the manufacturing method according to the first embodiment of the present invention; FIG. 8 is a sectional view illustrating the manufacturing method according to the first embodiment of the present invention;
FIG. 9 is a sectional view illustrating a manufacturing method according to a second embodiment of the present invention. FIG. 9 is a sectional view illustrating a manufacturing method according to a second embodiment of the present invention.
FIG. 10 is a sectional view illustrating a manufacturing method according to a second embodiment of the present invention. FIG. 10 is a sectional view illustrating a manufacturing method according to a second embodiment of the present invention.
FIG. 11 is a sectional view illustrating a manufacturing method according to a third embodiment of the present invention. FIG. 11 is a sectional view illustrating a manufacturing method according to a third embodiment of the present invention.
FIG. 12 is a sectional view illustrating a manufacturing method according to a third embodiment of the present invention. FIG. 12 is a sectional view illustrating a manufacturing method according to a third embodiment of the present invention.
FIG. 13 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device. FIG. 13 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.
FIG. 14 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device. FIG. 14 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.
FIG. 15 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device. FIG. 15 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.
FIG. 16 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device. FIG. 16 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.
FIG. 17 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device. FIG. 17 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.
FIG. 18 is a perspective view showing a conventional semiconductor device. FIG. 18 is a perspective view showing a conventional semiconductor device.

Claims (5)

  1. 半導体チップ上に第1の絶縁膜を介して一定の離間距離を有するように第1の配線を形成する工程と、
    前記第1の配線上を含む前記半導体チップ上に接着剤を介して支持材を接着する工程と、
    前記半導体チップ裏面をエッチングすることで前記第1の配線及びその離間箇所に充填された前記接着剤を露出させる工程と、
    前記半導体チップ裏面及び前記エッチング箇所に第2の絶縁膜を形成する工程と、
    前記第2の絶縁膜の所望位置をエッチングした後に前記第1の配線とコンタクトする第2の配線を形成する工程と、
    前記第2の配線上に導電端子を形成し、前記第1の配線の離間位置に沿ってダイシングする工程とを具備し、
    前記支持材がフィルム材、又は再生シリコン基板であることを特徴とする半導体装置の製造方法。 A method for manufacturing a semiconductor device, wherein the support material is a film material or a recycled silicon substrate. Forming a first wiring on the semiconductor chip so as to have a fixed distance via a first insulating film; Forming a first wiring on the semiconductor chip so as to have a fixed distance via a first insulating film;
    Bonding a support material to the semiconductor chip including the first wiring via an adhesive, Bonding a support material to the semiconductor chip including the first wiring via an adhesive,
    Exposing the adhesive filled in the first wiring and the space between the first wiring by etching the back surface of the semiconductor chip; Exposing the adhesive filled in the first wiring and the space between the first wiring by etching the back surface of the semiconductor chip;
    Forming a second insulating film on the back surface of the semiconductor chip and the etching location; Forming a second insulating film on the back surface of the semiconductor chip and the etching location;
    Forming a second wiring in contact with the first wiring after etching a desired position of the second insulating film; Forming a second wiring in contact with the first wiring after etching a desired position of the second insulating film;
    Forming a conductive terminal on the second wiring, and dicing along the separated position of the first wiring, Forming a conductive terminal on the second wiring, and dicing along the separated position of the first wiring,
    A method for manufacturing a semiconductor device, wherein the support material is a film material or a recycled silicon substrate. A method for manufacturing a semiconductor device, wherein the support material is a film material or a recycled silicon substrate.
  2. 半導体チップ上に第1の絶縁膜を介して一定の離間距離を有するように第1の配線を形成する工程と、
    前記第1の配線上に絶縁物からなる支持材を形成する工程と、
    前記半導体チップ裏面をエッチングすることで前記第1の配線及びその離間箇所に配置された前記支持材を露出させる工程と、
    前記半導体チップ及び前記エッチング箇所に第2の絶縁膜を形成する工程と、前記第2の絶縁膜の所望位置をエッチングした後に前記第1の配線とコンタクトする第2の配線を形成する工程と、
    前記第2の配線上に導電端子を形成し、前記第1の配線の離間位置に沿ってダイシングする工程とを具備することを特徴とする半導体装置の製造方法。 A method for manufacturing a semiconductor device, which comprises a step of forming a conductive terminal on the second wiring and dicing along the separated position of the first wiring. Forming a first wiring on the semiconductor chip so as to have a fixed distance via a first insulating film; Forming a first wiring on the semiconductor chip so as to have a fixed distance via a first insulating film;
    Forming a support material made of an insulator on the first wiring; Forming a support material made of an insulator on the first wiring;
    A step of exposing the first wiring and the support member disposed at a space between the first wiring and the space separated by etching the back surface of the semiconductor chip; A step of exposing the first wiring and the support member disposed at a space between the first wiring and the space separated by etching the back surface of the semiconductor chip;
    Forming a second insulating film at the semiconductor chip and the etching location, forming a second wiring that contacts the first wiring after etching a desired position of the second insulating film, Forming a second insulating film at the semiconductor chip and the etching location, forming a second wiring that contacts the first wiring after etching a desired position of the second insulating film,
    Forming a conductive terminal on the second wiring, and dicing along the separated position of the first wiring. Forming a conductive terminal on the second wiring, and dicing along the separated position of the first wiring.
  3. 前記絶縁物が、透明性を有するエポキシ材又はポリイミド材からなることを特徴とする請求項2記載の半導体装置の製造方法。 3. The method according to claim 2, wherein the insulator is made of a transparent epoxy material or polyimide material.
  4. 半導体チップ上に第1の絶縁膜を介して一定の離間距離を有するように第1の配線を形成する工程と、
    前記第1の配線上を含む前記半導体チップ上に酸化膜を形成する工程と、
    前記半導体チップ裏面をエッチングすることで前記第1の配線及びその離間箇所に配置された前記酸化膜を露出させる工程と、

    前記半導体チップ及び前記エッチング箇所に第2の絶縁膜を形成する工程と、前記第2の絶縁膜の所望位置をエッチングした後に前記第1の配線とコンタクトする第2の配線を形成する工程と、 A step of forming a second insulating film on the semiconductor chip and the etched portion, and a step of forming a second wiring that contacts the first wiring after etching a desired position of the second insulating film.
    前記第2の配線上に導電端子を形成し、前記第1の配線の離間位置に沿ってダイシングする工程とを具備することを特徴とする半導体装置の製造方法。 A method for manufacturing a semiconductor device, which comprises a step of forming a conductive terminal on the second wiring and dicing along the separated position of the first wiring. Forming a first wiring on the semiconductor chip so as to have a fixed distance via a first insulating film; Forming a first wiring on the semiconductor chip so as to have a fixed distance via a first insulating film;
    Forming an oxide film on the semiconductor chip including on the first wiring; Forming an oxide film on the semiconductor chip including on the first wiring;
    Exposing the oxide film disposed on the first wiring and the space separated from the first wiring by etching the back surface of the semiconductor chip; Exposing the oxide film disposed on the first wiring and the space separated from the first wiring by etching the back surface of the semiconductor chip;
    Forming a second insulating film at the semiconductor chip and the etching location, forming a second wiring that contacts the first wiring after etching a desired position of the second insulating film, Forming a second insulating film at the semiconductor chip and the etching location, forming a second wiring that contacts the first wiring after etching a desired position of the second insulating film,
    Forming a conductive terminal on the second wiring, and dicing along the separated position of the first wiring. Forming a conductive terminal on the second wiring, and dicing along the separated position of the first wiring.
  5. 前記酸化膜を低圧CVD法、又はプラズマCVD法によって形成することを特徴とする請求項4記載の半導体装置の製造方法。 5. The method according to claim 4, wherein the oxide film is formed by a low pressure CVD method or a plasma CVD method.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006100580A (en) * 2004-09-29 2006-04-13 Sanyo Electric Co Ltd Method for manufacturing semiconductor device
JP2006179709A (en) * 2004-12-22 2006-07-06 Sanyo Electric Co Ltd Manufacturing method for semiconductor device
JP2007242813A (en) * 2006-03-07 2007-09-20 Sanyo Electric Co Ltd Semiconductor device and its manufacturing method
JP2009099838A (en) * 2007-10-18 2009-05-07 Nec Electronics Corp Semiconductor device and manufacturing method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006100580A (en) * 2004-09-29 2006-04-13 Sanyo Electric Co Ltd Method for manufacturing semiconductor device
JP4522213B2 (en) * 2004-09-29 2010-08-11 三洋電機株式会社 Manufacturing method of semiconductor device
JP2006179709A (en) * 2004-12-22 2006-07-06 Sanyo Electric Co Ltd Manufacturing method for semiconductor device
JP2007242813A (en) * 2006-03-07 2007-09-20 Sanyo Electric Co Ltd Semiconductor device and its manufacturing method
JP2009099838A (en) * 2007-10-18 2009-05-07 Nec Electronics Corp Semiconductor device and manufacturing method thereof
US8110443B2 (en) 2007-10-18 2012-02-07 Renesas Electronics Corporation Semiconductor device and method of fabricating semiconductor device

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