JP2004006807A - Wiring board, manufacturing method thereof, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board using silicon as a base material for the wiring board, manufacturing method thereof and a semiconductor device. <P>SOLUTION: In the wiring board whose base material is composed of silicon, the wiring board has a plurality of through holes 109 on a silicon wafer 106, a first conductive pattern 112 is formed on a surface of the silicon wafer 106, the through holes 109 are provided on a slope 108 formed by making an inner angle formed with a backside of the silicon wafer 106 into obtuse angle, a second conductive pattern 113 is formed on the backside and the slope 108, and the first conductive pattern 112 and the second conductive pattern 113 are electrically connected by third conductive patterns 114 formed in the plurality of through holes 109. The through holes 109 are formed on the slope 108 so that working time is shortened and stable carrying is secured without necessity to make the silicon wafer 106 thin. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a wiring board in which external electrodes on both surfaces of a semiconductor substrate are electrically connected by a conductive pattern formed via a side surface of the semiconductor substrate, a method of manufacturing the same, and a semiconductor device using a semiconductor chip. is there.
[0002]
[Prior art]
2. Description of the Related Art In recent years, as electronic devices such as computers and communication devices have become smaller and more sophisticated, semiconductor devices have been required to be smaller, denser, and faster. Therefore, there has been proposed a multi-chip type semiconductor device in which a plurality of semiconductor chips are mounted on a wiring board to form a module, and the size and the density are increased.
[0003]
Hereinafter, a conventional semiconductor device will be described for each mode.
[0004]
60 to 64 are cross-sectional views showing a conventional semiconductor device.
[0005]
First, as shown in FIG. 60, a plurality of semiconductor chips 2 are mounted on a wiring board 1 by a flip chip method, and electrodes of the semiconductor chip 2 and connection electrodes of the wiring board 1 are electrically connected by metal bumps 3. In addition, a plurality of semiconductor chips are mounted on one wiring board in a line.
[0006]
Next, as shown in FIG. 61, a plurality of semiconductor chips 5 are stacked on the wiring board 4, and the electrodes of the respective semiconductor chips 5 and the connection electrodes of the wiring board 4 are electrically connected by the metal wires 6. The mounting area of the semiconductor chip with respect to the substrate is smaller than that in the case where the semiconductor chips are arranged in a plane.
[0007]
Further, as shown in FIG. 62, the electrode-shaped surfaces of the two semiconductor chips 7 are opposed to each other, and the electrodes of the respective semiconductor chips 7 are electrically connected by metal bumps 8 to form a substrate-less laminated structure. I have.
[0008]
Further, as shown in FIG. 63, a plurality of semiconductor devices in which the semiconductor chip 9 is mounted on the wiring board 11 via the metal bumps 10 by the flip chip method are stacked, and the wiring of each wiring board 11 is connected by the metal bumps 12. It is electrically connected.
[0009]
As described above, the conventional semiconductor devices have been described according to their forms. However, each of the conventional semiconductor devices realizes a semiconductor device including a plurality of semiconductor chips, and the plurality of semiconductor chips are mounted on a plane with respect to a wiring board. In this configuration, the semiconductor chip is mounted on the wiring board, the semiconductor chip is mounted on the wiring board, and the semiconductor chip is mounted on the wiring board. Was in the form.
[0010]
In addition, since the semiconductor chips constituting each semiconductor device have electrodes formed only on one side thereof, when the semiconductor chips are stacked, the semiconductor chips are electrically connected to each other using metal wires or substrates. Had gone.
[0011]
FIG. 64 is a cross-sectional view of a semiconductor device using a conventional resin wiring substrate.
[0012]
As shown in FIG. 64, one or a plurality of semiconductor chips 2 are mounted on a resin wiring board 1 formed of a composite material containing an epoxy resin by a flip chip method, and a surface electrode of the semiconductor chip 2 is connected to a resin wiring. The connection electrodes on the surface of the substrate 1 are electrically connected by metal bumps 3. Further, the connection electrodes on the back surface of the resin wiring board 1 are electrically connected to the wiring of the motherboard 405 by the solder balls 404. The connection electrodes on both surfaces of the resin wiring board 1 are electrically connected by a conductive pattern formed on the inner wall of a through hole (not shown) penetrating the inside of the resin wiring board 1.
[0013]
Thus, the semiconductor chip 2 is not directly mounted on the motherboard 405, but has a structure in which the resin wiring board 1 is interposed between the semiconductor chip 2 and the motherboard 405.
[0014]
[Problems to be solved by the invention]
However, conventional semiconductor devices in which a plurality of semiconductor chips are stacked have the following problems in each form.
[0015]
First, as shown in FIG. 60, in order to arrange the plurality of semiconductor chips 2 on the wiring board 1 in a plane, at least the area of the wiring board 1 needs to be larger than the total area of the plurality of semiconductor chips 2. As the number of semiconductor chips 2 to be mounted increases, the area of the wiring board 1 must be increased.
[0016]
In the semiconductor device shown in FIG. 61, every time the semiconductor chip 5 is stacked, it is necessary to expose an electrode for connecting the metal wire 6 electrically connected to the wiring of the wiring board 4 to the upper surface of the semiconductor chip 5. Therefore, the size of the semiconductor chip 5 apart from the substrate becomes smaller. Therefore, it is impossible to stack semiconductor chips of the same size. If the number of stacked semiconductor chips 5 increases, the total length of the metal wires 6 also increases, so that there is a problem that the wiring length increases.
[0017]
Further, in the semiconductor device shown in FIG. 62, it is impossible to stack three or more semiconductor chips 7, so that the function as the semiconductor device is limited.
[0018]
Further, in the semiconductor device shown in FIG. 63, since it is necessary to provide the wiring board 11 between the plurality of semiconductor chips 9, there is a problem that the thickness of the semiconductor device after the semiconductor chips are stacked increases.
[0019]
As described above, in the conventional semiconductor device, when a plurality of semiconductor chips are arranged in a plane, the mounting area increases, and it is impossible to stack semiconductor chips of the same size because electrodes for connecting metal wires need to be provided. Since the number of semiconductor chips to be formed is limited, the function as a semiconductor device is limited, and the thickness of the semiconductor device is increased due to a structure in which a substrate is provided between stacked semiconductor chips, miniaturization, higher functionality, and higher speed are realized. It was difficult to achieve.
[0020]
In addition, the change in characteristics of a resin wiring board using a composite material containing an epoxy resin due to temperature, humidity, and the like is larger than the change in characteristics of a semiconductor chip. There is a remarkable difference from the composite material of the type, and a large stress is generated at the joint between the semiconductor chip and the resin wiring board, and there is a risk that the joint may be broken.
[0021]
Further, since the resin wiring board has insufficient flatness compared to the semiconductor chip, the flip chip method in which the semiconductor chip is directly bonded to the resin wiring board uses metal bumps formed on the electrodes of the semiconductor chip and the resin wiring board. There is a problem that the electrical connection with the connection electrode is not stable.
[0022]
In addition, since the dimensional accuracy of the wiring formed on the resin wiring board is not sufficient as compared with the dimensional accuracy of the semiconductor chip, a positional shift occurs at a connection portion between the surface electrode of the semiconductor chip and the connection electrode of the resin wiring board, Poor bonding may result.
[0023]
Furthermore, since the semiconductor chip is mounted on a flat surface on the resin wiring board, the area of the resin wiring board cannot be made smaller than the total area of the mounted semiconductor chips. There is a problem in that the area of the resin wiring board increases as the number increases.
[0024]
The present invention solves the above-mentioned conventional problem by electrically connecting electrodes on both surfaces of a semiconductor chip by a conductive pattern passing through the side surface of the semiconductor chip, thereby stacking a plurality of semiconductor chips on a wiring board. Another object of the present invention is to provide a semiconductor device using a semiconductor chip which focuses on not increasing the thickness and substrate area of the semiconductor device on which the semiconductor chips are stacked and increasing the wiring length between the semiconductor chips.
[0025]
SUMMARY OF THE INVENTION The present invention provides a wiring board using silicon as a base material of the wiring board and a method of manufacturing the same, in order to solve the above-mentioned conventional problems.
[0026]
[Means for Solving the Problems]
2. The wiring board according to claim 1, wherein the base material is made of silicon, the wiring board has a plurality of through holes, a first conductive pattern is formed on a surface of the wiring board, and the through holes are formed by wiring. An inner angle with the back surface of the substrate is provided on a slope formed at an obtuse angle, a second conductive pattern is formed on the back surface and the slope, and the first conductive pattern and the second conductive pattern are formed in a plurality of through holes. It is characterized by being electrically connected by the formed third conductive pattern.
[0027]
According to the wiring board of the first aspect, the formation of the slope makes it unnecessary to form the hole deeply, so that the processing time can be reduced and the cost can be reduced. In addition, since it is not necessary to grind the silicon substrate to reduce its thickness, stable conveyance can be ensured.
[0028]
The wiring board according to claim 2 is a wiring board for a multi-chip semiconductor device in which electronic components are mounted on a wiring board and mounted on a motherboard, wherein the wiring board has a silicon substrate made of silicon. A first conductive pattern including at least one layer for mounting and wiring electronic components on a front surface and a second conductive pattern including at least one layer having electrodes for mounting on a motherboard are provided on a back surface of the silicon substrate. The first conductive pattern and the second conductive pattern are electrically connected by a third conductive pattern formed on a side surface of the silicon substrate.
[0029]
According to the wiring board of the second aspect, the first conductive pattern for mounting and wiring the electronic components on the front surface and the second conductive pattern including electrodes for mounting on the motherboard on the rear surface are provided, and the first conductive pattern is provided. A wiring substrate made of silicon is obtained in which the conductive pattern and the second conductive pattern are electrically connected by the third conductive pattern formed on the side surface.
[0030]
This silicon wiring board does not change its shape due to humidity and is made of the same silicon as the semiconductor chip, so the shape change such as expansion and contraction due to temperature change is the same as that of the semiconductor chip, and the flatness is high because it is formed by polishing. In addition, the dimensional accuracy of the electrode position is high, and the pitch of the connection electrodes at the same level as that of the semiconductor chip can be narrowed and the wiring density can be increased.
[0031]
Therefore, a multi-chip semiconductor device using such a silicon wiring board can reduce the stress at the joints of the metal bumps to increase the reliability, improve the bonding stability by the flatness and dimensional accuracy of the wiring board, It is possible to improve the wiring density at a level that cannot be achieved by a wiring board, and it is possible to realize compactness, high density, and high speed.
[0032]
4. The wiring board according to claim 3, wherein the wiring board is a wiring board for a multi-chip semiconductor device in which electronic components are mounted on the wiring board and mounted on a motherboard, wherein the wiring board forms an acute angle with the surface and has a side surface formed around the surface. Having a silicon substrate made of silicon with a recess formed therein, a first conductive pattern formed of at least one layer having electrodes formed on the surface of the silicon substrate and the recess, and formed on the back and side surfaces of the silicon substrate, A second conductive pattern connected to the first conductive pattern and comprising at least one layer having an electrode.
[0033]
According to the wiring board of the third aspect, the first conductive pattern is provided on the front surface and the second conductive pattern is provided on the back surface, and the first conductive pattern and the second conductive pattern are directly electrically connected. Thus, a wiring substrate made of silicon can be obtained.
[0034]
Therefore, in the multi-chip semiconductor device using such a silicon wiring board, the reliability is improved by reducing the stress at the joint portion of the metal bumps, and the flatness and the dimensional accuracy of the wiring board are improved. The bonding stability can be improved, the wiring density can be increased at a level that cannot be achieved by a resin wiring board, and a small size, high density, and high speed can be realized.
[0035]
According to a fourth aspect of the present invention, in the wiring board according to the first or third aspect, an insulating layer is formed on a side surface so as to be perpendicular to a surface of the substrate.
[0036]
According to the wiring board of the fourth aspect, in addition to the same effects as those of the first or third aspect, the side face of the wiring board can be reinforced and the protection of the conductive pattern on the side face can be improved.
[0037]
According to a fifth aspect of the present invention, in the wiring board according to the first, second, or third aspect, one or both of the first conductive pattern and the substrate and the second conductive pattern and the substrate are provided. Has a low-stress resin layer.
[0038]
According to the fifth aspect of the present invention, in addition to the same effects as those of the first, second, and third aspects, it is possible to reduce stress caused by a temperature change between the semiconductor chip and the wiring board. Thus, the mounting reliability of the semiconductor chip can be improved.
[0039]
According to a sixth aspect of the present invention, in the method of manufacturing a wiring substrate, a step of forming a hole from the surface of the silicon substrate, a step of forming a first conductive pattern in the surface and the hole, and an inner angle formed with the back surface of the silicon substrate is obtuse. Forming a slope in a region sandwiching a boundary portion of the substrate piece unit on the back surface, exposing a first conductive pattern by penetrating a hole, and a second conductive pattern electrically connected to the first conductive pattern On the back surface and the slope.
[0040]
According to the method of manufacturing a wiring board according to the sixth aspect, since the hole is made to penetrate by forming the slope from the back surface of the wiring board, the processing time of the hole can be reduced, and the processing cost can be reduced.
[0041]
8. The method for manufacturing a wiring board according to claim 7, wherein a first conductive pattern including at least one layer for mounting and wiring electronic components is formed on a surface of the silicon wafer, and the first conductive pattern is mounted on a back surface of the silicon wafer. Forming a second conductive pattern composed of at least one layer having an electrode for performing the operation, dividing the silicon wafer into individual silicon substrates to form side surfaces, and forming the first conductive pattern and the second conductive pattern. Forming a third conductive pattern for electrically connecting the pattern to the side surface, and after forming the first conductive pattern, forming a side surface by dividing the silicon wafer into individual silicon substrates. And thereafter, the step of forming the second conductive pattern and the step of forming the third conductive pattern are performed simultaneously.
[0042]
According to the method of manufacturing a wiring board according to claim 7, the method has a first conductive pattern for mounting and wiring electronic components on the front surface and a second conductive pattern including electrodes for mounting on the motherboard on the back surface. A wiring board made of silicon is obtained in which the first conductive pattern and the second conductive pattern are electrically connected by the third conductive pattern formed on the side surface. Further, it is possible to easily realize a multi-chip semiconductor wiring substrate having a front electrode and a back electrode electrically connected from a silicon substrate in a wafer state via a conductive pattern passing through a side surface. Further, after the step of forming the first conductive pattern, a step of dividing the silicon wafer into individual silicon substrates to form side surfaces is performed, and thereafter, a step of forming a second conductive pattern and a step of forming the third conductive pattern Since the step of forming the substrate is performed simultaneously, the number of manufacturing steps can be reduced.
[0043]
In the method of manufacturing a wiring substrate according to claim 8, a step of forming a concave portion around the surface of the silicon substrate in a wafer state, and forming a first conductive pattern including at least one electrode having electrodes on the surface and the concave portion. Forming a slope forming an acute angle with the front surface on the silicon substrate; forming a second conductive pattern electrically connected to the first conductive pattern on the back surface and the slope of the silicon substrate and having at least one layer having electrodes; Forming step.
[0044]
According to the method of manufacturing a wiring board according to the eighth aspect, the first conductive pattern has the first conductive pattern on the front surface and the second conductive pattern on the back surface, and the first conductive pattern and the second conductive pattern are directly electrically connected. A wiring substrate made of connected silicon is obtained. Further, since the concave portion and the side surface forming an acute angle with the front surface are formed in the wiring substrate, it is possible to form a wiring that conducts between the front and back surfaces only by forming a conductive pattern from the front surface and the back surface. Further, a multi-chip semiconductor wiring substrate having a front electrode and a back electrode electrically connected from a silicon substrate in a wafer state via a conductive pattern passing through a side surface can be easily realized.
[0045]
According to a ninth aspect of the present invention, there is provided a method of manufacturing a wiring board according to the sixth or eighth aspect, further comprising the step of forming an insulating layer on an inclined surface so as to form a right angle with the surface of the silicon substrate. It is formed by curing and divided into individual pieces by dicing.
[0046]
According to the method of manufacturing a wiring board according to the ninth aspect, in addition to the same effect as the sixth aspect or the eighth aspect, the liquid resin is supplied on the slope, and the cured resin portion is diced to be divided into individual pieces of the substrate. Thus, the resin absorbs mechanical interference generated by cutting resistance at the time of dicing and distortion caused by frictional heat, thereby preventing problems such as chipping.
[0047]
According to a tenth aspect of the present invention, in the method of the sixth or eighth aspect, a low-stress resin layer is formed between the substrate and the first conductive pattern or between the substrate and the second conductive pattern. Is provided.
[0048]
According to the method of manufacturing a wiring board according to the tenth aspect, in addition to the same effects as the sixth and eighth aspects, it is possible to reduce stress caused by a temperature change generated between the semiconductor chip and the wiring board, The mounting reliability of the semiconductor chip can be improved.
[0049]
The semiconductor device according to claim 11, wherein the semiconductor substrate, a first external electrode formed on a first surface of the semiconductor substrate, a second external electrode formed on a second surface of the semiconductor substrate, A through-hole formed in the substrate, wherein the through-hole is provided on a slope formed such that an inner angle with the second surface is formed at an obtuse angle, and the first external electrode and the second external electrode A plurality of semiconductor chips electrically connected by a conductive pattern formed via the inner wall and the slope of the hole are stacked by electrically connecting the first external electrode and the second external electrode, respectively. It is characterized by having been done.
[0050]
According to the semiconductor device of the eleventh aspect, the semiconductor chip having the first external electrode and the second external electrode connected via the conductive pattern formed on the inner wall and the slope of the through hole is laminated, and both surfaces thereof are stacked. A semiconductor device in which the semiconductor chips are electrically connected via the electrodes described above is obtained. Since the semiconductor chips are not arranged in a plane on the wiring board, the mounting area can be reduced. Further, since there is no need to provide electrodes for connecting metal wires, two or more semiconductor chips of the same size and different sizes can be stacked in a desired order, and the wiring length between the semiconductor chips can be increased. , And the thickness of the stacked layers can be reduced, and a semiconductor device corresponding to miniaturization, high density, and high speed can be realized.
[0051]
13. The semiconductor device according to claim 12, wherein: a semiconductor substrate; a first external electrode formed on a first surface of the semiconductor substrate; a second external electrode formed on a second surface of the semiconductor substrate; A through-hole formed in the substrate, wherein the through-hole is provided on a slope formed such that an inner angle with the second surface is formed at an obtuse angle, and the first external electrode and the second external electrode Between two first semiconductor chips electrically connected by a first conductive pattern formed via an inner wall and a slope of the hole, the third semiconductor chip is formed on a portion of the third surface other than the element formation region. A second semiconductor chip is provided in which the third external electrode and the fourth external electrode formed on a portion of the fourth surface other than the element formation region are electrically connected by a second conductive pattern. And the first semiconductor chip and the second semiconductor chip directly or And it is characterized in that it is electrically connected to.
[0052]
According to the semiconductor device of the twelfth aspect, a multi-chip type semiconductor with a small mounting area, a short wiring length between each semiconductor chip, a low stacking height, small size, high density, and high speed. The device can be realized.
[0053]
14. The semiconductor device according to claim 13, wherein the semiconductor chip is a multi-chip type semiconductor device in which a plurality of semiconductor chips each including a semiconductor substrate in which elements are integratedly formed on the surface are stacked. A first external electrode formed of a semiconductor substrate having a back surface facing in parallel with the front surface, a slope formed at an acute angle with the front surface, and a concave portion formed around the front surface, and a first external electrode formed on the front surface; A second external electrode formed on the back surface, a conductive pattern formed in the concave portion and on the side surface for connecting the first external electrode and the second external electrode, and The semiconductor device is characterized by being electrically connected to another semiconductor chip via the first external electrode and the second external electrode.
[0054]
According to the semiconductor device of claim 13, a semiconductor chip having a first external electrode and a second external electrode connected via a conductive pattern is laminated, and the first external electrode and the second external electrode are stacked. Since each semiconductor chip is electrically connected via the semiconductor chip, the mounting area is small and the same size semiconductor chips can be stacked without arranging a plurality of semiconductor chips in a plane on the wiring board. It is also possible to stack semiconductor chips of different sizes in a desired order, and the wiring length between the semiconductor chips is short, the stacking height is low, and the number of stacked semiconductor chips is two or more. A high-density and high-speed multi-chip semiconductor device can be realized. Further, since the semiconductor substrate has a slope formed at an acute angle with the surface and a concave portion formed around the surface, the semiconductor chip can be easily manufactured.
[0055]
According to a fourteenth aspect of the present invention, in the semiconductor device according to the thirteenth aspect, the stacked semiconductor chips are electrically connected to the semiconductor chips immediately above and below the semiconductor chips directly or via a connection member. Things.
[0056]
According to the semiconductor device of the fourteenth aspect, in addition to the same effects as in the thirteenth aspect, a multi-layered semiconductor chip having a shorter wiring length and a lower stacking height in the plane of the semiconductor chip is provided. A chip semiconductor device is obtained. Therefore, it is possible to realize a small-sized, high-density, high-speed multi-chip semiconductor device having a small mounting area, a short wiring length between the semiconductor chips, a low stacking height.
[0057]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a semiconductor chip, a method of manufacturing the same, and a semiconductor device using the semiconductor chip of the present invention will be described with reference to the drawings.
[0058]
First, the semiconductor chip of the present invention will be described. First, a first embodiment of the present invention will be described.
[0059]
FIG. 1 is a sectional view of the semiconductor chip of the present embodiment. As shown in FIG. 1, an element (not shown) and a multilayer conductive pattern (not shown) are formed on a first surface 14 which is a surface of a semiconductor substrate 13, from the first surface 14 to the slope 15. The slanted surface 15 in which the processed through hole 16 is formed and the inner angle with the second surface 17 as the bottom surface is formed to be an obtuse angle forms a part of the outer shape of the semiconductor substrate 13. In the present embodiment, the interior angle between the slope and the second surface is 135 degrees, and the slope is formed to a position of 50 [μm] from the second surface. This makes it easier for a certain amount of resin supplied on the slope to adhere to the surface, protects the conductive pattern against external impact, and electrically connects the electrodes formed on the surface of the semiconductor substrate. Since the distance between the conductive patterns is shortened, it is possible to cope with an increase in speed.
[0060]
The surface electrode 18 formed on the first surface 14 is electrically connected to the inner wall of the through hole 16 and the conductive pattern 19 formed on the surface of the slope 15. The conductive pattern 19 may be filled in the through-hole 16, and the thickness of the conductive pattern 19 is preferably 5 to 15 [μm], and is 10 [μm] in the present embodiment. The material of the surface electrode 18 is made of aluminum (Al) or copper (Cu), and the thickness of the surface electrode 18 is 0.3 to 1.0 [μm]. In a manufacturing process for forming a wiring made of copper (Cu) having a wiring width of 0.13 [μm], the thickness of the wiring is 0.45 [μm].
[0061]
Next, the insulating layer formed on the formed surface electrode and conductive pattern will be described. A first insulating layer 20 is formed on the first surface 14, the second surface 17, the inclined surface 15, and the inner wall of the through hole 16 of the semiconductor substrate 13 excluding the surface electrode 18, and the thickness of the first insulating layer 20 is It is preferably 0.5 to 10 [μm], and is 1 [μm] in the present embodiment. Then, a part of the conductive pattern 19 is opened as the first external electrode 21 and the second external electrode 22, and the first insulating layer on which the conductive pattern 19 is not formed is formed on the conductive pattern 19 except for those electrodes. A second insulating layer 23 is formed on the first insulating layer 20 on the surface 20 and the second surface 17.
[0062]
Here, the thickness of the second insulating layer 23 is 1 to 30 μm, and in the present embodiment, 1 μm for silicon dioxide (SiO 2), silicon nitride (SiN), and oxynitride film (SiON). And 7 [μm] for polyimide. Note that the second insulating layer 23 may be mainly made of a solder resist, and the thickness in this case is 30 [μm] in the present embodiment. Since the first external electrode 21 and the second external electrode 22 are formed as a part of the conductive pattern 19, the thickness of the first external electrode 21 and the thickness of the second external electrode 22 It is the same as the thickness of No.
[0063]
As described above, in the semiconductor chip of the present embodiment, the surface electrodes of the semiconductor substrate and the external electrodes formed on both surfaces of the semiconductor substrate are electrically connected, so that a plurality of semiconductor chips are stacked facing each other. Thus, electrical connection between the semiconductor chips can be achieved.
[0064]
Next, a method for manufacturing the semiconductor chip of the present embodiment will be described.
[0065]
2 to 16 are cross-sectional views of each step of the method for manufacturing a semiconductor chip of the present embodiment.
[0066]
First, as shown in FIG. 2A, a semiconductor substrate 13 in a wafer state having a plurality of semiconductor chip units and having a thickness of 600 to 1000 [μm] is prepared, and a first surface which is a surface of the semiconductor substrate 13 is prepared. 14, an element (not shown), a multilayer conductive pattern (not shown), and a surface electrode 18 are formed. Here, the position where the surface electrode 18 is formed is not particularly limited, but is formed around the semiconductor chip unit in the present embodiment. In the present embodiment, a surface insulating layer 25 mainly composed of silicon nitride (SiN) is formed in a region other than the surface electrode 18, but may be formed of a material other than SiN. The material is not particularly limited as long as it has a function. The thickness of the surface insulating layer 25 is 0.5 to 10 [μm], and is 1 [μm] in the present embodiment. Since the surface insulating layer 25 is intended to protect against external impact, it is not necessary to particularly form the surface insulating layer 25.
[0067]
The dotted lines indicate the positions where both ends in the width direction of the cutting blade pass during dicing for dividing the semiconductor substrate into semiconductor chip units, and the center of the two dotted lines indicates the boundary between the semiconductor chip units. It is.
[0068]
Next, the hole forming process will be described.
[0069]
FIG. 2B is a cross-sectional view showing a state where a hole is machined from the first surface of the semiconductor substrate.
[0070]
As shown in FIG. 2B, a hole 26 having a depth of 20 to 100 [μm] is formed by RIE (Reactive Ion Etching) without penetrating the first surface 14 of the semiconductor substrate 13 in the thickness direction. However, the formation position of the hole is formed around the semiconductor chip unit, and in the present embodiment, is a position closest to the corresponding hole on a straight line at a position of 50 [μm] from the boundary line of the semiconductor chip unit. In the present embodiment, the depth of the hole is 70 [μm], and the length of the through hole through which the hole penetrates by forming the slope is about 50 [μm]. The method for forming the holes 26 is not limited to the RIE method, and light etching, wet etching, ultrasonic processing, electric discharge processing, and the like can be used, and the above-described various processing methods may be combined. .
[0071]
As described above, the RIE method, which is a processing method of a hole formed in a semiconductor substrate, is a dry etching method using reactive gas plasma, and is a method used for fine processing of a semiconductor wafer. A mask covering portions other than the holes is formed on the insulating layer so as not to be etched, and the mask is removed after etching.
[0072]
Next, as shown in FIG. 3C, after forming the first insulating layer 20 on the inner wall of the hole 26 and on the surface insulating layer 25 except for the opening of the surface electrode 18, the portion of the surface electrode 18 is opened. The formed mask is formed on the first insulating layer 20, and after the insulating layer formed on the surface electrode 18 is etched, the mask is removed. Here, the first insulating layer 20 is formed of silicon dioxide (SiO 2) by a method such as a CVD method, a sputtering method, a photo CVD method, and a coating method. ₂ ), Silicon nitride (SiN), oxynitride film (SiON), polyimide and the like.
[0073]
Next, as shown in FIG. 3D, a first laminated metal film 27 is formed on the first insulating layer 20, and the first laminated metal film 27 has a seed layer laminated on the barrier layer. It has a two-layer structure. Here, the barrier layer and the seed layer are formed by a sputtering method, a CVD method, an electron beam evaporation method, or the like. The barrier layer is made of any of titanium (Ti), titanium tungsten (Ti / W), chromium (Cr), and nickel (Ni), and the seed layer is made of copper (Cu), gold (Au), and silver (Ag). ), Nickel (Ni) or the like.
[0074]
Next, as shown in FIG. 4E, a first conductive pattern 28 is formed on the inner wall of the hole 26 by electrolytic plating using the first laminated metal film 27 as an electrode, and the desired wiring and electrode shapes are formed. Is formed on the first laminated metal film 27. At this time, a plating resist 29 is formed on the first laminated metal film 27 in order to obtain a desired wiring and electrode shape, and after the electrolytic plating, the plating resist 29 is removed. The first conductive pattern 28 may be formed by filling the hole 26. Further, as a material of the first conductive pattern 28, copper (Cu), gold (Au), tungsten (W), molybdenum (Mo), nickel (Ni), titanium (Ti), aluminum (Al), or the like is used. .
[0075]
Next, as shown in FIG. 4F, using the first conductive pattern 28 as a mask, the first laminated metal film 27 in a portion other than the region where the first conductive pattern 28 is formed is removed by etching.
[0076]
Next, as shown in FIG. 5 (g), a second insulating layer 23 is formed by opening a part of the first conductive pattern 28 as a first external electrode 21. At this time, a second insulating layer 23 is formed. After the layer 23 is formed on the first conductive pattern 28 and the first insulating layer 20 excluding the first external electrode 21, a mask in which the first external electrode 21 is opened is formed. After etching the second insulating layer 23 in the opening of the electrode 21, the mask is removed. Note that a film of silicon dioxide (SiO2), silicon nitride (SiN), oxynitride film (SiON), polyimide, or the like is formed as the second insulating layer 23 by a CVD method, a sputtering method, an optical CVD method, a coating method, or the like. It is a thing.
[0077]
As described above, only the first external electrode 21 electrically connected to the surface electrode 18 is formed on the surface of the semiconductor substrate as being exposed from the second insulating layer 23.
[0078]
Next, as shown in FIG. 6, the first surface 14 of the semiconductor substrate is adhered to the support 31 with an adhesive 30, and the semiconductor substrate 13 is ground from the second surface 17 by mechanical grinding or CMP (Chemical Mechanical Polishing). Then, it is processed to a thickness of 50 to 200 [μm]. In the present embodiment, the thickness of the semiconductor substrate after grinding is 100 [μm].
[0079]
Next, as shown in FIG. 7, on the second surface 17 of the semiconductor substrate 13, the center of the two dotted lines sandwiching the boundary of the semiconductor chip unit is cut by bevel cutting, and the second surface 17 of the semiconductor substrate 13 is cut. The first conductive pattern 28 is exposed on the slope 15 while forming the slope 15 at an obtuse angle with 17. Therefore, as shown in FIG. 2B, the hole 26 formed in the semiconductor substrate 13 does not need to penetrate the semiconductor substrate 13, and the time required for processing the hole 26 can be reduced. The processing depth of the hole 26 shown in FIG. 2B is determined by the cutting depth in bevel cutting and the tip shape of the cutting blade.
[0080]
Here, the bevel cut refers to a semiconductor substrate having a relatively large thickness and a slope formed such that an inner angle with the second surface is formed at an obtuse angle by using a cutting blade having a slope formed at the tip. It is a cutting method. Note that the thickness of the cutting blade used for bevel cutting is desirably greater than the distance between adjacent through holes by about 100 [μm] or more. In the present embodiment, the distance between adjacent through holes is 100 [μm], and the thickness of the cutting blade used for bevel cutting is 200 [μm]. In the present embodiment, the processing method using bevel cutting has been described, but processing may be performed by etching.
[0081]
Next, as shown in FIG. 8, a third insulating layer 32 is formed on the entire surface of the slope 15 and the second surface 17 excluding the portion exposed on the slope 15 of the first conductive pattern 28. After the third insulating layer 32 is formed on the entire slope 15 and the second surface 17, a mask having an opening at a portion where the first conductive pattern 28 is exposed is formed on the third insulating layer 32, and the first conductive layer 28 is formed. After etching the third insulating layer 32 at the opening of the pattern 28, the mask is removed. Note that, as the third insulating layer 32, a film of silicon dioxide (SiO2), silicon nitride (SiN), oxynitride film (SiON), polyimide, or the like was formed by a CVD method, a sputtering method, an optical CVD method, coating, or the like. Things.
[0082]
Further, it is preferable that the third insulating layer 32 be formed using a material whose etching rate is higher than that of the first insulating layer 20. That is, when opening the third insulating layer 32 by etching, the third insulating film 32 is selectively etched without substantially etching the first insulating layer 20 even if a mask shift occurs. This is because the opening can be formed and the first insulating layer 20 is not partially removed.
[0083]
Next, as shown in FIG. 9, a second laminated metal film 33 is formed on the entire surface of the slope 15 and the second surface 17. The second laminated metal film 33 has a two-layer structure in which a seed layer is laminated on a barrier layer. The barrier layer and the seed layer are formed by a sputtering method, a CVD method, an electron beam evaporation method, or the like. Titanium (Ti), titanium tungsten (Ti / W), chromium (Cr), nickel (Ni), etc. are used for the barrier layer, and copper (Cu), gold (Au), silver (Ag), Nickel (Ni) or the like is used.
[0084]
Next, as shown in FIG. 10, a second conductive pattern 34 having a desired wiring and electrode shape is formed on the inclined surface 15 and the second surface 17 by electrolytic plating using the second laminated metal film 33 as an electrode. Thus, the second conductive pattern 34 is electrically connected to the first conductive pattern 28 exposed from the slope 15 via the second laminated metal film 33. At this time, in order to form desired wiring and electrode shapes, a plating resist 35 is formed on a portion of the second laminated metal film 33 where the second conductive pattern 34 does not need to be formed, After the electrolytic plating, the plating resist 35 is removed. Further, as a material of the second conductive pattern 34, copper (Cu), gold (Au), tungsten (W), molybdenum (Mo), nickel (Ni), titanium (Ti), aluminum (Al), or the like is used. Can be
[0085]
Next, as shown in FIG. 11, using the second conductive pattern 34 as a mask, the second stacked metal film 33 other than the region where the second conductive pattern 34 is formed is removed by etching.
[0086]
Next, as shown in FIG. 12, a fourth insulating layer 36 is formed on the entire second surface 17 except the opening of the second external electrode 22 and on the inclined surface 15. At this time, after the fourth insulating layer 36 is formed on the entire slope 15 and the second surface 17, a mask having an opening in the second external electrode 22 is formed, and the opening of the second external electrode 22 is formed. After etching the fourth insulating layer 36, the mask is removed. Note that the fourth insulating layer 36 is formed of a film such as silicon dioxide (SiO 2), silicon nitride (SiN), an oxynitride film (SiON), or polyimide by using a CVD method, a sputtering method, an optical CVD method, a coating method, or the like. Is formed.
[0087]
Next, as shown in FIG. 13, dicing is performed on a scribe line 37 which is a boundary line of a semiconductor chip unit, to form a side surface 38 whose inner angle with the first surface 14 is a right angle. Thereafter, the adhesive 30 and the support 31 are removed, and the semiconductor chip 39 is divided into individual pieces.
[0088]
Through such a series of semiconductor chip manufacturing steps, a first external electrode is formed on the first surface of the semiconductor chip in a state of being exposed from the second insulating layer. Is formed with the second external electrode exposed from the fourth insulating layer, and the surface electrode, the first external electrode, and the second external electrode are electrically connected to each other.
[0089]
The formation positions of the first external electrode and the second external electrode are not particularly limited. When a plurality of semiconductor chips are stacked, if the external electrodes of adjacent semiconductor chips are at corresponding positions, respectively. Good.
[0090]
14 to 16 are cross-sectional views of a process of supplying and curing the resin on the slope after the process shown in FIGS. The steps shown in FIGS. 14 to 16 are intended to reinforce the slope.
[0091]
As shown in FIG. 14, after the step shown in FIG. 11 or FIG. 12, the liquid resin is applied to the bevel-cut portion until the upper surface thereof becomes the height of the second surface, thereby forming the second external resin. An insulating resin layer 40 is formed on the entire surface of the second surface except for the portion to be opened as the electrode 22 and on the slope 15.
[0092]
The liquid resin is preferably a resin such as polyimide which can relieve stress.
[0093]
Next, as shown in FIG. 15, dicing is performed on the portion of the scribe line 37 from the second surface side to form a side surface perpendicular to the second surface.
[0094]
Next, as shown in FIG. 16, the adhesive 30 and the support 31 are removed, and the semiconductor chip 39 is divided into individual pieces.
[0095]
The shape of the through-hole or the hole may be circular or square. In the case of a circular shape, the diameter is 10 to 20 [μm], and in the case of a square, the length of one side is 10 to 20 [μm]. Is 20 [μm]. Here, when the shape of the hole is a quadrangle, the corner of the quadrangle is not a right angle but a rounded shape. In addition, it is also possible to process a through-hole or a hole whose diameter or side length is smaller than 10 [μm] by technical innovation of the RIE method.
[0096]
The thickness of the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer is 1 to 30 μm, and in the present embodiment, silicon dioxide (SiO 2), silicon nitride The thickness is 1 [μm] for (SiN) and oxynitride film (SiON), and 7 [μm] for polyimide. Further, the second insulating layer and the fourth insulating layer may be mainly made of a solder resist, and the thickness in this case is 30 [μm] in the present embodiment.
[0097]
Further, the thickness of the first conductive pattern 28 and the second conductive pattern 34 is preferably 5 to 15 [μm], and is 10 [μm] in the present embodiment.
[0098]
In the present embodiment, by applying the liquid resin on the slope, and then dicing the cured liquid resin portion, problems such as chipping at the time of cutting can be prevented, and the thickness is perpendicular to the second surface and relatively large. Since the corners of the semiconductor substrate formed of the insulating resin layer can be formed and the semiconductor chips can be separated into individual pieces, the side surfaces of the semiconductor chips are reinforced and the second conductive pattern on the slope is protected. Can be.
[0099]
As described above, in the present embodiment, in addition to the various insulating layer forming steps, a step of forming a hole halfway from the first surface of the semiconductor substrate and a step of forming a slope from the second surface and passing the hole are performed. By providing the step of forming the conductive pattern and the step of forming the conductive pattern via the hole and the inclined surface, a structure in which the electrodes formed on both surfaces of the semiconductor substrate are electrically connected to each other can be realized.
[0100]
Further, after the first conductive pattern is formed in the hole formed in the semiconductor substrate, the first conductive pattern is formed in the second conductive surface by forming a slope that reaches the hole and forms an obtuse angle with the second surface. Therefore, since it is not necessary to form a hole deeply or to polish the semiconductor substrate thinly, the processing time can be reduced and the processing cost can be reduced. In addition, since the degree of freedom of the thickness of the semiconductor chip is increased and the thickness of the semiconductor substrate is relatively large, the transfer of the semiconductor substrate is facilitated. In addition, since the first conductive pattern is exposed on the second surface by forming a slope having an obtuse interior angle with the second surface by bevel cutting, compared with a processing method in which a hole is first penetrated, The number of manufacturing steps and manufacturing costs can be significantly reduced.
[0101]
Note that, in order to reduce the number of manufacturing steps, the formation of the first external electrode and the formation of the first conductive pattern, or the formation of the second external electrode and the formation of the second conductive pattern may be performed simultaneously. Good.
[0102]
Further, by forming a laminated metal film including a barrier layer and a seed layer below the first conductive pattern and the second conductive pattern, constituent elements of the first conductive pattern and the second conductive pattern by the barrier layer are reduced. It is possible to suppress diffusion to the first external electrode and the semiconductor substrate and prevent the characteristics of the semiconductor chip from deteriorating, and to form the first conductive pattern and the second conductive pattern by electroplating the seed layer. it can.
[0103]
As described above, according to the method of manufacturing a semiconductor chip of the present embodiment, the surface electrode is formed on the first surface of the semiconductor substrate, and the conductive pattern is formed via the inner wall of the through hole formed in the semiconductor substrate. The first external electrode formed on the surface, the second external electrode formed on the second surface and the surface electrode are electrically connected by a conductive pattern, and the inner angle with the second surface is obtuse. A semiconductor chip having a through hole formed on a certain slope can be manufactured.
[0104]
In the semiconductor chip manufactured by the semiconductor chip manufacturing method of the present embodiment, the electrodes on both surfaces are electrically connected by a conductive pattern passing through the side surface of the semiconductor substrate. The semiconductor chip can be electrically connected, and the length of the wiring can be shortened by forming the slope, and the resin can be supplied on the slope, thereby preventing the conductive pattern from being externally impacted. Accordingly, it is possible to cope with a reduction in thickness, size, and speed of a semiconductor device in which semiconductor chips are stacked.
[0105]
Next, a second embodiment of the present invention will be described.
[0106]
FIG. 17 is a sectional view showing a semiconductor chip of the present embodiment.
[0107]
Here, the same components as those of the first embodiment are denoted by the same reference numerals, and description of common contents is omitted.
[0108]
As shown in FIG. 17, the semiconductor chip of the present embodiment differs from the semiconductor chip of the first embodiment in the thickness of the first external electrode and the thickness of the second external electrode.
[0109]
That is, in the semiconductor chip of the present embodiment, the surface of the first external electrode and the surface of the second external electrode protrude from the surface of the second insulating layer formed on the surface of the semiconductor substrate. Specifically, the surface of the first external electrode and the surface of the second external electrode protrude from the surface of the second insulating layer by securing the height of the electrode itself by plating or the like.
[0110]
Therefore, when a plurality of semiconductor chips of the present embodiment are stacked, electrical connection between the semiconductor chips can be ensured without using a connecting member.
[0111]
Next, a method for manufacturing the semiconductor chip of the present embodiment will be described.
[0112]
The method of manufacturing a semiconductor chip according to the present embodiment is obtained by adding a step of forming each external electrode after the semiconductor chip according to the first embodiment is completed. That is, after the steps shown in FIGS. 10 to 12 or FIGS. 14 to 15 shown in the first embodiment, a step for securing the height of the external electrode is added.
[0113]
That is, as shown in FIG. 17, by securing the height of the electrode itself by plating or the like, the surface of the first external electrode 21 and the surface of the second external electrode 22 are separated from the surface of the second insulating layer 23. Protrude. Accordingly, when a plurality of semiconductor chips are stacked facing each other, electrical connection between the semiconductor chips can be ensured without using a connection member, so that it is possible to achieve a reduction in thickness and speed. It becomes.
[0114]
Next, a third embodiment of the present invention will be described.
[0115]
FIG. 18 is a sectional view of the semiconductor chip of the present embodiment.
[0116]
Here, the same components as those in the first embodiment and the second embodiment are denoted by the same reference numerals, and description of common contents is omitted.
[0117]
As shown in FIG. 18, at least one conductive pattern 19 that is not electrically connected to the surface electrode formed on the surface of the semiconductor substrate has to be connected to the integrated circuit of the semiconductor chip H. Instead, the first external electrodes 21 formed on the first surface 14 of the semiconductor chip H are electrically connected to the second external electrodes 22 formed on the second surface 17.
[0118]
Therefore, the semiconductor chip of the present embodiment has a structure having a conductive pattern in which external electrodes formed on both surfaces are electrically connected but are not electrically connected to the integrated circuit.
[0119]
Next, a method for manufacturing the semiconductor chip of the present embodiment will be described.
[0120]
The method of manufacturing a semiconductor chip of the present embodiment is different from the method of manufacturing a semiconductor chip of the first embodiment in that a conductive pattern is formed on at least one arbitrary surface electrode among surface electrodes formed on a semiconductor substrate. The feature is that it does not. That is, in the method of manufacturing a semiconductor chip according to the first embodiment, the conductive pattern that electrically connects the external electrodes on both surfaces of the semiconductor chip is electrically connected to the surface electrode. By forming a conductive pattern for electrically connecting the external electrodes on both surfaces of the semiconductor chip to a portion where no is present, a conductive pattern that is not electrically connected to the integrated circuit of the semiconductor chip is formed. Therefore, a semiconductor chip that does not need to be electrically connected to the integrated circuit is sandwiched between two semiconductor chips that need to be electrically connected and stacked, thereby passing the integrated circuit of the sandwiched semiconductor chip. A semiconductor device can be realized, and the degree of freedom of electrical connection between semiconductor chips is improved.
[0121]
As described above, the three embodiments of the semiconductor chip all have a structure in which electrodes are formed on both sides of a semiconductor substrate, but differ in that the structure of the electrodes and the electrodes to be electrically connected are selective. .
[0122]
That is, the surface electrode formed on the surface of the semiconductor substrate and the external electrodes on both surfaces are electrically connected by a conductive pattern, and the height of the surface of the external electrode is ensured by plating or the like so that the insulating layer is formed. There is a form in which the external electrodes are electrically connected to each other by a conductive pattern that is not electrically connected to the surface electrode of the semiconductor substrate, and a form in which a conductive pattern that is not connected to at least one external electrode is formed. When multiple semiconductor chips are stacked, the external electrodes on the surfaces of the opposing semiconductor chips can be electrically connected to each other, and it is possible to select whether or not to electrically connect any semiconductor chip to the integrated circuit. Become.
[0123]
Next, the semiconductor device of the present invention will be described.
[0124]
Each embodiment of the semiconductor device described below is configured from each embodiment of the above-described semiconductor chip, and will be described as fourth to sixth embodiments.
[0125]
A fourth embodiment of the present invention will be described.
[0126]
FIG. 19 is a sectional view showing the semiconductor device of the present embodiment.
[0127]
As shown in FIG. 19, the semiconductor chip A, the semiconductor chip B, and the semiconductor chip C shown as the first embodiment of the semiconductor chip are stacked. External electrodes formed on both surfaces of each semiconductor chip are electrically connected via connection members.
[0128]
That is, the surface electrode 18 of the semiconductor chip C is electrically connected to the second external electrode 22 of the semiconductor chip B via the connecting member 24, and the surface electrode 18 of the semiconductor chip B is connected to the semiconductor chip via the connecting member 24. Since the semiconductor chip A, the semiconductor chip B, and the semiconductor chip C are electrically connected to the second external electrode 22 of A, they are electrically connected to each other.
[0129]
With such a configuration, in the present embodiment, the semiconductor chips A, B, and C are electrically connected to the electrodes formed on both surfaces thereof by the conductive patterns passing through the through holes of the semiconductor substrates. When the semiconductor chips are connected and stacked, when the semiconductor chips are stacked, the surfaces of the semiconductor chips are opposed to each other. Therefore, unlike a conventional semiconductor device in which a plurality of semiconductor chips are arranged in a plane, the number of stacked semiconductor chips is different. The problem that the mounting area of the semiconductor device increases as the number of semiconductor devices increases is solved.
[0130]
Also, since the electrodes arranged on both sides of each semiconductor chip are electrically connected to each other, the electrical connection of each stacked semiconductor chip is separated from the mounting substrate, unlike the conventional form of connecting the stacked semiconductor chips with metal wires. There is no need to expose the lower electrode of the semiconductor chip to the upper semiconductor chip, and it is possible not only to stack semiconductor chips of the same size but also to stack semiconductor chips of different sizes in a desired order. Therefore, there is no problem that the wiring length between the semiconductor chips becomes long.
[0131]
Further, in the conventional COC (Chip On Chip) structure in which the surfaces of the respective semiconductor chips are connected to face each other, the element formation surface on which the electrodes are formed is only one surface of the semiconductor chip. Although the number of electrodes is limited to two, the present embodiment has a structure in which electrodes can be formed on both sides of the semiconductor chip, so that the electrodes on both sides of each semiconductor chip can be electrically connected, It is possible to increase the number of layers.
[0132]
In addition, in the present embodiment, since the electrodes of the respective semiconductor chips are laminated in correspondence with each other, a plurality of semiconductor chips can be formed without increasing the thickness of the entire semiconductor device unlike a conventional semiconductor device laminated using a wiring board. Can be reduced in thickness, and the mounting area is the same as the size of the semiconductor chip to be stacked.
[0133]
As described above, the semiconductor device in which the semiconductor chips of the present embodiment are stacked enables a plurality of semiconductor chips to be stacked, and is not restricted by the size and arrangement of the stacked semiconductor chips, and the wiring length between the semiconductor chips is not limited. Since the thickness of the laminated structure is reduced without increasing the length of the semiconductor device, it is possible to realize a semiconductor device which is compatible with miniaturization, high density, and high speed without increasing the mounting area.
[0134]
In this embodiment, the case where the number of stacked semiconductor chips is three has been described. However, two or four or more semiconductor chips can be stacked.
[0135]
Next, a fifth embodiment of the present invention will be described.
[0136]
FIG. 20 is a cross-sectional view showing a semiconductor device in which electrodes of respective semiconductor chips are directly joined without using a connecting member and semiconductor chips are stacked.
[0137]
Note that portions corresponding to those of the semiconductor device of FIG. 1 are denoted by the same reference numerals as in FIG. 1, and description of contents common to FIG. 19 will be omitted.
[0138]
As shown in FIG. 20, the configuration of the electrodes, insulating layers, and conductive patterns in each semiconductor chip is the same, except that the method of electrically connecting the semiconductor chips is different from that of the fourth embodiment.
[0139]
That is, the first external electrode 21 of the semiconductor chip F is directly joined to the second external electrode 22 of the semiconductor chip E, and the first external electrode 21 of the semiconductor chip E is connected to the second external electrode 22 of the semiconductor chip D. Since the semiconductor chips are directly bonded, the three semiconductor chips D, E, and F are electrically connected to each other.
[0140]
Here, since the first external electrode 21 and the second external electrode 22 of each semiconductor chip need to protrude from the second insulating layer 23, for example, the height of the electrodes themselves is reduced by plating or the like. It is desirable to secure it.
[0141]
As described above, according to the present embodiment, the external electrodes of the semiconductor substrate are directly connected to each other without using the connecting member, so that the thickness of the semiconductor device after stacking the semiconductor chips is smaller than that of the fourth embodiment. The size of the semiconductor device can be reduced, and the wiring length can be shortened. Therefore, the thickness of the semiconductor device in which the semiconductor chips are stacked is small, and a semiconductor device which is small and operates at high speed can be realized.
[0142]
Next, a sixth embodiment will be described.
[0143]
FIG. 21 is a sectional view showing the semiconductor device of the present embodiment.
[0144]
Parts corresponding to those in FIG. 19 are denoted by the same reference numerals as those in FIG. 1, and description of common contents is omitted.
[0145]
As shown in FIG. 21, the semiconductor chip H has a different configuration from the semiconductor chip G and the semiconductor I, and does not have the first electrode or the third electrode connected to the conductive pattern. 2 shows a characteristic configuration of a chip.
[0146]
That is, in the semiconductor chips G and I, the surface electrode 18 formed on the first surface, the first external electrode 21, and the second external electrode 22 formed on the second surface are electrically connected by the conductive pattern 19. The first external electrode 21 of the semiconductor chip I is electrically connected to the second external electrode 22 of the semiconductor chip H, and is electrically connected to the first external electrode 21 of the semiconductor chip H. Although it is electrically connected to the second external electrode 22 of the semiconductor chip G but is not connected to the integrated circuit of the semiconductor chip H, it can pass through the integrated circuit of the semiconductor chip H. Thus, by stacking semiconductor chips that do not need to be electrically connected to the integrated circuit between two semiconductor chips that need to be electrically connected, electrical connection between the semiconductor chips can be achieved. The degree of freedom is improved.
[0147]
As described above, three embodiments of the semiconductor device have been described. In any of the embodiments, the semiconductor device is formed by stacking semiconductor chips, and the semiconductor device is electrically connected to the surface electrode formed on the semiconductor substrate through the conductive pattern. A semiconductor device in which a plurality of semiconductor chips having external electrodes connected to each other are stacked, wherein the external connection electrodes are electrically connected via a connection member, and the external electrodes of the semiconductor chip are directly electrically connected to each other. And at least one semiconductor chip in which external electrodes on both sides are electrically connected by a conductive pattern not connected to the surface electrode of the semiconductor substrate.
[0148]
In the fourth to sixth embodiments, a laminated metal film is formed as a base of a conductive pattern between a conductive pattern and a first resin layer and between a conductive pattern and a surface electrode. May be. The laminated metal film is composed of a barrier layer and a seed layer. The barrier layer can prevent diffusion of the constituent elements of the conductive pattern and prevent deterioration of the characteristics of the semiconductor chip. The conductive pattern can be plated. The thicknesses of the barrier layer and the seed layer constituting the laminated metal film are 0.05 to 0.35 [μm] for the barrier layer and 0.2 to 0.8 [μm] for the seed layer. In the embodiment, the thickness of the barrier layer is 0.2 [μm], and the thickness of the seed layer is 0.5 [μm].
[0149]
As described above, the semiconductor device in which the semiconductor chips having the external electrodes formed on both surfaces thereof are stacked does not increase the mounting area of the semiconductor chip and reduces the size, the density, and the speed of the wiring board and metal wires. Is possible.
[0150]
As described above, according to the semiconductor chip of the present invention, since the electrodes formed on both surfaces of the semiconductor chip are electrically connected via the conductive pattern, it is possible to stack a plurality of semiconductor chips without using metal wires, Further, by forming a slope having an obtuse interior angle with the second surface, it is possible to shorten the wiring length and protect the side surface of the semiconductor chip by supplying resin.
[0151]
Further, in the semiconductor device in which the semiconductor chips of the present invention are stacked, a plurality of semiconductor chips are electrically connected on the surface facing each other, so that the wiring length can be reduced and the thickness and mounting area of the semiconductor device can be prevented from increasing. is there.
[0152]
Further, in the method of manufacturing a semiconductor chip, the hole formed in the semiconductor substrate is made to penetrate by forming a slope having an obtuse internal angle with the second surface of the semiconductor substrate. Can be shortened. Further, in the division of the semiconductor chip unit, by cutting the resin portion supplied on the slope, problems such as chipping at the time of cutting can be prevented.
[0153]
Hereinafter, a seventh embodiment of the wiring board and the method of manufacturing the same according to the present invention will be described.
[0154]
First, the wiring board of the present embodiment will be described. FIG. 22 is a cross-sectional view of the wiring board of the present embodiment.
[0155]
As shown in FIG. 22, a through hole 109 is formed from a surface 107 to a slope 108 of a silicon substrate 106 having a thickness of 50 to 200 [μm] and made of silicon as a base material, and an inner angle with the back surface 110 is obtuse. The slope 108 thus formed forms a part of the outer shape of the wiring board 111. In the present embodiment, the through-hole 109 is formed in the vicinity of the boundary of the wiring substrate 111 in units of individual pieces, for example, at a position of 50 to 150 [μm] from the boundary. The shape of the through-hole 109 may be circular or square. In the case of a circular shape, the diameter is 10 to 20 [μm]. In the case of a square, the length of one side is 10 to 20 [μm]. It has a rounded shape instead of a right angle. Further, in the present embodiment, the inner angle between the slope 108 and the back surface 110 is 135 degrees, and the slope 108 is formed to a position of 10 to 50 [μm] from the back surface. In the present embodiment, the substrate thickness is 100 [μm], and the slope 108 is formed from the rear surface 110 to a position of 20 [μm]. A first conductive pattern 112 and a second conductive pattern 113 are formed on the front surface 107 and the rear surface 110 of the silicon substrate 106, respectively. Further, a third conductive pattern 114 is formed on the inner wall and the slope of the through hole, and the first conductive pattern 112 and the second conductive pattern 113 are electrically connected by the third conductive pattern 114. In this manner, by forming a slope having an obtuse interior angle with the back surface of the silicon substrate, the distance of the conductive pattern electrically connecting the electrodes on both surfaces of the silicon substrate is shortened, and a wiring pattern corresponding to high speed is formed. Can be secured. Note that the third conductive pattern 114 may be formed along the inner wall of the through hole or may be filled in the through hole. As a material of each of these conductive patterns, copper (Cu), gold (Au), tungsten (W), molybdenum (Mo), nickel (Ni), titanium (Ti), aluminum (Al), and the like are used. Each conductive pattern preferably has a thickness of 5 to 15 μm, and in this embodiment, 10 μm, and the material and thickness of each external electrode are the same as those of each conductive pattern.
[0156]
As a base of the conductive pattern, a laminated metal film may be formed between each conductive pattern and the first insulating layer 115. The laminated metal film has a two-layer structure in which a seed layer is laminated on the upper surface of the barrier layer. In addition, the barrier layer can prevent the diffusion of the constituent elements of each conductive pattern and the deterioration of the characteristics of the wiring board. By providing the seed layer, the conductive pattern can be plated by the electrolytic plating method. The barrier layer is made of titanium (Ti), titanium tungsten (Ti / W), chromium (Cr), nickel (Ni), or the like, and has a thickness of 0.05 to 0.35 [μm]. Is 0.2 [μm]. The seed layer is made of copper (Cu), gold (Au), silver (Ag), nickel (Ni), or the like, and has a thickness of 0.2 to 0.8 [μm]. 0.5 [μm].
[0157]
In addition, a first insulating layer 115 is formed between the silicon substrate 106 and the first conductive pattern 112, the second conductive pattern 113, and the third conductive pattern 114, and the silicon substrate 106 and each conductive pattern are formed. It is electrically insulated. Further, the front surface of the first conductive pattern 112 other than the electrode portion 116 and the back surface of the second conductive pattern 113 other than the electrode portion 117 are covered with a second insulating layer 118. And each electrode portion corresponding to each conductive pattern is formed at the same time. Each insulating layer is made of silicon dioxide (SiO2), silicon nitride (SiN), oxynitride film (SiON), polyimide film or the like having a thickness of 1 to 30 [μm]. In the case of SiN) and oxynitride film (SiON), it is 1 [μm], and in the case of polyimide film, it is 7 [μm]. Further, the second insulating layer 118 may be mainly made of a solder resist, and the thickness in this case is 30 [μm] in the present embodiment.
[0158]
In the present embodiment, each conductive pattern is formed in one layer, but two or more conductive patterns may be formed alternately with the insulating layer, and the number of layers of each conductive pattern is not limited.
[0159]
As described above, a through hole is formed in a silicon substrate based on silicon, and electrodes formed on both surfaces of the silicon substrate are electrically connected to each other through conductive patterns formed on both surfaces of the silicon substrate and the through hole. With the substrate, it is possible to achieve high-precision pattern formation and flatness on the same level as a semiconductor chip mounted on a wiring substrate, so that it is possible to realize improvement in bonding reliability.
[0160]
Next, a method for manufacturing the wiring board of the present embodiment will be described.
[0161]
Note that the same components as those in FIG. 22 are denoted by the same reference numerals.
[0162]
23 to 38 are sectional views or plan views of each step of the method for manufacturing a wiring board according to the present embodiment.
[0163]
First, as shown in FIG. 23, a silicon substrate 106 in a wafer state having a thickness of 600 to 1000 [μm] is prepared. The broken lines shown in the figure indicate the positions where both ends in the width direction of the cutting blade at the time of dicing for dividing the silicon substrate into the divided wiring board units pass, and the center of the two broken lines is This is the boundary between the individual units of the wiring board.
[0164]
FIG. 24 is a plan view showing a state in which holes are machined from the surface of the silicon substrate, and FIG. 25A is a cross-sectional view taken along a line VV ′ in FIG.
[0165]
As shown in FIGS. 24 and 25A, a hole 119 having a depth of 20 to 100 [μm] is formed by RIE (Reactive Ion Etching) without penetrating the surface 107 of the silicon substrate 106 in the thickness direction. However, the formation position of the hole 119 is formed around the individual unit of the divided wiring board. In the present embodiment, the hole 119 is formed at a position of 50 [μm] from the boundary line of the individual unit of the divided wiring board. You.
[0166]
In the present embodiment, the thickness of the silicon substrate 106 is 100 [μm], the depth of the hole 119 is 70 [μm], and the length of the through hole 109 through which the hole 119 has penetrated by forming the slope 108 in a later step. Is about 50 [μm]. Note that the method for forming the holes 119 is not limited to the RIE method, and light etching, wet etching, ultrasonic machining, electric discharge machining, and the like can be used, and the above-described various machining methods may be combined. .
[0167]
As described above, the RIE method, which is a processing method of a hole formed in a silicon substrate, is a dry etching method using reactive gas plasma, and is a method used for fine processing of a semiconductor wafer. A mask covering portions other than the holes is formed on the insulating layer so as not to be etched, and the mask is removed after etching.
[0168]
Next, as shown in FIG. 25B, a first insulating layer 120 is formed on the inner wall of the hole 119 and on the surface 107 of the silicon substrate. Here, the first insulating layer 120 is made of a material such as silicon dioxide (SiO 2), silicon nitride (SiN), oxynitride film (SiON), or polyimide by a method such as a CVD method, a sputtering method, an optical CVD method, or a coating method. Is formed.
[0169]
Next, as shown in FIG. 26C, a first laminated metal film 121 is formed on the first insulating layer 120. In the first laminated metal film 121, a seed layer is laminated on a barrier layer. It has a two-layer structure. Here, the barrier layer and the seed layer are formed by a sputtering method, a CVD method, an electron beam evaporation method, or the like. The barrier layer is made of any of titanium (Ti), titanium tungsten (Ti / W), chromium (Cr), and nickel (Ni), and the seed layer is made of copper (Cu), gold (Au), and silver (Ag). ), Nickel (Ni) or the like.
[0170]
Next, as shown in FIG. 26D, a first conductive pattern 112 is formed on the inner wall of the hole 119 and on the first laminated metal film 121 by electrolytic plating using the first laminated metal film 121 as an electrode. I do. At this time, a plating resist 122 is formed on the first laminated metal film 121 in order to obtain a desired wiring and electrode shape, and the plating resist 122 is removed after electrolytic plating. Note that the first conductive pattern 112 may be formed by filling the hole 119. Further, as a material of the first conductive pattern 112, copper (Cu), gold (Au), tungsten (W), molybdenum (Mo), nickel (Ni), titanium (Ti), aluminum (Al), or the like is used. .
[0171]
Next, as shown in FIG. 27E, using the first conductive pattern 112 as a mask, the first stacked metal film 121 in a portion other than the region where the first conductive pattern 112 is formed is removed by etching.
[0172]
Next, as shown in FIG. 27F, a second insulating layer 124 is formed by opening a part of the first conductive pattern 112 as a first external electrode 123. At this time, a second insulating layer 124 is formed. After the layer 124 is formed on the first conductive pattern 112 and the first insulating layer 120 except for the first external electrode 123, a mask in which the portion of the first external electrode 123 is opened is formed. After etching the second insulating layer 124 in the opening of the electrode 123, the mask is removed. Note that a film of silicon dioxide (SiO 2), silicon nitride (SiN), oxynitride film (SiON), polyimide, or the like is formed as the second insulating layer 124 by a CVD method, a sputtering method, an optical CVD method, a coating method, or the like. It is something.
[0173]
Next, as shown in FIG. 28, the front surface 107 of the silicon substrate 106 is adhered to the support 126 with an adhesive 125, and the silicon substrate 106 is ground from the rear surface 110 by mechanical grinding or CMP (Chemical Mechanical Polishing), and Work to a thickness of [μm]. In this embodiment, the thickness of the silicon substrate after the grinding is 100 [μm].
[0174]
Next, as shown in FIG. 29, on the back surface 110 of the silicon substrate 106, the center part of two dotted lines sandwiching the boundary of each divided wiring substrate is cut by bevel cutting, and the back surface of the silicon substrate 106 is cut. A slope 108 at an obtuse angle with 110 is formed, and the first conductive pattern 114 is exposed on the slope 108. Therefore, as shown in FIG. 25A, the hole 119 formed in the silicon substrate 106 does not need to penetrate the silicon substrate 106, and the time required for processing the hole 119 can be reduced. The processing depth of the hole 119 shown in FIG. 25A is determined by the cutting depth in bevel cutting and the tip shape of the cutting blade.
[0175]
Here, bevel cutting refers to cutting in which the thickness of the blade is relatively large and the cutting edge is formed such that the inner angle with the back surface also forms an obtuse angle with the back surface by using a cutting blade formed with a bevel. That's how. Note that the thickness of the cutting blade used for bevel cutting is desirably greater than the distance between adjacent through holes by about 100 [μm] or more. In the present embodiment, the distance between adjacent through holes is 100 [μm], and the thickness of the cutting blade used for bevel cutting is 200 [μm]. In the present embodiment, the processing method using bevel cutting has been described, but processing may be performed by etching.
[0176]
Next, as shown in FIG. 30, a third insulating layer 127 is formed on the entire surface of the slope 108 and the back surface 110 except for the portion exposed on the slope 108 of the first conductive pattern 114. At this time, the third insulating layer 127 is formed. After the insulating layer 127 is formed on the entire surface of the slope 108 and the back surface 110, a mask having an opening at the portion where the first conductive pattern 114 is exposed is formed on the third insulating layer 127, and the opening of the first conductive pattern 114 is formed. After the portion of the third insulating layer 127 is etched, the mask is removed. Note that as the third insulating layer 127, a film such as silicon dioxide (SiO2), silicon nitride (SiN), an oxynitride film (SiON), or polyimide was formed by a CVD method, a sputtering method, an optical CVD method, coating, or the like. Things.
[0177]
Further, the third insulating layer 127 is preferably formed using a material whose etching rate is higher than that of the first insulating layer 120. That is, when opening the third insulating layer 127 by etching, even if a mask shift occurs, the third insulating layer 127 is selectively etched without substantially etching the first insulating layer 120. This is because the opening can be formed and the first insulating layer 120 is not partially removed.
[0178]
Next, as shown in FIG. 31, a second laminated metal film 128 is formed on the entire surface of the inclined surface 108 and the rear surface 110. The second laminated metal film 128 has a two-layer structure in which a seed layer is laminated on a barrier layer. The barrier layer and the seed layer are formed by a sputtering method, a CVD method, an electron beam evaporation method, or the like. Titanium (Ti), titanium tungsten (Ti / W), chromium (Cr), nickel (Ni), etc. are used for the barrier layer, and copper (Cu), gold (Au), silver (Ag), Nickel (Ni) or the like is used.
[0179]
Next, as shown in FIG. 32, a second conductive pattern 129 having a desired wiring and electrode shape is formed on the inclined surface 108 and the back surface 110 by an electrolytic plating method using the second laminated metal film 128 as an electrode. Thus, the second conductive pattern 129 is electrically connected to the first conductive pattern 114 exposed from the slope 108 via the second stacked metal film 128. At this time, in order to form desired wiring and electrode shapes, a plating resist 130 is formed on a portion of the second laminated metal film 128 where the second conductive pattern 129 does not need to be formed, After the electrolytic plating, the plating resist 130 is removed. Further, as a material of the second conductive pattern 129, copper (Cu), gold (Au), tungsten (W), molybdenum (Mo), nickel (Ni), titanium (Ti), aluminum (Al), or the like is used. Can be
[0180]
Next, as shown in FIG. 33, the second stacked metal film 128 other than the region where the second conductive pattern 129 is formed is removed by etching using the second conductive pattern 129 as a mask.
[0181]
Next, as shown in FIG. 34, a fourth insulating layer 132 is formed on the entire back surface 110 and the slope 108 except for the opening of the second external electrode 131. At this time, after the fourth insulating layer 132 is formed on the entire surface of the inclined surface 108 and the rear surface 110, a mask having an opening at the portion of the second external electrode 131 is formed, and the fourth portion of the opening of the second external electrode 131 is formed. After etching the insulating layer 132, the mask is removed. Note that the fourth insulating layer 132 is formed of a film such as silicon dioxide (SiO 2), silicon nitride (SiN), an oxynitride film (SiON), or polyimide by a CVD method, a sputtering method, a photo CVD method, a coating method, or the like. Is formed.
[0182]
Next, as shown in FIG. 35, dicing is performed on the inside of both ends in the width direction of the cutting blade shown by broken lines in FIG. Is formed at a right angle.
[0183]
Through such a series of manufacturing processes of the wiring substrate, the first external electrode is formed on the surface of the wiring substrate in a state exposed from the second insulating layer, and the second external electrode is formed on the back surface. Are formed so as to be exposed from the fourth insulating layer, and the first external electrode and the second external electrode are electrically connected to each other.
[0184]
The positions where the first external electrodes and the second external electrodes are formed are not particularly limited, and the external electrodes are formed at positions corresponding to the electrodes of the semiconductor chip to be mounted and the electrodes at the junction with the motherboard, respectively. It should be done.
[0185]
36 to 38 are cross-sectional views showing a process of supplying a resin to the slope and curing the same after the process shown in FIGS. The steps shown in FIGS. 36 to 38 are intended to reinforce the slope.
[0186]
As shown in FIG. 36, after the step shown in FIG. 33 or FIG. 34, the liquid resin is applied to the bevel-cut portion until the upper surface thereof becomes the height of the back surface, thereby forming the second external electrode 131. An insulating resin layer 135 is formed on the entire surface of the back surface 110 and the slope 108 except for the opening.
[0187]
The liquid resin is preferably a resin such as polyimide which can relieve stress.
[0188]
Next, as shown in FIG. 37, dicing is performed from the back surface centering on the scribe line 133 to form a side surface perpendicular to the back surface.
[0189]
Next, as shown in FIG. 38, the adhesive 125 and the support 126 are removed, and the wiring board 106 is divided into individual pieces.
[0190]
The shape of the through-hole or the hole may be circular or square. In the case of a circular shape, the diameter is 10 to 20 [μm], and in the case of a square, the length of one side is 10 to 20 [μm]. Is 20 [μm]. Here, when the shape of the hole is a quadrangle, the corner of the quadrangle is not a right angle but a rounded shape. In addition, it is also possible to process a through-hole or a hole whose diameter or side length is smaller than 10 [μm] by technical innovation of the RIE method.
[0191]
Further, the thickness of the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer is 1 to 30 μm, and in this embodiment, silicon dioxide (SiO 2) ₂ ), 1 [μm] for silicon nitride (SiN) and oxynitride film (SiON), and 7 [μm] for polyimide. Further, the second insulating layer and the fourth insulating layer may be mainly made of a solder resist, and the thickness in this case is 30 [μm] in the present embodiment.
[0192]
Further, the thickness of the first conductive pattern 12 and the second conductive pattern 13 is preferably 5 to 15 [μm], and is 10 [μm] in the present embodiment.
[0193]
In this embodiment, after applying the liquid resin on the slope, dicing of the cured liquid resin portion can prevent defects such as chipping at the time of cutting, and the insulating resin layer having a relatively large thickness perpendicular to the back surface can be prevented. In addition, since the corners of the silicon substrate formed in step (1) are formed and the wiring substrate can be divided into individual pieces, the side surfaces of the wiring substrate can be reinforced and the second conductive pattern on the slope can be protected.
[0194]
As described above, in this embodiment, in addition to the steps of forming various insulating layers, a step of forming a hole halfway from the first surface of the silicon substrate and a step of forming a slope from the back surface and penetrating the hole. And a step of forming a conductive pattern via a hole and a slope, whereby a structure in which electrodes formed on both surfaces of the silicon substrate are electrically connected to each other can be realized.
[0195]
Furthermore, after forming the first conductive pattern in the hole formed in the silicon substrate, the first conductive pattern is exposed on the back surface by forming a slope that reaches the hole and has an obtuse internal angle with the back surface. Since it is not necessary to form a hole deeply or to polish a silicon substrate thinly, it is possible to realize a reduction in processing time and a reduction in processing cost. In addition, since the degree of freedom of the thickness of the wiring substrate is increased, the transfer of the silicon substrate becomes easy. In addition, since the first conductive pattern is exposed on the back surface by forming a slope having an obtuse interior angle with the back surface by bevel cutting, the number of manufacturing steps and manufacturing cost are reduced as compared with the processing method of first penetrating holes. Can be significantly reduced.
[0196]
Further, by forming a laminated metal film including a barrier layer and a seed layer below the first conductive pattern and the second conductive pattern, constituent elements of the first conductive pattern and the second conductive pattern by the barrier layer are reduced. Diffusion to the first electrode and the silicon substrate can be suppressed, and characteristics of the semiconductor chip can be prevented from deteriorating. The first conductive pattern and the second conductive pattern can be formed by electrolytic plating on the seed layer. .
[0197]
As described above, according to the method of manufacturing a wiring substrate of the present embodiment, a conductive pattern is formed via the inner wall of the through hole formed in the silicon substrate, and the first external electrode formed on the first surface and the conductive pattern are formed on the back surface. It is possible to manufacture a wiring board in which the formed second external electrode is electrically connected by the conductive pattern, and a through hole is formed on a slope having an obtuse interior angle with the back surface.
[0198]
In the wiring board manufactured by the method for manufacturing a wiring board according to the present embodiment, the electrodes on both sides are electrically connected by a conductive pattern passing through the side surface of the silicon substrate. Substrates can be joined.
[0199]
Further, by forming a slope on the wiring board, it is possible to ensure the shortening of the wiring length, and by supplying a resin on the slope, it is possible to prevent external impact on the conductive pattern.
[0200]
Next, an eighth embodiment of the present invention will be described.
[0201]
The contents common to the seventh embodiment are omitted, and the same components are denoted by the same reference numerals.
[0202]
FIG. 39 is a cross-sectional view of the wiring board of the present embodiment.
[0203]
As shown in FIG. 39, the wiring board according to the present embodiment has a hole 109, a first insulating layer 115, a second insulating layer 118, a first conductive pattern 112, Are formed, and the first conductive pattern 112 and the second conductive pattern 113 are electrically connected by the third conductive pattern 114. Unlike the seventh embodiment, the wiring board of the present embodiment has a low-stress resin layer 136 between the silicon substrate 106 and the second conductive pattern 113. As a material for the low stress resin layer, an epoxy resin, a phenol resin, a polyimide resin, a silicon resin, an acrylic resin, and a bismalimide resin are suitable. In the present embodiment, an epoxy resin is used. In the present embodiment, the low-stress resin layer is provided between the silicon substrate and the second conductive pattern, but may be provided between the silicon substrate and the first conductive pattern. The low-stress resin layer preferably has a thickness of 5 to 100 [μm] and is 20 [μm] in the present embodiment. However, it is preferable that the thickness be as thin as possible in order to reduce the thickness of the wiring board. The thickness of the low-stress resin layer is adjusted in accordance with characteristics such as elastic modulus and shrinkage ratio, which vary depending on the type, the size of the substrate, the temperature at the time of mounting, and the characteristics of the members such as the material of the motherboard and the material of the solder.
[0204]
As described above, the stress generated by the temperature change generated between the motherboard and the motherboard can be reduced by the low-stress resin layer, and the mounting reliability on the motherboard can be improved.
[0205]
Next, a method for manufacturing the wiring board of the present embodiment will be described.
[0206]
In the present embodiment, after the mechanical grinding or the CMP step of the back surface 110 of the silicon substrate shown in FIG. 28 in the seventh embodiment, a step of forming a low stress resin layer on the back surface of the silicon substrate is provided. ing. That is, a liquid low-stress resin before curing is applied to the back surface of the silicon substrate, and a low-stress resin layer is formed only at a necessary portion by exposure and development, followed by heating and curing. The surface of the low-stress resin may be processed by a CMP method in order to flatten the surface after curing.
[0207]
Next, the semiconductor device of the present invention will be described.
[0208]
Each embodiment of the semiconductor device described below is composed of each embodiment of the wiring substrate described above, and will be described as a ninth embodiment and a tenth embodiment.
[0209]
A ninth embodiment of the present invention will be described.
[0210]
The semiconductor device of the present embodiment uses the wiring board of the seventh embodiment. The contents common to the seventh embodiment are omitted, and the same components are denoted by the same reference numerals. ing.
[0211]
FIG. 40 is a sectional view of the semiconductor device of the present embodiment.
[0212]
The semiconductor device of this embodiment is obtained by mounting one or more semiconductor chips 137 on the wiring board shown in the seventh embodiment, and mounting the wiring board 111 on a motherboard 139 by using bumps 138. . The wiring substrate 111 has a silicon substrate 106 as a base material, and the silicon substrate 106 has an inclined surface 108 formed at an obtuse angle with the back surface 110, and a plurality of through holes 109 reaching the inclined surface 108 from the surface 107 of the silicon substrate 106. A first conductive pattern 112 formed in the front surface 107 and the through hole 109 of the silicon substrate 106, and a second conductive pattern 113 formed in the back surface 110 and the slope 108 are formed. The first conductive pattern 112 and the second conductive pattern 113 are directly electrically connected at a connection portion between the through hole 109 and the slope 108. Note that a first insulating layer 115 is formed and electrically insulated between the first conductive pattern 112 and the silicon substrate 106 and between the second conductive pattern 113 and the silicon substrate 106. Further, the surface of the first conductive pattern 112 other than the electrode part 116, the surface of the second conductive pattern 113 other than the electrode part 117, and the slope 108 are covered with the second insulating layer 118.
[0213]
As described above, the semiconductor chip is electrically connected to the first conductive pattern of the silicon wiring board via the metal bump, and the second conductive pattern is electrically connected to the motherboard via the bump.
[0214]
By using the silicon-based wiring board of the present embodiment, the thermal expansion characteristics of the semiconductor chip and the wiring board become substantially the same, the reliability of the joint can be secured, and the flatness and dimensions of the wiring board Since the accuracy is improved as compared with the conventional resin wiring board, high-density mounting corresponding to the wiring density of the semiconductor chip becomes possible. In addition, by interposing metal bumps at the joint between the wiring board and the motherboard, it is possible to reduce the stress at the joint and improve the joint reliability.
[0215]
Next, a tenth embodiment of the present invention will be described.
[0216]
The semiconductor device of the present embodiment uses the wiring board of the eighth embodiment, and the contents common to the eighth embodiment are omitted, and the same components are denoted by the same reference numerals. It is attached.
[0219]
FIG. 41 is a cross-sectional view of the semiconductor device of the present embodiment.
[0218]
As shown in FIG. 41, in the wiring board of the semiconductor device of this embodiment, a low-stress resin layer 136 is formed between the silicon substrate 106 and the second conductive pattern 113. Note that the low-stress resin layer 136 may be formed between the silicon substrate 106 and the first conductive pattern 112.
[0219]
According to the present embodiment, the stress generated between the wiring board and the motherboard due to the temperature change is reduced by the low-stress resin layer, and the mounting reliability of the motherboard on the wiring board can be improved. In addition, with a semiconductor device in which a semiconductor chip is mounted on a wiring substrate made of silicon as a base material, the thermal expansion characteristics of the semiconductor chip and the wiring substrate are substantially the same, so that the reliability of the bonding portion can be ensured and the metal bumps can be formed. Since the stress at the joint between the used wiring board and the motherboard is reduced, the bonding reliability is improved, and the flatness and dimensional accuracy of the wiring board using the silicon substrate improve the bonding stability, miniaturization and high density. And high speed can be realized.
[0220]
In the ninth and tenth embodiments, the semiconductor chip is mounted on the wiring board. However, electronic components other than the semiconductor chip may be mounted.
[0221]
As described above, according to each of the embodiments of the semiconductor device of the present invention, by using the same silicon as the material of the semiconductor chip for the wiring board, the thermal stress generated at the junction between the semiconductor chip and the wiring board during heating at the time of mounting the semiconductor chip Is reduced, the bonding reliability is improved, and the wiring pattern formed on the wiring board has the same flatness and dimensional accuracy as the wiring pattern formed on the semiconductor chip. High-density mounting can be realized. Further, by mounting the wiring board on the motherboard via the metal bumps, the stress due to the metal bumps can be reduced, and the bonding reliability is improved.
[0222]
Further, the slope can be shortened by forming a slope having an obtuse interior angle with the back surface of the wiring board as a part of the outer shape of the wiring board, thereby shortening the wiring, and forming the resin on the slope to protect the conductive pattern. A semiconductor device having a semiconductor chip mounted thereon can be realized.
[0223]
Further, by forming a low-stress resin layer on the front surface or the back surface of the silicon substrate, the stress generated between the wiring substrate and the motherboard can be reduced, and the bonding reliability is improved.
[0224]
As described above, according to the wiring substrate and the method of manufacturing the same of the present invention, the electrodes on both surfaces of the silicon substrate are electrically connected via the conductive patterns formed in the through holes. Therefore, the semiconductor device using this wiring board reduces the stress of each bonding portion via the metal bumps to increase the reliability, and the flatness and dimensional accuracy of the wiring board using silicon improve the stability and the bonding of the bonding. The wiring density is improved, and miniaturization, high density, and high speed can be realized.
[0225]
Further, the slope can be shortened by forming a slope having an obtuse interior angle with the back surface of the wiring board as a part of the outer shape of the wiring board, thereby shortening the wiring, and forming the resin on the slope to protect the conductive pattern. A semiconductor device on which a semiconductor chip is mounted can be realized, and a low-stress resin layer is formed on the back surface of the silicon substrate as described above, so that the stress generated between the wiring substrate and the motherboard is reduced. And bonding reliability is improved.
[0226]
An eleventh embodiment of the present invention will be described with reference to FIG. FIG. 42 is a sectional view of the multichip semiconductor device according to the eleventh embodiment of the present invention. This multi-chip semiconductor device has three semiconductor chips 1 ₁ , 1 ₂ , 1 ₃ Are laminated. Each semiconductor chip 1 ₁ , 1 ₂ , 1 ₃ Comprises a semiconductor substrate 202 having on its surface an integrated device (not shown) and a multilayer conductive pattern (not shown) formed thereon, and the semiconductor substrate 202 is formed at an acute angle with the surface. A first electrode 205 formed on the front surface, a second electrode 206 formed on the back surface, and a plurality of concave portions 204 formed around the front surface. A conductive pattern 207 for connecting the first electrode 205 and the second electrode 206 is formed so as to extend inside the concave portion 204 and on the inclined surface 203 and extend to the front surface and the back surface. An insulating layer 208 is formed between the first electrode 205 and the semiconductor substrate 202, between the second electrode 206 and the semiconductor substrate 202, and between the conductive pattern 207 and the semiconductor substrate 202. In addition, each semiconductor chip 1 ₁ , 1 ₂ , 1 ₃ Each of the multilayer wirings (not shown) on the semiconductor substrate 202 is provided with a surface electrode 209, and the surface electrode 209 is electrically connected to the conductive pattern 207. In addition, each semiconductor chip 1 ₁ , 1 ₂ , 1 ₃ The entire surface of the first electrode 205 and the second electrode 206 other than the openings is covered with an insulating layer 210. Semiconductor chip 1 ₁ The first electrode 205 is connected to the semiconductor chip 1 via a connection member 211 such as a metal bump. ₂ Is electrically connected to the second electrode 206. Thereby, the semiconductor chip 1 ₁ Is the semiconductor chip 1 ₂ It is electrically connected to. Similarly, semiconductor chip 1 ₂ The first electrode 205 is connected to the semiconductor chip 1 via the connecting member 211. ₃ Electrically connected to the second electrode 206 of the semiconductor chip 1 ₂ Is the semiconductor chip 1 ₃ Is electrically connected to Thus, the semiconductor chip 1 ₁ , 1 ₂ , 1 ₃ The connection is made electrically.
[0227]
According to the present embodiment, the semiconductor chip 1 ₁ , 1 ₂ , 1 ₃ Therefore, unlike a conventional multichip semiconductor device in which a plurality of semiconductor chips are arranged in a plane, there is no problem that the area of the device increases as the number of semiconductor chips increases.
[0228]
In addition, the semiconductor chip 1 ₁ ~ 1 ₃ Semiconductor chip 1 for connection via electrodes 205 and 206 arranged on the front and back surfaces of ₁ ~ 1 ₃ Unlike a conventional multi-chip semiconductor device in which semiconductor chips are stacked and connected by metal wires, there is no restriction that the area of the semiconductor chip in the upper layer must be smaller and the lower surface electrode must be exposed. In addition to stacking semiconductor chips, semiconductor chips of different sizes can be stacked in a desired order, and there is no problem that the wiring length between the semiconductor chips becomes long.
[0229]
Furthermore, unlike the conventional multi-chip semiconductor device having the COC structure in which the surfaces are connected face to face via electrodes arranged on the front and back surfaces of the semiconductor chip, the number of stacked semiconductor chips is limited to two. It is not done. Since only semiconductor chips are stacked, unlike a conventional multi-chip semiconductor device in which the semiconductor chips are stacked using a wiring board, the height of the stacked semiconductor chips can be reduced, and the size of the semiconductor chips to be stacked can be reduced by the mounting area of the device. can do.
[0230]
Therefore, according to the present embodiment, the mounting area is small, the size and order of the semiconductor chips to be stacked are not limited, the wiring length between the semiconductor chips is short, the stacking height is low, and the number of stacked semiconductor chips is two. A small, high-density, high-speed multichip semiconductor device capable of more than one device can be realized.
[0231]
In this embodiment, the case where the number of stacked semiconductor chips is three has been described. However, with the structure of this embodiment, connection can be similarly performed even when the number of stacked semiconductor chips is four or more.
[0232]
FIG. 43 is a sectional view of the multichip semiconductor device according to the twelfth embodiment of the present invention. Parts corresponding to those of the multi-chip semiconductor device in FIG. 42 are denoted by the same reference numerals as those in FIG. 42, and detailed description is omitted.
[0233]
The present embodiment is an example in which the connection members 211 are not used for connecting the electrodes 205 and 206. Semiconductor chip 1 ₁ The first electrode 205 of the semiconductor chip 1 ₂ Is directly bonded to the second electrode 206. Thereby, the semiconductor chip 1 ₁ Is the semiconductor chip 1 ₂ It is electrically connected to. Semiconductor chip 1 ₂ The first electrode 205 is directly bonded to and electrically connected to the second electrode 206 of the semiconductor chip 213. Thus, the semiconductor chip 1 ₁ , 1 ₂ , 1 ₃ The connection is made electrically.
[0234]
According to the present embodiment, by directly connecting the electrodes without using a connecting member, the stacked height can be further reduced, and the wiring length can be shortened. Therefore, the same effects as those of the first embodiment can be obtained, and furthermore, a multi-chip semiconductor device having a shorter wiring length between semiconductor chips, a lower stacking height, and a smaller size and higher speed can be realized.
[0235]
FIGS. 44 to 46 are process cross-sectional views illustrating a method for manufacturing a semiconductor chip of a multichip semiconductor device according to the thirteenth embodiment of the present invention.
First, a semiconductor substrate 212 in a wafer state is prepared as shown in FIG. The semiconductor substrate 212 has an element (not shown) and a multilayer conductive pattern (not shown) formed on the surface thereof. The multilayer conductive pattern is provided with a surface electrode 213, and the semiconductor substrate 212 has a desired area on the surface. Has an insulating layer 214 made of SiN and a resin layer 215 made of polyimide. Note that the insulating layer 214 and the resin layer 215 may or may not be formed of another material.
[0236]
Next, as shown in FIG. 44B, a concave portion 217 is formed on the surface of the semiconductor substrate 12 so as to straddle the scribe line 216 by RIE. At this time, a mask is formed so that other portions are not etched, and the mask is removed after the etching. The depth of the recess 217 is 20 to 100 μm. FIG. 47 shows a partial plan view at this time. FIGS. 44 (b) and 47 (b) are cross-sectional views taken along line VV 'of FIG. 47 (a). Note that the method for forming the recess 217 is not limited to the RIE method, and light etching, wet etching, ultrasonic processing, electric discharge processing, or the like can also be used. Further, the above processing methods may be combined.
[0237]
Next, as shown in FIG. 44C, a first insulating layer 218 is formed on the entire surface including the inner wall of the concave portion 217 except for the opening of the surface electrode 213. At this time, after forming the first insulating layer 218 over the entire surface, a mask is formed. After the first insulating layer 218 in the opening of the surface electrode 213 is etched, the mask is removed. Note that the first insulating layer 218 is made of SiO. ₂ , SiN, SiON, a polyimide film, and other layers are formed by a CVD method, a sputtering method, an optical CVD method, coating, or the like.
[0238]
Next, as shown in FIG. 44D, a laminated metal film in which a barrier layer 219 and a seed layer 220 are sequentially laminated on the entire surface is formed. As a method for forming the barrier layer 219 and the seed layer 220, a sputtering method, a CVD method, an electron beam evaporation method, or the like is used. The barrier layer uses Ti, Ti / W, Cr or Ni, and the seed layer uses Cu, Au, Ag, Ni or the like.
[0239]
Next, as shown in FIG. 44E, the recess 217 is buried and the first conductive pattern 221 is formed in a desired wiring and electrode shape by electrolytic plating using the seed layer 220 as an electrode. At this time, a plating resist 222 is formed on the seed layer 220 in order to obtain desired wiring and electrode shapes, and the plating resist 222 is removed after electrolytic plating. Cu, Au, W, Mo, Ni, Ti, Al, or the like is used as the first conductive pattern.
[0240]
Next, as shown in FIG. 44 (f), the seed layer 220 other than the region where the first conductive pattern 221 is formed is removed by etching using the first conductive pattern 221 as a mask. The barrier layer 219 other than the region where the first conductive pattern 221 is formed is removed by etching using the mask 221 as a mask.
[0241]
Next, as shown in FIG. 44G, a second insulating layer 224 is formed over the entire surface of the first electrode 223 except for the opening. At this time, after forming the second insulating layer 224 over the entire surface, a mask is formed. After the second insulating layer 224 in the opening of the first electrode 223 is etched, the mask is removed. Note that the second insulating layer 224 is formed using a layer such as a SiO2, SiN, SiON, or polyimide film by a CVD method, a sputtering method, an optical CVD method, coating, or the like.
[0242]
As a result, only the first electrode 223 electrically connected to the surface electrode 213 is formed on the wafer surface in a state exposed from the second insulating layer 224.
[0243]
Next, as shown in FIG. 45A, the wafer surface is bonded to a support 226 with an adhesive 225, and the semiconductor substrate 212 is polished from the back surface to reduce the thickness to a desired thickness. The polishing method may be mechanical polishing or CMP. The thickness of the semiconductor substrate is 50 to 200 μm.
[0244]
Next, as shown in FIG. 45B, a slope 227 forming an acute angle with the front surface is formed from the back surface of the semiconductor substrate 212 by bevel cutting, and the slope 227 is formed so that the first conductive pattern 221 can be seen from the back surface. At the same time, and dividing the semiconductor chip 228 into semiconductor chips.
[0245]
Note that the processing method may be etching.
[0246]
Next, as shown in FIG. 45C, a third insulating layer 229 is formed on the slope 227 and the entire back surface of the first conductive pattern 221 except for the portion exposed on the slope 227. At this time, after forming the third insulating layer 229 on the slope 227 and the entire back surface, a mask is formed, and after the third insulating layer 229 in the opening of the first conductive pattern 221 is etched, the mask is removed. . Note that the third insulating layer 229 is made of SiO. ₂ , SiN, SiON, a polyimide film, and other layers are formed by a CVD method, a sputtering method, an optical CVD method, coating, or the like.
[0247]
The third insulating layer 229 is preferably formed using a material whose etching rate is higher than those of the first insulating layer 218 and the second insulating layer 224.
[0248]
Thus, when the third insulating layer 229 is opened by etching, even if a mask shift occurs, the first insulating layer 218 and the second insulating layer 224 are hardly etched, and the third insulating film 229 is formed. 229 can be selectively etched to form an opening, and the first insulating layer 218 and the second insulating layer 224 covering the first conductive pattern 221 are not partially removed.
[0249]
Next, as shown in FIG. 45D, a laminated metal film in which the barrier layer 230 and the seed layer 231 are sequentially laminated on the entire slope 227 and the rear surface is formed. The barrier layer 230 and the seed layer 231 are formed by a sputtering method, a CVD method, an electron beam evaporation method, or the like. The barrier layer 230 uses Ti, Ti / W, Cr, or Ni, and the seed layer 231 uses Cu, Au, Ag, Ni, or the like.
[0250]
Next, as shown in FIG. 46A, desired wiring and electrode are formed on the inclined surface 227 and the back surface by electrolytic plating using the seed layer 231 as an electrode so as to be connected to the first conductive pattern 221 exposed from the inclined surface 227. The second conductive pattern 232 having the shape shown in FIG. At that time, a plating resist 233 is formed on the seed layer 231 in order to obtain a desired wiring and electrode shape, and after the electrolytic plating, the plating resist 233 is removed. As the second conductive pattern 232, Cu, Au, W, Mo, Ni, Ti, Al, or the like is used.
[0251]
Next, as shown in FIG. 46B, the seed layer 231 other than the region where the second conductive pattern 232 is formed is removed by etching using the second conductive pattern 232 as a mask. The barrier layer 230 other than the region where the second conductive pattern 232 is formed is removed by etching using the 232 as a mask.
[0252]
Next, as shown in FIG. 46C, a fourth insulating layer 235 is formed on the slope 227 and the entire back surface except for the opening portion of the second electrode 234 and the scribe line 216. At this time, after forming the fourth insulating layer 235 on the slope 227 and the entire back surface, a mask is formed, and the fourth insulating layer 235 at the opening of the second electrode 234 and the fourth insulating layer on the scribe line 216 are formed. After etching the layer 235 and the third insulating layer 229, the mask is removed. Note that the fourth insulating layer 235 is made of SiO. ₂ , SiN, SiON, a polyimide film, and other layers are formed by a CVD method, a sputtering method, an optical CVD method, coating, or the like.
[0253]
Next, as shown in FIG. 46D, the adhesive 225 and the support 226 are removed, and the semiconductor chip 228 is divided into individual pieces.
[0254]
As a result, only the first electrode 223 is formed on the front surface of the semiconductor chip 228 so as to be exposed from the second insulating layer 224, and only the second electrode 234 is exposed on the back surface from the fourth insulating layer 235. Thus, a structure in which the surface electrode 213, the first electrode 223, and the second electrode 234 are electrically connected is completed.
[0255]
As described above, the present embodiment includes the step of forming the concave portion 217 on the surface of the semiconductor substrate 212 so as to straddle the scribe line 216 and the step of bevel-cutting the scribe line 216 from the back surface. A structure in which the first electrode 223 and the second electrode 234 which are electrically connected to each other and are also electrically connected to the front electrode 213 can be formed on the front surface and the rear surface of the chip of the semiconductor substrate 212, respectively.
[0256]
Therefore, according to the present embodiment, after the first conductive pattern 221 is formed on the front surface side of the semiconductor substrate 212 where the concave portion 217 is formed, the second conductive pattern 221 is formed on the back surface side where the inclined surface 227 forming an acute angle with the front surface is formed. By simply forming the pattern 232, it is possible to form a conductive line from the front surface to the back surface, and it is possible to easily form the front and back conductive electrodes.
[0257]
Further, according to the present embodiment, the first conductive pattern 221 is formed in recess 217 formed in a wafer state, and then the surface is cut at an acute angle at the center of recess 217, whereby the first conductive pattern 221 is formed. Since a part of the wiring 221 can be seen from the back surface, the concave portion 217 does not need to be formed extremely deep, and the semiconductor substrate 212 does not need to be polished extremely thin. The degree of freedom is large, the number of manufacturing steps can be reduced, and the cost of a chip for a multi-chip semiconductor device can be reduced.
[0258]
Further, according to the present embodiment, the step of forming the first electrode 223 and the step of forming the first conductive pattern 221 can be performed simultaneously, and the step of forming the second electrode 234 and the step of forming Since the step of forming the second conductive pattern 232 can be performed at the same time, the number of manufacturing steps can be further reduced.
[0259]
Further, according to the present embodiment, the slope 227 forming an acute angle with the front surface is formed by bevel cutting, the semiconductor chip 228 is divided into individual pieces, and the first conductive pattern is made visible from the back surface. Can be performed at the same time, and the number of manufacturing steps and manufacturing cost can be significantly reduced as compared with the case where the forming is performed by other means.
[0260]
Since the barrier layer (219, 230) and the seed layer (220, 231) are always formed under the first conductive pattern 221 and the second conductive pattern 232, the barrier layer (219, 230) The deterioration of the characteristics of the semiconductor chip due to the diffusion of the constituent elements of the first conductive pattern 221 and the second conductive pattern 232 into the surface electrode 213 and the semiconductor substrate 212 can be prevented, and the seed layers (220, 231) can be used. The first conductive pattern 221 and the second conductive pattern 232 can be formed by electrolytic plating.
[0261]
FIG. 49 is a cross-sectional view showing a case where the line of the bevel cut is shifted in the step of FIG. 45 (b), and is denoted by the same reference numeral as FIG. In FIG. 49, AA 'indicates a line to be originally cut, and BB' indicates a case where the line is deviated. By making the width of the recess sufficiently large so that the bottom surface of the recess 217 is always cut even in the case of such displacement, the first conductive pattern 221 exposed on the slope cut and formed by each line is formed. The distances C and D from the center to the contact point between the slope and the back surface are equal, and the shape and position of the exposed first conductive pattern 221 can be stabilized.
[0262]
FIG. 50 is a view showing another method in the step of FIG. 44 (b), and portions common to FIG. 44 are denoted by the same reference numerals. A groove 237 is formed by dicing on the surface of the semiconductor substrate 212 instead of the recess 217 in the step of FIG. The depth of the groove 237 is 20 to 100 μm. By forming them collectively by dicing, the number of steps can be reduced and the formation can be performed in a short time as compared with the case of forming by etching.
[0263]
FIG. 48 is a process sectional view illustrating the method for manufacturing the semiconductor chip of the multi-chip semiconductor device according to the fourteenth embodiment of the present invention. 44, 45, and 46 are denoted by the same reference numerals as those in FIGS. 44, 45, and 46, and will not be described in detail. In the present embodiment, after the step of FIG. 46B of the thirteenth embodiment, as shown in FIG. 48A, the entire back surface except for the slope 227 and the opening of the second electrode 234 is formed. A liquid resin is applied so as to be flat and cured to form an insulating resin layer 236. Although the present embodiment is performed after the step of FIG. 46B, it may be performed after the step of FIG. As the liquid resin, a resin such as polyimide which can relieve stress is preferable.
[0264]
Next, as shown in FIG. 48B, dicing is performed from the back surface to form side surfaces perpendicular to the front surface.
[0265]
Next, as shown in FIG. 48C, the adhesive 225 and the support 226 are removed, and the semiconductor chip 228 is divided into individual pieces.
[0266]
As described above, in the present embodiment, the side surface formed by the inclined surface 227 can be embedded with the liquid resin, and the cured liquid resin portion is formed by dicing to form the thick insulating resin layer 236 perpendicular to the surface. At the same time, it is possible to separate the pieces into pieces at the same time.
[0267]
Therefore, the side surface of the multi-chip semiconductor device chip can be reinforced and the protection of the second conductive pattern 232 on the slope 227 can be enhanced.
[0268]
FIG. 51 is a sectional view of the multichip semiconductor device according to the fifteenth embodiment of the present invention. Parts corresponding to those of the multi-chip semiconductor device in FIG. 42 are denoted by the same reference numerals as those in FIG. 42, and the details are omitted.
[0269]
The feature of this embodiment is that the semiconductor chip 1 ₂ Is that at least one of the front and back conductive electrodes formed is not connected to the surface electrode.
[0270]
This multi-chip semiconductor device has three semiconductor chips 1 ₁ , 1 ₂ , 1 ₃ Are laminated. Semiconductor chip 1 ₁ And 1 ₃ In the semiconductor chip 1, a first electrode 205 formed on the front surface, a second electrode 206 formed on the back surface, and a front electrode 209 are electrically connected by a conductive pattern 207. ₂ Has a conductive pattern 238 that is not electrically connected to at least one surface electrode 209, and the conductive pattern 238 includes a first electrode 239 formed on the front surface and a second electrode 240 formed on the back surface. Electrically connected.
[0271]
Thereby, the semiconductor chip 1 ₂ Semiconductor chip 1 electrically connected to the second electrode 240 of FIG. ₁ Of the first electrode 205 and the semiconductor chip 1 ₂ Semiconductor chip 1 electrically connected to the first electrode 239 of FIG. ₃ The second electrode 206 is electrically connected to the semiconductor chip 1 ₂ Will not be connected to this integrated circuit.
[0272]
Therefore, according to the present embodiment, the semiconductor chip 1 ₂ Electrodes (205, 206) that do not need to be electrically connected to the integrated circuit of the ₁ And 1 ₃ The electrodes (205, 206) are connected to the semiconductor chip 1 ₂ The semiconductor chip 1 is connected to the front and back conductive electrodes (239, 240) that are not electrically connected to the integrated circuit formed on the semiconductor chip 1. ₂ Can be passed.
[0273]
A sixteenth embodiment of the present invention will be described with reference to FIG. FIG. 52 is a sectional view of a multi-chip semiconductor device using a silicon wiring substrate according to a sixteenth embodiment of the present invention.
[0274]
As shown in FIG. 52, in this multi-chip semiconductor device, a plurality of electronic components such as a plurality of semiconductor chips 308 are mounted on the surface of a silicon wiring board 301 alone or in a stacked manner, and mounted on a mother board 307 using solder balls 306. It has a configuration. The silicon wiring substrate 301 has a silicon substrate 305 made of silicon, and has a first conductive pattern 302 formed on the front surface, a second conductive pattern 303 formed on the back surface, and a third conductive pattern 303 formed on the side surface. And a pattern 304. The first conductive pattern 302 and the second conductive pattern 303 are electrically connected via a third conductive pattern 304. The first conductive pattern 302 has at least one layer for mounting and wiring electronic components 308, and the second conductive pattern 303 has at least one layer having electrodes for mounting on the motherboard 7.
[0275]
An insulating layer 310 is formed between the first conductive pattern 302 and the silicon substrate 305, between the second conductive pattern 303 and the silicon substrate 305, and between the third conductive pattern 304 and the silicon substrate 305. It is electrically insulated. The entire surface of the silicon wiring substrate 301 other than the electrode portions of the first conductive pattern 302 and the electrode portions of the second conductive pattern 303 is covered with an insulating layer 311. The semiconductor chip 308 is electrically connected to the first conductive pattern 302 of the silicon wiring substrate 301 via the metal bump 309. The second conductive pattern 303 of the silicon wiring board 301 is electrically connected to the motherboard 7 via the solder balls 306. In this way, each of the plurality of semiconductor chips 308 is electrically connected to each of the semiconductor chips 308 via the silicon wiring substrate 301 and also to the motherboard 307.
[0276]
For the wiring substrate for a multi-chip semiconductor device, a step of forming a first conductive pattern 302 on the front surface of a silicon wafer, a step of forming a second conductive pattern 303 on the back surface of the silicon wafer, And forming a third conductive pattern 304 on the side surface that electrically connects the first conductive pattern 302 and the second conductive pattern 303 to each other. .
[0277]
After the step of forming the first conductive pattern, a step of dividing the silicon wafer into individual silicon substrates to form side surfaces is performed, and thereafter, a step of forming a second conductive pattern and a step of forming the third conductive pattern are performed. The step of forming a pattern may be performed simultaneously.
[0278]
According to this embodiment, a wiring substrate using silicon as a base material can be obtained, and a multi-chip semiconductor device using the same can reduce the stress at the joints of the metal bumps, increase the reliability, and improve the wiring substrate. The flatness and dimensional accuracy of the above enhance the bonding stability, enable the wiring density to be improved at a level that cannot be achieved by a resin wiring board, and realize a small size, high density, and high speed.
[0279]
A seventeenth embodiment of the present invention will be described with reference to FIG. FIG. 53 is a sectional view of a multi-chip semiconductor device using a silicon wiring substrate according to a seventeenth embodiment of the present invention.
[0280]
As shown in FIG. 53, in this multi-chip semiconductor device, electronic components such as a plurality of semiconductor chips 308 are mounted on the surface of a silicon wiring board 312 singly or in a stacked manner, and mounted on a mother board 307 using solder balls 306. It has a configuration. The silicon wiring substrate 312 is made of a silicon substrate 305. The silicon substrate 305 has four inclined surfaces 314 formed at acute angles with the surface and a plurality of recesses 313 formed around the surface. The first conductive pattern 302 is formed on the front surface and the concave portion 313, and the second conductive pattern 303 is formed on the rear surface and the inclined surface 314. The first conductive pattern 302 and the second conductive pattern 303 are directly electrically connected at a joint between the concave portion 313 and the slope 314. The first conductive pattern 302 has at least one layer for mounting and wiring the electronic component 308, and the second conductive pattern 303 has at least one layer having electrodes for mounting on the motherboard 307. When the silicon substrate 312 is used upside down, the first conductive pattern 302 has at least one layer having electrodes for mounting on the motherboard 317, and the second conductive pattern 303 mounts and wiring electronic components. For at least one layer.
[0281]
Further, an insulating layer 310 is formed between the first conductive pattern 2 and the silicon substrate 305 and between the second conductive pattern 303 and the silicon substrate 305 to be electrically insulated. The entire surface of the silicon wiring substrate 312 other than the electrode portion of the first conductive pattern 302 and the electrode portion of the second conductive pattern 303 is covered with an insulating layer 311. The semiconductor chip 308 is electrically connected to the first conductive pattern 302 of the silicon wiring substrate 312 via the metal bump 309. The second conductive pattern 303 of the silicon wiring board 312 is electrically connected to the motherboard 307 via the solder balls 306. In this way, each of the plurality of semiconductor chips 308 is electrically connected to each of the semiconductor chips 308 via the silicon wiring substrate 301 and also to the motherboard 307.
[0282]
According to this embodiment, a wiring substrate using silicon as a base material can be easily obtained, and a multi-chip semiconductor device using the same can reduce the stress at the joints of the metal bumps and increase the reliability, The flatness and dimensional accuracy of the wiring board enhance the bonding stability, enable the wiring density to be improved at a level that cannot be achieved by the resin wiring board, and realize small size, high density, and high speed.
[0283]
An eighteenth embodiment of the present invention will be described with reference to FIG. FIG. 54 is a sectional view of a multi-chip semiconductor device using a silicon wiring substrate according to the third embodiment of the present invention. As shown in FIG. 54, the silicon wiring substrate 315 of this multi-chip semiconductor device has a low-stress resin layer 316 between the second conductive pattern 303 and the silicon substrate 305. The parts corresponding to those of the multi-chip semiconductor device of FIG. 52 are denoted by the same reference numerals as those of FIG. 52, and detailed description is omitted.
[0284]
According to this embodiment, the stress caused by a temperature change between the motherboard and the motherboard can be reduced by the resin layer, and the mounting reliability on the motherboard can be improved. Further, the resin layer 316 of this embodiment may be applied to the multi-chip semiconductor device of FIG. In this embodiment mode, the case where the second conductive pattern 303 is connected to the motherboard 307 is shown. However, when the second conductive pattern 303 is used upside down, that is, when the first conductive pattern 302 is connected to the motherboard 307, the first conductive pattern 303 is connected. A low-stress resin layer 316 is formed between the pattern 302 and the silicon substrate 305. In order to further reduce the stress, a low-stress resin layer 316 is formed both between the first conductive pattern 302 and the silicon substrate 305 and between the second conductive pattern 303 and the silicon substrate 305. Is also good.
[0285]
A nineteenth embodiment of the present invention will be described with reference to FIGS. 55 to 57 are process cross-sectional views illustrating a method for manufacturing a multi-chip semiconductor device wiring board according to a nineteenth embodiment of the present invention. FIG. 58 is a multi-chip semiconductor device chip according to a nineteenth embodiment of the present invention. FIG. 4 is a plan view showing a method for forming a concave portion of FIG.
[0286]
As shown in FIG. 57D, the silicon wiring board 330 has a side surface (slope 329) formed at an acute angle to the surface and a recess 319 formed around the surface, as in the second embodiment. A first conductive pattern 323 formed on the surface of the silicon substrate 317 and at least one layer having an electrode formed in the concave portion 319, and formed on the back surface and side surfaces of the silicon substrate 317; A second conductive pattern 334 connected to the first conductive pattern 323 and having at least one layer having electrodes.
[0287]
Next, a method of manufacturing the wiring board for a multi-chip semiconductor device having the above configuration will be described. First, as shown in FIG. 55A, a silicon substrate 317 in a wafer state is prepared.
[0288]
Next, as shown in FIG. 55B, a concave portion 319 is formed on the surface of the silicon substrate 317 by RIE so as to straddle the scribe line 318. At this time, a mask is formed so that other portions are not etched, and the mask is removed after the etching. The depth of the recess 319 is 20 to 100 μm. FIG. 58 shows a partial plan view at this time. FIG. 55B is a cross-sectional view taken along line VV ′ of FIG. Note that the method of forming the concave portion 319 is not limited to the RIE method, and light etching, wet etching, ultrasonic processing, electric discharge processing, or the like can also be used. Further, the above processing methods may be combined.
[0289]
Next, as shown in FIG. 55C, a first insulating layer 320 is formed on the entire surface including the inner wall of the concave portion 319. Note that the first insulating layer 320 is made of SiO ₂ , SiN, SiON, a polyimide film, and other layers are formed by a CVD method, a sputtering method, an optical CVD method, coating, or the like.
[0290]
Next, as shown in FIG. 55D, a laminated metal film in which a barrier layer 321 and a seed layer 322 are sequentially laminated on the entire surface is formed. As a method for forming the barrier layer 321 and the seed layer 322, a sputtering method, a CVD method, an electron beam evaporation method, or the like is used. The barrier layer 321 uses Ti, Ti / W, Cr or Ni, and the seed layer 322 uses Cu, Au, Ag, Ni, or the like.
[0291]
Next, as shown in FIG. 55 (e), the concave portion 319 is buried and the first conductive pattern 323 is formed in a desired wiring and electrode shape by electrolytic plating using the seed layer 322 as an electrode. At this time, a plating resist 324 is formed on the seed layer 322 in order to obtain a desired wiring and electrode shape, and after the electrolytic plating, the plating resist 324 is removed. As the wiring material, Cu, Au, W, Mo, Ni, Ti, Al or the like is used.
[0292]
Next, as shown in FIG. 55 (f), the seed layer 322 other than the region where the first conductive pattern 323 is formed is removed by etching using the first conductive pattern 323 as a mask. The barrier layer 321 other than the region where the first conductive pattern 323 is formed is removed by etching using the mask 323 as a mask.
[0293]
Next, as shown in FIG. 55 (g), a second insulating layer 325 is formed on the entire surface excluding the first conductive pattern electrode portion 326. At this time, after forming the second insulating layer 325 over the entire surface, a mask is formed. After the second insulating layer 325 on the first conductive pattern electrode portion 326 is etched, the mask is removed. Note that the second insulating layer 325 is made of SiO. ₂ , SiN, SiON, a polyimide film, and other layers are formed by a CVD method, a sputtering method, an optical CVD method, coating, or the like.
[0294]
As a result, only the first conductive pattern electrode portion 326 is formed on the wafer surface in a state exposed from the second insulating layer 325.
[0295]
Next, as shown in FIG. 56 (a), the wafer surface is bonded to the support 327 with an adhesive 328, and the silicon substrate 317 is polished from the back surface to reduce the thickness to a desired thickness. The polishing method may be mechanical polishing, chemical polishing or CMP. The thickness of the silicon substrate 317 is 50 to 200 μm.
[0296]
Next, as shown in FIG. 56B, bevel cutting is performed by a scribe line from the back surface of the silicon substrate 317 to form an inclined surface 329 that forms an acute angle with the front surface, and the first conductive pattern 323 is removed from the back surface. The exposure to the slope 329 and the division to the silicon wiring substrate 330 are performed at the same time. Note that the processing method may be etching.
[0297]
Next, as shown in FIG. 56 (c), a third insulating layer 331 is formed on the slope 329 and the entire back surface of the first conductive pattern 323 except for the portion exposed on the slope 329. At this time, after forming the third insulating layer 331 on the slope 329 and the entire back surface, a mask is formed. After the third insulating layer 331 in the opening of the first conductive pattern 323 is etched, the mask is removed. . Note that the third insulating layer 331 is made of SiO ₂ , SiN, SiON, a polyimide film, and other layers are formed by a CVD method, a sputtering method, an optical CVD method, coating, or the like. It is preferable that the third insulating layer 331 be formed using a material whose etching rate is higher than that of the first insulating layer 320 and the second insulating layer 325. Thus, when the third insulating layer 331 is etched and opened, even if a mask shift occurs, the first insulating layer 320 and the second insulating layer 325 are hardly etched, and the third insulating film is formed. The opening 331 can be selectively etched to prevent the first insulating layer 320 and the second insulating layer 325 covering the first conductive pattern 323 from being partially removed.
[0298]
Next, as shown in FIG. 56D, a laminated metal film in which a barrier layer 332 and a seed layer 333 are sequentially laminated on the entire slope 329 and the rear surface is formed. As a method for forming the barrier layer 332 and the seed layer 333, a sputtering method, a CVD method, an electron beam evaporation method, or the like is used. The barrier layer uses Ti, Ti / W, Cr or Ni, and the seed layer uses Cu, Au, Ag, Ni or the like.
[0299]
Next, as shown in FIG. 57 (a), a desired plating is performed by electrolytic plating using the seed layer 333 as an electrode to electrically connect the first conductive pattern 323 exposed from the slope 329 to the slope 329 and the back. A second conductive pattern 334 is formed in the shape of the wiring and the electrode. At this time, a plating resist 335 is formed on the seed layer 333 in order to obtain desired wiring and electrode shapes, and the plating resist 335 is removed after electrolytic plating. As the wiring material, Cu, Au, W, Mo, Ni, Ti, Al or the like is used.
[0300]
Next, as shown in FIG. 57B, the seed layer 333 other than the region where the second conductive pattern 334 is formed is removed by etching using the second conductive pattern 334 as a mask. The barrier layer 332 other than the region where the second conductive pattern 334 is formed is removed by etching using the 334 as a mask.
[0301]
Next, as shown in FIG. 57C, a fourth insulating layer 336 is formed on the entire back surface including the inclined surface 329 except for the second conductive pattern electrode portion 337 and the adhesive 328. At this time, after forming the fourth insulating layer 336 on the inclined surface 329 and the entire back surface, a mask is formed, and the fourth insulating layer 336 on the second conductive pattern electrode portion 337 and the fourth portion of the adhesive 328 are formed. After etching the insulating layer 336 and the third insulating layer 331, the mask is removed. Note that the fourth insulating layer 336 is formed using a layer such as a SiO2 film, a SiN film, a SiON film, or a polyimide film by a CVD method, a sputtering method, an optical CVD method, coating, or the like.
[0302]
Next, as shown in FIG. 57D, the adhesive 328 and the support 327 are removed to obtain a silicon wiring substrate 330.
[0303]
As a result, only the first conductive pattern electrode portion 326 is formed on the surface of the silicon wiring substrate 330 so as to be exposed from the second insulating layer 325, and only the second conductive pattern electrode portion 337 is formed on the back surface of the silicon wiring substrate 330. A structure in which the first conductive pattern electrode portion 326 on the front surface and the second conductive pattern electrode portion 337 on the rear surface are electrically connected to each other is formed in a state exposed from the insulating layer 336.
[0304]
As described above, in the present embodiment, the surface of the silicon substrate 317 is provided with the step of forming the concave portion 319 so as to straddle the scribe line 318 and the step of bevel-cutting the scribe line 318 from the back surface. Only by forming a conductive pattern from the back and back surfaces, a structure having electrodes electrically connected to each other on the front and back surfaces of the silicon wiring substrate 330 can be formed.
[0305]
Therefore, according to the present embodiment, the front and back conductive electrodes can be easily formed.
[0306]
Further, according to the present embodiment, after forming the first conductive pattern 323 in the concave portion 319 formed in a wafer state, the first conductive pattern 323 is cut at a central portion of the concave portion 319 with the surface at an acute angle. Since the part for the wiring can be seen from the back surface, the concave portion 319 does not need to be formed extremely deep, and the silicon substrate 317 does not need to be extremely thinly polished. The degree of freedom is large, the number of manufacturing steps can be reduced, and the cost can be reduced.
[0307]
Further, according to the present embodiment, the slope 329 forming an acute angle with the front surface is formed by bevel cutting, the silicon wiring substrate 330 is divided into individual pieces, and the first conductive pattern 323 is seen from the back surface. Can be performed at the same time, and the number of manufacturing steps and the manufacturing cost can be greatly reduced as compared with the case where they are formed by other means.
[0308]
A twentieth embodiment of the present invention will be described with reference to FIG. FIG. 59 is a process sectional view showing the method for manufacturing the multi-chip semiconductor device wiring substrate according to the twentieth embodiment of the present invention.
[0309]
As shown in FIG. 59 (c), this silicon wiring board 330 has a side surface (slope 329) formed at an acute angle with the surface and a recess 319 around the surface, as in the second embodiment. A first conductive pattern 323 formed on the surface of the silicon substrate 317 and at least one layer having an electrode formed in the concave portion 319, and formed on the back surface and side surfaces of the silicon substrate 317; A second conductive pattern 334 having at least one electrode and connected to the first conductive pattern 323 is provided, and an insulating layer 338 is formed on a side surface so as to be perpendicular to the surface of the silicon substrate 317.
[0310]
Next, a method of manufacturing the wiring board for a multi-chip semiconductor device having the above configuration will be described. 55 to 57 are denoted by the same reference numerals as those in FIGS. 55 to 57, and detailed description is omitted.
[0311]
In this embodiment, after the step of FIG. 57B of the nineteenth embodiment, as shown in FIG. 59A, the entire back surface and the slope 329 except for the second conductive pattern electrode portion 337 are provided. An insulating resin layer 338 is formed. At this time, a liquid resin is applied to the inclined surface 329 and the entire back surface so as to be flat, and is formed by exposing and developing so as to open the second conductive pattern electrode portion 337. In the present embodiment, the process is performed after the step of FIG. 57B, but may be performed after the process of FIG. 57C. As the liquid resin, a resin such as polyimide which can relieve stress is preferable.
[0312]
Next, as shown in FIG. 59 (b), dicing is performed from the back surface using scribe lines to form side surfaces perpendicular to the front surface.
[0313]
Next, as shown in FIG. 59 (c), the adhesive 328 and the support 327 are removed to obtain a silicon wiring substrate 330.
[0314]
As described above, in this embodiment, the side surface formed by the slope 329 can be embedded with the liquid resin, and the hardened liquid resin portion is formed by dicing to form the thick insulating resin layer 338 perpendicular to the surface. At the same time, it is possible to separate the pieces into pieces at the same time.
[0315]
Therefore, it is possible to reinforce the side surface of the wiring board for a multi-chip semiconductor device and to enhance protection of the second conductive pattern 334 on the slope 329.
[0316]
The above embodiment is an example, and the present invention is not limited to the above embodiment. In addition, various modifications can be made without departing from the scope of the present invention.
[0317]
【The invention's effect】
According to the wiring board of the first aspect, the formation of the slope makes it unnecessary to form the hole deeply, so that the processing time can be reduced and the cost can be reduced. In addition, since it is not necessary to grind the silicon substrate to reduce its thickness, stable conveyance can be ensured.
[0318]
According to the wiring board of the second aspect, the first conductive pattern for mounting and wiring the electronic components on the front surface and the second conductive pattern including electrodes for mounting on the motherboard on the rear surface are provided, and the first conductive pattern is provided. A wiring substrate made of silicon is obtained in which the conductive pattern and the second conductive pattern are electrically connected by the third conductive pattern formed on the side surface.
[0319]
This silicon wiring board does not change its shape due to humidity and is made of the same silicon as the semiconductor chip, so the shape change such as expansion and contraction due to temperature change is the same as that of the semiconductor chip, and the flatness is high because it is formed by polishing. In addition, the dimensional accuracy of the electrode position is high, and the pitch of the connection electrodes at the same level as that of the semiconductor chip can be narrowed and the wiring density can be increased.
[0320]
Therefore, a multi-chip semiconductor device using such a silicon wiring board can reduce the stress at the joints of the metal bumps to increase the reliability, improve the bonding stability by the flatness and dimensional accuracy of the wiring board, It is possible to improve the wiring density at a level that cannot be achieved by a wiring board, and it is possible to realize compactness, high density, and high speed.
[0321]
According to the wiring board of the third aspect, the first conductive pattern is provided on the front surface and the second conductive pattern is provided on the back surface, and the first conductive pattern and the second conductive pattern are directly electrically connected. Thus, a wiring substrate made of silicon can be obtained.
[0322]
Therefore, a multi-chip semiconductor device using such a silicon wiring board can reduce the stress at the joints of the metal bumps to increase the reliability, improve the bonding stability by the flatness and dimensional accuracy of the wiring board, It is possible to improve the wiring density at a level that cannot be achieved by a wiring board, and it is possible to realize compactness, high density, and high speed.
[0323]
According to the wiring board of the fourth aspect, in addition to the same effects as those of the first or third aspect, the side face of the wiring board can be reinforced and the protection of the conductive pattern on the side face can be improved.
[0324]
According to the fifth aspect of the present invention, in addition to the same effects as those of the first, second, and third aspects, it is possible to reduce stress caused by a temperature change between the semiconductor chip and the wiring board. Thus, the mounting reliability of the semiconductor chip can be improved.
[0325]
According to the method of manufacturing a wiring board according to the sixth aspect, since the hole is made to penetrate by forming the slope from the back surface of the wiring board, the processing time of the hole can be reduced, and the processing cost can be reduced.
[0326]
According to the method of manufacturing a wiring board according to claim 7, the method has a first conductive pattern for mounting and wiring electronic components on the front surface and a second conductive pattern including electrodes for mounting on the motherboard on the back surface. A wiring board made of silicon is obtained in which the first conductive pattern and the second conductive pattern are electrically connected by the third conductive pattern formed on the side surface. Further, it is possible to easily realize a multi-chip semiconductor wiring substrate having a front electrode and a back electrode electrically connected from a silicon substrate in a wafer state via a conductive pattern passing through a side surface. Further, after the step of forming the first conductive pattern, a step of dividing the silicon wafer into individual silicon substrates to form side surfaces is performed, and thereafter, a step of forming a second conductive pattern and a step of forming the third conductive pattern Since the step of forming the substrate is performed simultaneously, the number of manufacturing steps can be reduced.
[0327]
According to the method of manufacturing a wiring board according to the eighth aspect, the first conductive pattern has the first conductive pattern on the front surface and the second conductive pattern on the back surface, and the first conductive pattern and the second conductive pattern are directly electrically connected. A wiring substrate made of connected silicon is obtained. Further, since the concave portion and the side surface forming an acute angle with the front surface are formed in the wiring substrate, it is possible to form a wiring that conducts between the front and back surfaces only by forming a conductive pattern from the front surface and the back surface. Further, a multi-chip semiconductor wiring substrate having a front electrode and a back electrode electrically connected from a silicon substrate in a wafer state via a conductive pattern passing through a side surface can be easily realized.
[0328]
According to the method of manufacturing a wiring board according to the ninth aspect, in addition to the same effect as the sixth aspect or the eighth aspect, the liquid resin is supplied on the slope, and the cured resin portion is diced to be divided into individual pieces of the substrate. Thus, the resin absorbs mechanical interference generated by cutting resistance at the time of dicing and distortion caused by frictional heat, thereby preventing problems such as chipping.
[0329]
According to the method of manufacturing a wiring board according to the tenth aspect, in addition to the same effects as the sixth and eighth aspects, it is possible to reduce stress caused by a temperature change generated between the semiconductor chip and the wiring board, The mounting reliability of the semiconductor chip can be improved.
[0330]
According to the semiconductor device of the eleventh aspect, the semiconductor chip having the first external electrode and the second external electrode connected via the conductive pattern formed on the inner wall and the slope of the through hole is laminated, and both surfaces thereof are stacked. A semiconductor device in which the semiconductor chips are electrically connected via the electrodes described above is obtained. Since the semiconductor chips are not arranged in a plane on the wiring board, the mounting area can be reduced. Further, since there is no need to provide electrodes for connecting metal wires, two or more semiconductor chips of the same size and different sizes can be stacked in a desired order, and the wiring length between the semiconductor chips can be increased. , And the thickness of the stacked layers can be reduced, and a semiconductor device corresponding to miniaturization, high density, and high speed can be realized.
[0331]
According to the semiconductor device of the twelfth aspect, a multi-chip type semiconductor with a small mounting area, a short wiring length between each semiconductor chip, a low stacking height, small size, high density, and high speed. The device can be realized.
[0332]
According to the semiconductor device of claim 13, a semiconductor chip having a first external electrode and a second external electrode connected via a conductive pattern is laminated, and the first external electrode and the second external electrode are stacked. Since each semiconductor chip is electrically connected via the semiconductor chip, the mounting area is small and the same size semiconductor chips can be stacked without arranging a plurality of semiconductor chips in a plane on the wiring board. It is also possible to stack semiconductor chips of different sizes in a desired order, and the wiring length between the semiconductor chips is short, the stacking height is low, and the number of stacked semiconductor chips is two or more. A high-density and high-speed multi-chip semiconductor device can be realized. Further, since the semiconductor substrate has a slope formed at an acute angle with the surface and a concave portion formed around the surface, the semiconductor chip can be easily manufactured.
[0333]
According to the semiconductor device of the fourteenth aspect, in addition to the same effects as in the thirteenth aspect, a multi-layered semiconductor chip having a shorter wiring length and a lower stacking height in the plane of the semiconductor chip is provided. A chip semiconductor device is obtained. Therefore, it is possible to realize a small-sized, high-density, high-speed multi-chip semiconductor device having a small mounting area, a short wiring length between the semiconductor chips, a low stacking height.
[Brief description of the drawings]
FIG. 1 is a sectional view showing a semiconductor chip according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a manufacturing step of the semiconductor chip according to the first embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a manufacturing step of the semiconductor chip of the first embodiment of the present invention.
FIG. 4 is a sectional view illustrating a manufacturing step of the semiconductor chip according to the first embodiment of the present invention;
FIG. 5 is a cross-sectional view showing a manufacturing step of the semiconductor chip according to the first embodiment of the present invention.
FIG. 6 is a sectional view illustrating a manufacturing step of the semiconductor chip according to the first embodiment of the present invention;
FIG. 7 is a sectional view illustrating a manufacturing step of the semiconductor chip according to the first embodiment of the present invention;
FIG. 8 is a sectional view illustrating a manufacturing step of the semiconductor chip according to the first embodiment of the present invention;
FIG. 9 is a sectional view illustrating a manufacturing step of the semiconductor chip according to the first embodiment of the present invention;
FIG. 10 is a sectional view illustrating a manufacturing step of the semiconductor chip according to the first embodiment of the present invention;
FIG. 11 is a sectional view illustrating a manufacturing step of the semiconductor chip according to the first embodiment of the present invention;
FIG. 12 is a sectional view illustrating a manufacturing step of the semiconductor chip according to the first embodiment of the present invention;
FIG. 13 is a sectional view illustrating a manufacturing step of the semiconductor chip according to the first embodiment of the present invention;
FIG. 14 is a sectional view illustrating a manufacturing step of the semiconductor chip according to the first embodiment of the present invention;
FIG. 15 is a sectional view illustrating a manufacturing step of the semiconductor chip according to the first embodiment of the present invention;
FIG. 16 is a sectional view illustrating a manufacturing step of the semiconductor chip according to the first embodiment of the present invention;
FIG. 17 is a sectional view showing a semiconductor chip according to a second embodiment of the present invention.
FIG. 18 is a sectional view showing a semiconductor chip according to a third embodiment of the present invention.
FIG. 19 is a sectional view showing a semiconductor device according to a fourth embodiment of the present invention.
FIG. 20 is a sectional view showing a semiconductor device according to a fifth embodiment of the present invention.
FIG. 21 is a sectional view showing a semiconductor device according to a sixth embodiment of the present invention.
FIG. 22 is a sectional view of a wiring board according to a seventh embodiment of the present invention.
FIG. 23 is a cross-sectional view of each step of the method for manufacturing a wiring board of the present invention.
FIG. 24 is a plan view showing each step of the method for manufacturing a wiring board according to the present invention;
FIG. 25 is a cross-sectional view of each step of the method for manufacturing a wiring board of the present invention.
FIG. 26 is a cross-sectional view of each step of the method for manufacturing a wiring board of the present invention.
FIG. 27 is a cross-sectional view of each step of the method for manufacturing a wiring board of the present invention.
FIG. 28 is a cross-sectional view of each step of the method for manufacturing a wiring board of the present invention.
FIG. 29 is a cross-sectional view of each step of the method for manufacturing a wiring board of the present invention.
FIG. 30 is a cross-sectional view of each step of the method for manufacturing a wiring board of the present invention.
FIG. 31 is a cross-sectional view of each step of the method for manufacturing a wiring board of the present invention.
FIG. 32 is a sectional view of each step of the method for manufacturing a wiring board according to the present invention;
FIG. 33 is a cross-sectional view of each step of the method for manufacturing a wiring board of the present invention.
FIG. 34 is a cross-sectional view of each step of the method for manufacturing a wiring board of the present invention.
FIG. 35 is a cross-sectional view of each step of the method for manufacturing a wiring board of the present invention.
FIG. 36 is a cross-sectional view of each step of the method for manufacturing a wiring board of the present invention.
FIG. 37 is a cross-sectional view of each step of the method for manufacturing a wiring board of the present invention.
FIG. 38 is a cross-sectional view of each step of the method for manufacturing a wiring board of the present invention.
FIG. 39 is a sectional view of a wiring board according to an eighth embodiment of the present invention.
FIG. 40 is a sectional view of a semiconductor device using a wiring board according to a ninth embodiment of the present invention.
FIG. 41 is a sectional view of a semiconductor device using a wiring board according to a tenth embodiment of the present invention.
FIG. 42 is a sectional view of a multi-chip semiconductor device according to an eleventh embodiment of the present invention.
FIG. 43 is a sectional view of a multichip semiconductor device according to a twelfth embodiment of the present invention.
FIG. 44 is a process sectional view illustrating the method for forming the surface of the chip for a multi-chip semiconductor device according to the thirteenth embodiment of the present invention;
FIG. 45 is a process sectional view of the first half showing the method of forming the back surface of the chip for a multi-chip semiconductor device according to the thirteenth embodiment of the present invention;
FIG. 46 is a process sectional view of the latter half showing the method of forming the back surface of the chip for a multi-chip semiconductor device according to the thirteenth embodiment of the present invention.
FIG. 47 (a) is a plan view showing a method for forming a concave portion of a multi-chip semiconductor device chip according to a thirteenth embodiment of the present invention, and FIG. 47 (b) is a cross-sectional view taken along the line VV ′.
FIG. 48 is a process sectional view illustrating the method of manufacturing the semiconductor chip in the multi-chip semiconductor device according to the fourteenth embodiment of the present invention;
FIG. 49 is a cross-sectional view showing a case where a bevel cut line is shifted.
FIG. 50 is a perspective view showing another method for forming the concave portion.
FIG. 51 is a sectional view of a multi-chip semiconductor device according to a fifteenth embodiment of the present invention.
FIG. 52 is a sectional view of a multichip semiconductor device using a silicon wiring substrate according to a sixteenth embodiment of the present invention.
FIG. 53 is a cross-sectional view of a multichip semiconductor device using a silicon wiring substrate according to a seventeenth embodiment of the present invention.
FIG. 54 is a cross-sectional view of a multi-chip semiconductor device using a silicon wiring substrate according to an eighteenth embodiment of the present invention.
FIG. 55 is a process sectional view illustrating the method of manufacturing the multi-chip semiconductor device wiring substrate according to the nineteenth embodiment of the present invention;
FIG. 56 is a process sectional view after FIG. 55;
FIG. 57 is a process sectional view after FIG. 56;
FIG. 58 is a plan view illustrating a method of forming a concave portion in a multi-chip semiconductor device chip according to a nineteenth embodiment of the present invention.
FIG. 59 is a process sectional view illustrating the method for manufacturing the wiring substrate for a multichip semiconductor device of the twentieth embodiment of the present invention.
FIG. 60 is a cross-sectional view showing a conventional semiconductor device.
FIG. 61 is a cross-sectional view showing a conventional semiconductor device.
FIG. 62 is a cross-sectional view showing a conventional semiconductor device.
FIG. 63 is a cross-sectional view showing a conventional semiconductor device.
FIG. 64 is a cross-sectional view of a conventional semiconductor device.
[Explanation of symbols]
1 wiring board
2 semiconductor chips
3 metal bumps
4 wiring board
5 semiconductor chips
6 metal wire
7 semiconductor chips
8 metal bumps
9 semiconductor chips
10 metal bumps
11 wiring board
12 metal bumps
13 semiconductor substrate
14 first side
15 slopes
16 through holes
17 Second Surface
18 surface electrodes
19 conductive pattern
20 first insulating layer
21 first external electrode
22 second external electrode
23 second insulating layer
24 connecting members
25 surface insulation layer
26 holes
27 First laminated metal film
28 first conductive pattern
29 plating resist
30 adhesive
31 support
32 third insulating layer
33 second laminated metal film
34 second conductive pattern
35 plating resist
36 fourth insulating layer
37 scribe lines
38 sides
39 semiconductor chips
40 insulating resin layer
106 silicon substrate
107 surface
108 Slope
109 Through hole
110 back
111 Wiring board
112 First conductive pattern
113 Second conductive pattern
114 Third conductive pattern

Claims (14)

A wiring substrate having a base made of silicon, wherein the wiring substrate has a plurality of through holes, a first conductive pattern is formed on a surface of the wiring substrate, and the through holes form a back surface of the wiring substrate. An inner angle is provided on a slope formed at an obtuse angle, a second conductive pattern is formed on the back surface and the slope, and the first conductive pattern and the second conductive pattern are formed on the plurality of through holes. A wiring board, which is electrically connected by the formed third conductive pattern. A wiring board for a multi-chip semiconductor device in which an electronic component is mounted on a wiring board and mounted on a motherboard, wherein the wiring board has a silicon substrate made of silicon, and the electronic component is mounted on a surface of the silicon substrate. A first conductive pattern composed of at least one layer for wiring, and a second conductive pattern composed of at least one layer having electrodes for mounting on the motherboard on the back surface of the silicon substrate; A wiring substrate, wherein a conductive pattern and the second conductive pattern are electrically connected by a third conductive pattern formed on a side surface of the silicon substrate. A wiring board for a multi-chip semiconductor device in which an electronic component is mounted on a wiring board and mounted on a motherboard, wherein the wiring board is formed at an acute angle with a surface, a side surface is formed, and a recess is formed around the surface. A first conductive pattern formed on the surface of the silicon substrate and at least one layer having an electrode formed in the concave portion, and the first conductive pattern formed on the back surface and the side surface of the silicon substrate. A second conductive pattern connected to the pattern and comprising at least one layer having electrodes. 4. The wiring board according to claim 1, wherein an insulating layer is formed on a side surface so as to be perpendicular to a surface of the board. 4. The wiring according to claim 1, further comprising a low-stress resin layer between at least one of the first conductive pattern and the substrate and between the second conductive pattern and the substrate. substrate. Forming a hole from the front surface of the silicon substrate, forming a first conductive pattern in the front surface and the hole, and forming an obtuse angle with the back surface of the silicon substrate at an obtuse angle on a substrate piece unit of the back surface. Exposing the first conductive pattern by forming the hole in a region sandwiching the boundary of the first conductive pattern and exposing the second conductive pattern electrically connected to the first conductive pattern; Forming a wiring board on a slope. Forming at least one first conductive pattern for mounting and wiring electronic components on the surface of the silicon wafer; and forming at least one layer having electrodes for mounting on a motherboard on the back surface of the silicon wafer. Forming a second conductive pattern, dividing the silicon wafer into individual silicon substrates to form side surfaces, and electrically connecting the first conductive pattern and the second conductive pattern. Forming a third conductive pattern on the side surface, and after forming the first conductive pattern, performing a step of forming the side surface by dividing the silicon wafer into individual silicon substrates, A step of forming a second conductive pattern and a step of forming a third conductive pattern are performed simultaneously. Method of manufacturing a substrate. Forming a recess around the surface of the silicon substrate in a wafer state, forming a first conductive pattern comprising at least one layer having electrodes on the surface and the recess, and forming a slope at an acute angle with the surface On the silicon substrate; and electrically connecting the back surface and the inclined surface of the silicon substrate with a first conductive pattern to form a second conductive pattern including at least one layer having electrodes. A method for manufacturing a wiring board for a multichip semiconductor device. Forming an insulating layer on an inclined surface so as to form a right angle with the surface of the silicon substrate, wherein the insulating layer is formed by applying and curing a liquid resin, and is divided into individual pieces by dicing. 9. The method for manufacturing a wiring board for a multi-chip semiconductor device according to claim 6. 9. The wiring board according to claim 6, further comprising a step of forming a low-stress resin layer between the substrate and the first conductive pattern or between the substrate and the second conductive pattern. Manufacturing method. A semiconductor substrate, a first external electrode formed on a first surface of the semiconductor substrate, a second external electrode formed on a second surface of the semiconductor substrate, and a through-hole formed on the semiconductor substrate. And a through hole is provided on a slope formed such that an inner angle with the second surface is formed at an obtuse angle, and the first external electrode and the second external electrode are connected to each other through the through hole. A plurality of semiconductor chips electrically connected by a conductive pattern formed via the inner wall and the inclined surface of the semiconductor chip, wherein the first external electrode and the second external electrode are respectively electrically connected. A semiconductor device, wherein the semiconductor device is stacked by stacking. A semiconductor substrate, a first external electrode formed on a first surface of the semiconductor substrate, a second external electrode formed on a second surface of the semiconductor substrate, and a through-hole formed on the semiconductor substrate. And a through hole is provided on a slope formed such that an inner angle with the second surface is formed at an obtuse angle, and the first external electrode and the second external electrode are connected to each other through the through hole. Formed between the two first semiconductor chips electrically connected by the first conductive pattern formed via the inner wall and the inclined surface of the third surface except for the element formation region on the third surface. A second semiconductor chip is provided in which the third external electrode and the fourth external electrode formed on a portion of the fourth surface other than the element formation region are electrically connected by a second conductive pattern. And the first semiconductor chip and the second semiconductor chip are directly Wherein a that are electrically connected via a connecting member. A multi-chip type semiconductor device in which a plurality of semiconductor chips each including a semiconductor substrate on which an element is integrally formed are stacked, wherein the stacked semiconductor chips face the surface in parallel with the surface. A first external electrode formed of a semiconductor substrate having a back surface, a slope formed at an acute angle with the front surface, and a concave portion formed around the front surface, and a first external electrode formed on the front surface; A second external electrode formed on the semiconductor substrate, and a conductive pattern formed in the recess and on the side surface for connecting the first external electrode and the second external electrode, and the semiconductor A semiconductor device, wherein a chip is electrically connected to another semiconductor chip via the first external electrode and the second external electrode. 14. The semiconductor device according to claim 13, wherein the stacked semiconductor chips are electrically connected to the semiconductor chips immediately above and below the semiconductor chips directly or via a connection member.

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