JP4282514B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a chip size package type semiconductor device and a manufacturing method thereof.

  In recent years, a chip size package (CSP) has attracted attention as a three-dimensional mounting technique and as a new packaging technique. The chip size package refers to a small package having an outer dimension substantially the same as the outer dimension of a semiconductor chip.

  Conventionally, a BGA type semiconductor device is known as a kind of chip size package. In this BGA type semiconductor device, a plurality of ball-shaped conductive terminals made of a metal member such as solder are arranged in a lattice pattern on one main surface of a package, and electrically connected to a semiconductor chip mounted on the other surface of the package. Is connected to.

  When incorporating this BGA type semiconductor device into an electronic device, each conductive terminal is crimped to a wiring pattern on the printed circuit board, thereby electrically connecting the semiconductor chip and the external circuit mounted on the printed circuit board. Connected.

  Such a BGA type semiconductor device is provided with a larger number of conductive terminals than other CSP type semiconductor devices such as SOP (Small Outline Package) and QFP (Quad Flat Package) having lead pins protruding from the side. It has the advantage that it can be reduced in size. This BGA type semiconductor device has an application as an image sensor chip of a digital camera mounted on a mobile phone, for example.

  FIG. 10 shows a schematic configuration of a conventional BGA type semiconductor device, and FIG. 10A is a perspective view of the surface side of this BGA type semiconductor device. FIG. 10B is a perspective view of the back side of the BGA type semiconductor device.

  In this BGA type semiconductor device 101, a semiconductor chip 104 is sealed between first and second glass substrates 102 and 103 via epoxy resins 105a and 105b. A plurality of conductive terminals 106 are arranged in a grid pattern on one main surface of the second glass substrate 103, that is, on the back surface of the BGA type semiconductor device 101. The conductive terminal 106 is connected to the semiconductor chip 104 via the second wiring 110. The plurality of second wirings 110 are connected to the first wirings drawn from the inside of the semiconductor chip 104, respectively, and each conductive terminal 106 and the semiconductor chip 104 are electrically connected.

  A cross-sectional structure of the BGA type semiconductor device 101 will be described in more detail with reference to FIG. FIG. 11 shows a cross-sectional view of a BGA type semiconductor device 101 divided into individual chips along a dicing line.

  A first wiring 107 is provided on the insulating film 108 disposed on the surface of the semiconductor chip 104. The semiconductor chip 104 is bonded to the first glass substrate 102 by a resin layer 105a. The back surface of the semiconductor chip 104 is bonded to the second glass substrate 103 with a resin layer 105b.

  One end of the first wiring 107 is connected to the second wiring 110. The second wiring 110 extends from one end of the first wiring 107 to the surface of the second glass substrate 103. A ball-shaped conductive terminal 106 is formed on the second wiring 110 extending on the second glass substrate 103.

The above-described technique is described in Patent Document 1 below, for example.
Japanese translation of PCT publication No. 2002-512436

  However, in the above-described BGA type semiconductor device 101, since the contact area between the first wiring 107 and the second wiring 110 is very small, there is a risk of disconnection at this contact portion. There was also a problem with the step coverage of the second wiring 110.

  Further, since the strength of the second wiring 110 is not sufficient, the second wiring 110 is distorted due to shear stress (force applied from the horizontal direction) or impact generated when the semiconductor device as a main body is mounted on a printed circuit board. As a result, problems such as deformation, breakage, or movement of the second wiring 110 have occurred. As a result, the reliability of the semiconductor device has been reduced.

  Therefore, the present invention aims to improve reliability in a chip size package type semiconductor device and a method for manufacturing the same.

The method for manufacturing a semiconductor device of the present invention is made in view of the above problems, and a step of preparing a semiconductor substrate on which a pad electrode is formed and bonding a support to a first main surface of the semiconductor substrate; A step of forming a via hole reaching the pad electrode from the second main surface of the semiconductor substrate, a step of forming a groove having a predetermined depth in the second main surface of the semiconductor chip, Forming a wiring layer electrically connected to the pad electrode through the groove and extending from the via hole and the groove onto the second main surface of the semiconductor substrate .

  The semiconductor device manufacturing method of the present invention is characterized in that, in the above manufacturing method, the groove is formed to be connected to the via hole.

  The semiconductor device manufacturing method of the present invention is characterized in that, in the manufacturing method, the groove is formed such that the predetermined depth is smaller than the film thickness of the wiring layer.

  In addition, the semiconductor device manufacturing method of the present invention is characterized in that, in the above manufacturing method, the wiring layer is formed such that both side ends of the wiring layer in the groove are in contact with the side wall of the groove.

  According to the present invention, since the wiring layer from the pad electrode of the semiconductor chip to the conductive terminal is formed through the via hole, disconnection of the wiring layer and deterioration of step coverage can be prevented.

  Furthermore, since the wiring layer is formed in a groove provided on the second main surface, that is, the back surface of the semiconductor chip, the wiring layer is fixed by the side wall portion of the groove. As a result, the strength of the wiring layer 63 is improved, and shear stress (force applied from the horizontal direction) generated when the semiconductor device is mounted on a printed circuit board or distortion of the wiring layer due to impact (deformation or movement of the wiring layer, etc.) The durability against is improved.

  Further, since the wiring layer in the groove is in contact with the side wall portion of the groove, heat generated during the operation of the semiconductor device is transferred from the wiring layer to the semiconductor chip and radiated in the side wall portion of the groove.

  As a result, a highly reliable chip size package type semiconductor device can be obtained.

  Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to the drawings. The semiconductor device manufacturing method according to the present embodiment is performed, for example, as follows. 1 to 9 show a cross section of a silicon wafer 51 which is a semiconductor substrate, and shows a cross section of a boundary between adjacent chips (ie, in the vicinity of the dicing line region DL) to be divided in a dicing process described later. 1 to 9, it is assumed that a device (not shown) (for example, a CCD image sensor) is formed on the first main surface, that is, the surface of the silicon wafer 51. The silicon wafer 51 may be a semiconductor substrate made of other materials such as GaAs, Ge, Si—Ge.

First, as shown in FIG. 1, an interlayer insulating film 5 such as BPSG is formed on the surface of the silicon wafer 51.
A pair of pad electrodes 53 are formed via 2. The pair of pad electrodes 53 is made of a metal layer such as aluminum, an aluminum alloy, or copper, and has a thickness of about 1 μm. Further, the pair of pad electrodes 53 is extended to the dicing line region DL, and the extended end portion is disposed before the dicing line center DS of the dicing line region DL.

  Then, a passivation film (not shown) made of a silicon nitride film or the like is formed so as to cover the pair of pad electrodes 53, and a resin layer 55 made of, for example, an epoxy resin is applied on the passivation film.

  A support 56 is bonded to the surface of the silicon wafer 51 through the resin layer 55. The support 56 supports the silicon wafer 51 and has a function of protecting the silicon wafer 51.

  When the silicon chip 51A is a CCD image sensor chip, it is necessary to receive light from the outside with a CCD device on the surface of the silicon chip 51A. Therefore, the support 56 is a transparent substrate such as a glass substrate, or It is necessary to use a translucent substrate. In the case where the silicon chip 51A does not receive or emit light, not only the glass substrate but also an opaque substrate may be used. For example, a substrate made of a metal or an organic material or a tape may be used.

  Then, with this support 56 adhered, backside etching of the silicon wafer 51, so-called back grinding, is performed as necessary, and the thickness is processed to about 150 μm, for example.

Thereafter, the silicon wafer 51 is etched by about 20 μm using an acid (for example, a mixed solution of HF and nitric acid) as an etchant. Thereby, the mechanical damage layer of the silicon wafer 51 generated by the back grinding is removed, and the characteristics of the device formed on the surface of the silicon wafer 51 are improved. In this embodiment, the final thickness of the silicon wafer 51 is about 130 μm, but this can be selected as appropriate according to the type of device. Next, as shown in FIG. A first photoresist layer 58 is selectively formed thereon. That is, the first photoresist layer 58 is formed with an opening at a position corresponding to the pad electrode 53. Using the first photoresist layer 58 as a mask, the silicon wafer 51 is etched. By this etching, a via hole 81 penetrating the silicon wafer 51 is formed. Here, the interlayer insulating film 52 is exposed at the bottom of the via hole 81, and the pad electrode 53 is in contact therewith.

  The etching method for forming the via hole 81 includes a method of etching using a laser beam and a method of using dry etching. The cross-sectional shape of the via hole 81 may be processed into a forward tapered shape in order to improve the coverage of a seed layer described later.

  Next, after removing the first photoresist layer 58, a second photoresist layer 59 is selectively formed on the back surface of the silicon wafer 51 as shown in FIG. That is, the second photoresist layer 59 is formed with an opening in a partial region on the back surface of the silicon wafer 51 including the region where the via hole 81 is formed. The silicon wafer 51 is etched using the second photoresist layer 59 as a mask. By this etching, a groove 82 having a predetermined depth is formed in a partial region on the back surface of the silicon wafer 51 including the region where the via hole 81 is formed. Further, by this etching, the interlayer insulating film 52 at the bottom of the via hole 81 is removed, and a part of the pad electrode 53 is exposed at the bottom.

  The groove 82 is preferably connected to the via hole 81. For example, the groove 82 has a predetermined depth such that the bottom of the groove 82 is located closer to the back surface of the silicon wafer 51 than the surface of the silicon wafer 51 (the main surface on the side where the pad electrode 53 is formed). Have. This predetermined depth is preferably smaller than the film thickness of the wiring layer 63 described later.

Next, after removing the second photoresist layer 59, as shown in FIG. 4, an insulating film 57 is formed on the entire back surface of the silicon wafer 51 including the inside of the via hole 81 and the inside of the groove 82 by the above process. The insulating film 57 is formed by, for example, a plasma CVD method, and a PE-SiO ₂ film or a PE-SiN film is suitable. Here, the bottom of the via hole 81 exists away from the back surface of the silicon wafer 51 and the bottom of the groove 82. Therefore, the insulating film 57 on the back surface of the silicon wafer 51 and in the groove 82 is formed thicker than the insulating film 57 located at the bottom of the via hole 81.

  Next, as shown in FIG. 5, anisotropic dry etching is performed without using a photoresist layer. Thereby, the insulating film 57 located at the bottom of the via hole 81 is removed. At the bottom of the via hole 81, the pad electrode 53 is exposed.

  On the other hand, the insulating film 57 on the side wall portion of the via hole 81 and the side wall portion of the groove 82 remains without being removed. Further, the insulating film 57 on the back surface of the silicon wafer 51 and at the bottom of the trench 82 is formed thicker than the insulating film 57 at the bottom of the via hole 81, and thus remains without being completely removed.

  Alternatively, the insulating film 57 located at the bottom of the via hole 81 may be removed by anisotropic dry etching using a resist layer (not shown). In this case, a resist layer (not shown) is formed on the insulating film 57 including the inside of the trench 82 so as to open only the formation region of the via hole 81. Then, after the dry etching is finished, the photoresist layer (not shown) is removed.

  Next, a process for forming the wiring layer 63 will be described. First, as shown in FIG. 6, a third photoresist layer 62 is selectively formed on a partial region of the insulating film 57. This region is a region excluding a region where a wiring layer 63 and a solder ball 66 described later are formed.

  Next, a seed layer (not shown) is formed on the back surface of the silicon wafer 51 including the inside of the via hole 81 and the inside of the groove 82 by any method such as sputtering, MOCVD, or electroless plating. A seed layer (not shown) is formed so as to be electrically connected to the pad electrode 53 exposed at the bottom of the via hole 81 and to cover the insulating film 57.

  The seed layer (not shown) is, for example, a copper (Cu) layer, a barrier metal layer such as a titanium tungsten (TiW) layer, a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, or a copper (Cu) layer. It consists of a laminated structure with a barrier metal layer.

  Here, in the via hole 81, a barrier metal layer constituting a seed layer (not shown) prevents copper (Cu) from diffusing into the silicon wafer 51 through the insulating film 57. However, when the insulating film 57 is formed of a silicon nitride film (SiN film), since the silicon nitride film (SiN film) serves as a barrier against copper diffusion, there is no problem even if the seed layer is only copper (Cu).

  This seed layer (not shown) serves as a plating electrode for plating growth during later-described electrolytic plating. Its thickness may be about 1 μm. When the via hole 81 is processed to have a forward taper, a sputtering method can be used to form the seed layer.

  Next, electrolytic plating of copper (Cu) is performed on a seed layer (not shown). That is, the wiring layer 63 is formed by performing electrolytic plating of copper (Cu). The wiring layer 63 is formed to extend from the inside of the via hole 81 and the groove 82 to the back surface of the silicon wafer 51 and is electrically connected to the pad electrode 53 through a seed layer (not shown).

  Here, the wiring layer 63 in the groove 82 is preferably formed so as to cover the groove 82 and to have a film thickness thicker than the depth of the groove 82. The ratio between the depth of the groove 82 and the thickness of the wiring layer 63 in the groove 82 is preferably about 2 to 3. Alternatively, the wiring layer 63 is not limited to the above ratio, and may be formed with a film thickness that is thicker than the depth of the groove 82. For example, when improving the throughput when forming the groove 82, the thickness of the wiring layer 63 may be about 5 to 15 μm, and the depth of the groove 82 may be about 1 to 2 μm.

  In addition, the wiring layer 63 in the groove 82 is preferably formed so that both end portions of the wiring layer 63 are in contact with the side wall portion of the groove 82. At least one side end portion of the wiring layer 63 in the groove 82 is formed in contact with one side wall portion of the groove 82.

  Generally, a wiring layer formed extending from a via hole to the back surface of a silicon wafer is distorted by shearing stress (force applied from the horizontal direction) or impact generated when a semiconductor device is mounted on a printed circuit board due to its metallic characteristics. As a result, the wiring layer may be deformed, damaged or moved. That is, the strength of the wiring layer was not sufficient. On the other hand, in the present embodiment, the wiring layer 63 is formed not only in the via hole 81 but also in the groove 82, so that the wiring layer 63 is fixed by the side wall portion of the groove 82. As a result, the strength of the wiring layer 63 against the above-described shear stress and impact is improved, and deformation, breakage, or movement of the wiring layer 63 can be suppressed as much as possible.

  In addition, since the wiring layer 63 in the groove 82 is in contact with the side wall portion of the groove 82, heat generated during the operation of the semiconductor device is generated on the side wall portion of the groove 82 from the wiring layer 63 after the silicon wafer 51 (after being divided). The heat is transmitted to the silicon chip 51A).

  Note that a desired number of wiring layers 63 can be formed in a desired region on the back surface of the silicon wafer 51.

  In FIG. 6, the wiring layer 63 is formed in the via hole 81 and the groove 82 by electrolytic plating of copper (Cu). However, the present invention is not limited thereto, and after tin (Sn) is formed by plating, Further, it may be formed by performing copper (Cu) plating.

  Further, the wiring layer 63 may be formed by a method other than plating. For example, the wiring layer 63 may be formed by depositing copper (Cu) in the via hole 81 and the groove 82 by the CVD method or the MOCVD method. The wiring layer 63 may be formed by sputtering with a metal such as aluminum (Al).

  In FIG. 6, after the third photoresist layer 62 is formed in a partial region on the back side of the silicon wafer 51, the wiring layer 63 is formed using this as a mask. However, the present invention is not limited to this. Instead, the wiring layer 63 may be formed as follows, for example. That is, although not shown, after a metal layer for the wiring layer 63 is formed on the entire back surface of the silicon wafer 51 including the via hole 81 and the groove 82, a photoresist layer is formed on the metal layer, and the photoresist layer is masked. The wiring layer 63 may be formed by patterning.

  Next, after removing the third photoresist layer 62, a barrier layer 64 made of, for example, nickel (Ni) and gold (Au) is formed on the wiring layer 63 as shown in FIG. Here, the barrier layer 64 is formed by, for example, electroless plating of nickel (Ni) and gold (Au) or sputtering.

  Next, as shown in FIG. 8, a solder mask 65 as a protective layer is formed on the back surface of the silicon wafer 51 including the wiring layer 63 and the barrier layer 64 so as to cover the wiring layer 63. Then, a part of the solder mask 65 corresponding to the formation position of the wiring layer 63 is selectively removed by, for example, etching, and an opening K that exposes the wiring layer 63 is provided in the part.

  Further, solder balls 66 are formed by printing solder on a predetermined region of the wiring layer 63, that is, on the wiring layer 63 exposed at the opening K, by using a screen printing method, and reflowing the solder by heat treatment. . The solder ball 66 is not limited to solder, and may be formed using a lead-free low melting point metal material. Further, by appropriately selecting the number of openings K and formation regions, the solder balls 66 can be formed by freely selecting the number and formation regions. Instead of forming the solder balls 66 by solder, conductive terminals (provided at the locations where the solder balls 66 are formed) may be formed by plating.

  Then, as shown in FIG. 9, a dicing process is performed along the dicing line center DS of the dicing line region DL to divide the silicon wafer 51 into a plurality of silicon chips 51A. In this dicing process, cutting is performed using a dicing blade. Thus, the semiconductor device according to this embodiment is completed.

  As described above, in this embodiment, the wiring layer 63 from the pad electrode 53 to the solder ball 66 formed on the back surface of the silicon chip 51A is wired through the via hole 81 and the groove 82. Step coverage is also excellent. Furthermore, by forming the wiring layer 63 in the groove 82, the strength of the wiring layer 63 against shear stress (force applied from the horizontal direction) and impact is improved, and the heat dissipation of the semiconductor device is improved. As a result, a highly reliable chip size package type semiconductor device can be obtained.

  In the above-described embodiment, the groove 82 is connected to the via hole 81, but the present invention is not limited to this. That is, the groove 82 and the via hole may be formed at positions separated from each other. In this case, the wiring layer 63 is formed on the back surface of the silicon wafer 51 so as to cover both the groove 82 and the via hole 81.

  Further, in the above-described embodiment, the pad electrode 53 formed by extending the pad electrode used for normal wire bonding to the dicing line region DL is formed. Alternatively, a pad electrode used for normal wire bonding that is not extended to the dicing line region DL may be used as it is. In this case, the formation position of the via hole 81 may be aligned with this pad electrode, and the other steps are exactly the same.

  Further, the present invention described above is applied to the BGA type semiconductor device in which the solder ball 66 is formed and the manufacturing method thereof, but the present invention is not limited to this. That is, the present invention is also applicable to a semiconductor device in which solder balls are not formed and a method for manufacturing the same as long as it has a wiring layer formed in a via hole penetrating a silicon wafer. For example, the present invention is also applied to an LGA (Land Grid Array) type semiconductor device and a manufacturing method thereof.

It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the semiconductor device which concerns on embodiment of this invention, and its manufacturing method. It is a figure explaining the conventional semiconductor device. It is a figure explaining the conventional semiconductor device.

Claims (6)

Preparing a semiconductor substrate on which a pad electrode is formed, and bonding a support to the first main surface of the semiconductor substrate;
Forming a via hole reaching the pad electrode from the second main surface of the semiconductor substrate;
Forming a groove having a predetermined depth in the second main surface of the semiconductor chip;
Forming a wiring layer electrically connected to the pad electrode through the via hole and the groove and extending on the second main surface of the semiconductor substrate from the via hole and the groove. A method for manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the groove is formed so as to be connected to the via hole. The method of manufacturing a semiconductor device according to claim 1, wherein the groove is formed so that the predetermined depth is smaller than a film thickness of the wiring layer. 4. The wiring layer according to claim 1, wherein the wiring layer is formed such that both side end portions of the wiring layer in the groove are in contact with a side wall portion of the groove. 5. A method for manufacturing a semiconductor device. Before the step of forming the wiring layer,
Forming an insulating film over the entire second main surface of the semiconductor substrate including the via hole and the trench;
The method of manufacturing a semiconductor device according to claim 1, further comprising: etching a bottom portion of the via hole to expose a part of the pad electrode. After the step of forming the wiring layer,
Forming a protective layer covering the wiring layer;
Forming an opening exposing a part of the wiring layer in a part of the protective layer, and forming a conductive terminal on the wiring layer exposed in the opening;
6. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of dividing the semiconductor substrate into a plurality of semiconductor chips.

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