JP2005260080A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability in a semiconductor device in a chip size package-type and in a manufacturing method of the device. <P>SOLUTION: A glass substrate 56 is bonded to a surface of a silicon wafer 51 where pad electrodes 53 are formed. Via holes VH reaching the pad electrodes 53 from a backside of the silicon wafer 51 are formed. Buffer layers 60 are formed and wiring layers 63 which extend to the backside of the silicon wafer 51 from the via holes VH and are connected to the pad electrodes 53 are formed. Reinforcement layers 64 are formed on the wiring layers 63 so that they are covered. Solder masks 65 are formed on the reinforcement layers 64, and openings K are arranged in a part of the reinforcement layers 54 and the solder masks 65. Solder balls 66 are formed in the openings K. The silicon wafer 51 supported by the glass substrate 56 is divided into individual silicon chips 51A by dicing. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a chip size package type semiconductor device and a manufacturing method thereof.

  In recent years, CSP (Chip Size Package) has attracted attention as a three-dimensional mounting technique and a new packaging technique. The CSP refers to a small package having an outer dimension substantially the same as the outer dimension of a semiconductor chip.

  Conventionally, a BGA type semiconductor device is known as a kind of CSP. In this BGA type semiconductor device, a plurality of ball-shaped conductive terminals made of a metal member such as solder are arranged in a lattice pattern on one main surface of a package, and electrically connected to a semiconductor chip mounted on the other surface of the package. Is connected to.

  When incorporating this BGA type semiconductor device into an electronic device, each conductive terminal is crimped to a wiring pattern on the printed circuit board, thereby electrically connecting the semiconductor chip and the external circuit mounted on the printed circuit board. Connected.

  Such a BGA type semiconductor device is provided with a larger number of conductive terminals than other CSP type semiconductor devices such as SOP (Small Outline Package) and QFP (Quad Flat Package) having lead pins protruding from the side. It has the advantage that it can be reduced in size. This BGA type semiconductor device has an application as an image sensor chip of a digital camera mounted on a mobile phone, for example.

  FIG. 13 shows a schematic configuration of a conventional BGA type semiconductor device, and FIG. 13A is a perspective view of the surface side of the BGA type semiconductor device. FIG. 13B is a perspective view of the back side of the BGA type semiconductor device.

  In this BGA type semiconductor device 101, a semiconductor chip 104 is sealed between first and second glass substrates 102 and 103 via epoxy resins 105a and 105b. A plurality of conductive terminals 106 are arranged in a grid pattern on one main surface of the second glass substrate 103, that is, on the back surface of the BGA type semiconductor device 101. The conductive terminal 106 is connected to the semiconductor chip 104 via the second wiring 110. The plurality of second wirings 110 are connected to the first wirings drawn from the inside of the semiconductor chip 104, respectively, and each conductive terminal 106 and the semiconductor chip 104 are electrically connected.

  A cross-sectional structure of the BGA type semiconductor device 101 will be described in more detail with reference to FIG. FIG. 14 shows a cross-sectional view of the BGA type semiconductor device 101 divided into individual chips along the dicing line.

  A first wiring 107 is provided on the insulating film 108 disposed on the surface of the semiconductor chip 104. The semiconductor chip 104 is bonded to the first glass substrate 102 by a resin layer 105a. Further, the back surface of the semiconductor chip 104 is bonded to the second glass substrate 103 by a resin layer 105b.

  One end of the first wiring 107 is connected to the second wiring 110. The second wiring 110 extends from one end of the first wiring 107 to the surface of the second glass substrate 103. A ball-shaped conductive terminal 106 is formed on the second wiring 110 extending on the second glass substrate 103.

The above-described technique is described in Patent Document 1 below, for example.
JP-T-2002-512436

  However, in the above-described BGA type semiconductor device 101, since the contact area between the first wiring 107 and the second wiring 110 is very small, there is a risk of disconnection at this contact portion. There was also a problem with the step coverage of the second wiring 110.

  In addition, since the strength of the second wiring 110 is not sufficient, the second wiring 110 is distorted by shearing stress (force applied in the horizontal direction) or impact generated when the semiconductor device as a main body is mounted on a printed circuit board. As a result, problems such as deformation, breakage, or movement of the second wiring 110 have occurred. As a result, the reliability of the semiconductor device has been reduced.

  Therefore, the present invention aims to improve reliability in a chip size package type semiconductor device and a method for manufacturing the same.

  The semiconductor device of the present invention has been made in view of the above problems, and a pad electrode formed on the first main surface of the semiconductor chip and a support bonded to the first main surface of the semiconductor chip. A via hole penetrating from the second main surface of the semiconductor chip to the surface of the pad electrode; a wiring layer electrically connected to the pad electrode through the via hole and extending from the via hole onto the second main surface of the semiconductor chip; And a reinforcing layer (for example, made of a silicon oxide film or a silicon nitride film) that is formed so as to cover the wiring layer and reinforces the wiring layer.

  Further, the semiconductor device of the present invention, in addition to the above configuration, an insulating film formed from the second main surface of the semiconductor chip to the sidewall of the via hole, a protective layer formed so as to cover the reinforcing layer, An opening that opens a part of the reinforcing layer and the protective layer, and a conductive terminal formed on the wiring layer exposed at the opening, the wiring layer is electrically connected to the pad electrode through the via hole, And extending from the via hole onto the second main surface of the semiconductor chip including the insulating film.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: preparing a semiconductor substrate on which a pad electrode is formed; and bonding a support to the first main surface of the semiconductor substrate; Forming a via hole reaching the surface of the pad electrode; forming a wiring layer electrically connected to the pad electrode through the via hole and extending from the via hole onto the second main surface of the semiconductor substrate; and on the wiring layer Forming a reinforcing layer (for example, made of a silicon oxide film or a silicon nitride film) for reinforcing the wiring layer so as to cover the wiring layer.

  In addition to the above steps, the method for manufacturing a semiconductor device of the present invention may include attaching a support to the first main surface of the semiconductor substrate, and then forming a first insulating film on the second main surface of the semiconductor substrate. Forming a via hole, forming a second insulating film over the entire second main surface of the semiconductor substrate including the inside of the via hole, and anisotropically etching the second insulating film to form the via hole. Removing the second insulating film located at the bottom of the substrate, forming a sidewall insulating film on the sidewall of the via hole, and forming a wiring layer and a reinforcing layer, and then forming a protective layer so as to cover the reinforcing layer A step of etching a part of the reinforcing layer and the protective layer to form an opening exposing a part of the wiring layer, a step of forming a conductive terminal on the wiring layer exposed in the opening, and a semiconductor Dividing the substrate into a plurality of semiconductor chips. To.

  Alternatively, in the semiconductor device manufacturing method of the present invention, in addition to the above steps, a step of forming an insulating film on the entire second main surface of the semiconductor substrate including the inside of the via hole after forming the via hole; The insulating film located at the bottom of the via hole is removed by anisotropic etching to form a sidewall insulating film on the side wall of the via hole, and the wiring layer and the reinforcing layer are formed, and then the reinforcing layer is covered. Forming a protective layer, etching a part of the reinforcing layer and the protective layer to form an opening exposing a part of the wiring layer, and a conductive terminal on the wiring layer exposed in the opening And a step of dividing the semiconductor substrate into a plurality of semiconductor chips.

  According to the present invention, since the wiring layer from the pad electrode of the semiconductor chip to the conductive terminal is formed via the via hole, disconnection of the wiring layer and deterioration of the step coverage can be prevented. Further, since the wiring layer is covered with a reinforcing layer that reinforces its strength, the wiring layer is distorted due to shear stress (force applied in the horizontal direction) or impact generated when the semiconductor device is mounted on a printed circuit board ( It is possible to improve durability against deformation or movement of the wiring layer and corrosion of the wiring layer. Further, when the wiring layer 63 is made of copper, it is possible to suppress so-called copper contamination as much as possible.

  In addition, the protective layer protects the semiconductor chip by covering only the reinforcing layer without covering a plurality of different layers (wiring layers and insulating films). Thereby, the adhesiveness with respect to the semiconductor chip of a protective layer improves.

  In addition, since the conductive terminal is formed on the buffer layer, the impact at the time of mounting on the printed circuit board is mitigated, and damage to the semiconductor device can be prevented. Further, the conductive terminal is formed at a position higher than the second main surface of the semiconductor chip by the thickness of the buffer layer. Thereby, the stress generated when the semiconductor device is mounted on the printed board is easily absorbed, and damage to the conductive terminals can be prevented as much as possible.

  As a result, a highly reliable chip size package type semiconductor device can be obtained.

  Next, the present embodiment will be described in detail with reference to the drawings. First, the structure of this semiconductor device will be described. FIG. 12 is a cross-sectional view of this semiconductor device, which shows a semiconductor substrate that has undergone the steps described later, that is, a silicon wafer 51 divided into individual semiconductor chips along the dicing line center DS of the dicing line region DL.

  The silicon chip 51A, which is a semiconductor chip, is, for example, a CCD (Charge Coupled Device) image sensor chip, and a pad electrode 53 is formed on the surface of the first main surface via an interlayer insulating film 52 such as BPSG. ing. The pad electrode 53 is obtained by extending a pad electrode used for normal wire bonding to the dicing line region DL, and is also called an extended pad electrode.

  The pad electrode 53 is covered with a passivation film 54 such as a silicon nitride film. A glass substrate 56 as a support is bonded to the surface of the silicon chip 51A on which the pad electrode 53 is formed via a resin layer 55 made of, for example, an epoxy resin. The glass substrate 56 as a support has a function of supporting the silicon chip 51A and protecting the silicon chip 51A.

  When the silicon chip 51A is a CCD image sensor chip, it is necessary to receive light from the outside with a CCD device on the surface of the silicon chip 51A, so a transparent substrate such as a glass substrate 56 or a translucent substrate is used. There is a need. In the case where the silicon chip 51A does not receive or emit light, not only the glass substrate but also an opaque substrate may be used. For example, a substrate made of a metal or an organic material or a tape may be used.

  A via hole VH reaching the pad electrode 53 is formed from the back surface which is the second main surface of the silicon chip 51A. A sidewall insulating film 59A is formed on the sidewall of the via hole VH. The side wall insulating film 59A electrically insulates a wiring layer 63 described later and the silicon chip 51A.

  A buffer layer 60 is formed on the back surface of the silicon chip 51A in the region adjacent to the via hole VH via the first insulating film 57 and the second insulating film 59. Note that the first insulating film 57 is not necessarily formed, and similarly, the omission of the buffer layer 60 is not limited.

  A wiring layer 63 (also referred to as a rewiring layer) that is electrically connected to the pad electrode 53 through the via hole VH and extends from the via hole VH onto the back surface of the silicon chip 51A is formed. The wiring layer 63 extends on the back surface of the silicon chip 51 </ b> A so as to cover the buffer layer 60. A seed layer 61 is provided below the wiring layer 63. This is a metal layer that serves as a plating electrode used when the wiring layer 63 is formed by electrolytic plating. The seed layer 61 and the wiring layer 63 are made of, for example, copper (Cu).

In general, the wiring layer 63 as described above is distorted by shearing stress (force applied in the horizontal direction) or impact generated when a semiconductor device is mounted on a printed circuit board due to its metallic characteristics. There is a risk of deformation, damage or movement. That is, the strength of the wiring layer 63 was not sufficient. Therefore, in the present embodiment, the reinforcing layer 64 for reinforcing the strength of the wiring layer 63 is formed on the wiring layer 63 and the first insulating film 57 so as to cover the wiring layer 63. As a result, the strength of the wiring layer 63 against the above-described shear stress and impact is improved, and deformation, breakage, or movement of the wiring layer 63 can be suppressed as much as possible. Further, the occurrence of damage such as corrosion in the wiring layer 63 can be suppressed. Further, when the wiring layer 63 is made of copper (Cu), it is possible to suppress as much as possible the so-called copper contamination caused by this. The reinforcing layer 64 is preferably made of, for example, a silicon oxide film (SiO ₂ film) or a silicon nitride film (SiN film).

  Further, the reinforcing layer 64 is covered with a solder mask 65 which is a protective layer. In the reinforcing layer 64 and the solder mask 65, an opening K is formed in a portion on the buffer layer 60. A solder ball 66 as a conductive terminal is mounted through the opening K of the solder mask 65. Thereby, the solder ball 66 and the wiring layer 63 are electrically connected. A BGA structure can be obtained by forming a plurality of such solder balls 66.

  Thus, wiring from the pad electrode 53 of the silicon chip 51A to the solder ball 66 formed on the back surface thereof is possible. Further, since the wiring is made through the via hole VH, disconnection hardly occurs and the step coverage is excellent. Furthermore, since the wiring layer 63 is covered with the reinforcing layer 64, the wiring layer 63 is corroded, and the wiring layer 63 is distorted due to stress or impact generated when the semiconductor device is mounted on the printed circuit board (deformation of the wiring layer 63). Durability against movement, etc.).

  Further, since the solder ball 66 is disposed on the buffer layer 60, when the semiconductor device is mounted on the printed circuit board via the solder ball 66, the buffer layer 60 acts as a kind of cushion, and the impact is reduced. The solder ball 66 and the semiconductor device as the main body are prevented from being damaged.

  Further, the solder ball 66 is formed at a position higher than the back surface of the silicon chip 51A by the thickness of the buffer layer 60. This prevents the solder ball 66 and the silicon chip 51A from being damaged by the stress and impact caused by the difference in thermal expansion coefficient between the printed board and the solder ball 66 when the semiconductor device is mounted on the printed board. .

  The buffer layer 60 can be made of various materials such as organic insulators, inorganic insulators, metals, silicon, and photoresists. However, in order to function as a cushion, the organic insulators and inorganic insulators that are rich in elasticity are used. Goods, photoresists, etc. are suitable.

  Further, the silicon chip 51A may be a semiconductor chip of another material such as GaAs, Ge, Si—Ge. The glass substrate 56 preferably has a thermal expansion coefficient Kg close to the thermal expansion coefficient Ks of the silicon chip 51A. The range of the thermal expansion coefficient Kg is within ± 30% of the thermal expansion coefficient Ks of Si (2.6 to 3.0 ppm / ° K). That is, if the thermal expansion coefficient Kg of the glass substrate and the thermal expansion coefficient Ks of the silicon chip 51A are set, a relationship of 0.7 Ks ≦ Kg ≦ 1.3 Ks is established.

  Thereby, the curvature of the glass substrate 56 due to the difference in thermal expansion coefficient between the glass substrate 56 and the silicon chip 51A is prevented as much as possible. The same can be said when the silicon chip 51A is a semiconductor chip of another material.

  Next, a method for manufacturing the semiconductor device according to the above-described embodiment will be described. The semiconductor device manufacturing method according to the present embodiment is performed, for example, as follows. 1 to 12 show a cross section of a silicon wafer 51 which is a semiconductor substrate, and shows a cross section of a boundary between adjacent chips (that is, near the dicing line region DL) to be divided in a dicing process described later. . 1 to 12, it is assumed that a semiconductor integrated circuit (for example, a CCD image sensor) (not shown) is formed on the first main surface, that is, the surface of the silicon wafer 51.

  First, as shown in FIG. 1, a pair of pad electrodes 53 is formed on the surface of a silicon wafer 51 via an interlayer insulating film 52 such as BPSG. The pair of pad electrodes 53 is made of a metal layer such as aluminum, an aluminum alloy, or copper, and has a thickness of about 1 μm. Further, the pair of pad electrodes 53 is extended to the dicing line region DL, and the extended end portion is disposed before the dicing line center DS of the dicing line region DL.

  Then, a passivation film 54 such as a silicon nitride film covering the pair of pad electrodes 53 is formed, and a resin layer 55 made of, for example, an epoxy resin is applied on the passivation film 54.

  Then, the glass substrate 56 is bonded to the surface of the silicon wafer 51 through the resin layer 55. The glass substrate 56 has a function of supporting and protecting the silicon wafer 51. The substrate is not limited to a glass substrate, and a substrate or a tape made of metal or organic material may be used.

  Then, with the glass substrate 56 bonded, if necessary, backside etching of the silicon wafer 51, so-called back grinding, is performed, and the thickness is processed to about 150 μm, for example.

  Thereafter, the silicon wafer 51 is etched by about 20 μm using an acid (for example, a mixed solution of HF and nitric acid) as an etchant. Thereby, the mechanical damage layer of the silicon wafer 51 generated by the back grinding is removed, and the characteristics of the device formed on the surface of the silicon wafer 51 are improved. In the present embodiment, the final thickness of the silicon wafer 51 is about 130 μm, but this can be appropriately selected according to the type of device.

Then, a first insulating film 57 is formed on the entire back surface of the silicon wafer 51 whose back surface has been cut by the above process. The first insulating film 57 is formed by, for example, a plasma CVD method, and a PE-SiO ₂ film or a PE-SiN film is suitable. Note that the formation of the first insulating film 57 may be omitted.

  Next, as shown in FIG. 2, a photoresist layer 58 is selectively formed on the first insulating film 57. That is, the photoresist layer 58 is formed with an opening at a position corresponding to the pad electrode 53. Using the photoresist layer 58 as a mask, the first insulating film 57 and the silicon wafer 51 are etched. By this etching, a via hole VH penetrating the silicon wafer 51 is formed. Here, the interlayer insulating film 52 is exposed at the bottom of the via hole VH, and the pad electrode 53 is in contact therewith.

  If the formation of the first insulating film 57 is omitted, the silicon wafer 51 is etched using the photoresist layer 58 directly formed on the silicon wafer 51 as a mask.

  As an etching method for forming the via hole VH, there are a method of etching using a laser beam and a method of using dry etching. The cross-sectional shape of the via hole VH may be processed into a forward tapered shape in order to improve the coverage of the seed layer 61 described later.

Next, as shown in FIG. 3, a second insulating film 59 is formed on the entire back surface of the silicon wafer 51 in which the via hole VH is formed. The second insulating film 59 is formed by, for example, a plasma CVD method, and a PE-SiO ₂ film or a PE-SiN film is suitable. The second insulating film 59 is formed on the bottom of the via hole VH, the side wall, and the first insulating film 57.

  When the formation of the first insulating film 57 is omitted, the second insulating film 59 is formed on the back surface of the silicon wafer 51 including the bottom and side walls of the via hole VH.

  Next, as shown in FIG. 4, a buffer layer 60 is formed on the second insulating film 59 adjacent to the via hole VH. The buffer layer 60 can be formed in a predetermined region by mask exposure and development processing using a film resist. The buffer layer 60 is not limited to this, and various materials such as an organic insulator, an inorganic insulator, a metal, silicon, and a photoresist can be used. However, in order to function as a cushion, an organic insulator rich in elasticity is used. Inorganic insulators and photoresists are suitable.

  Next, as shown in FIG. 5A, anisotropic dry etching is performed without using a photoresist layer. As a result, the second insulating film 59 remains only on the side wall of the via hole VH, and this becomes the side wall insulating film 59A. Further, the second insulating film 59 and the interlayer insulating film 52 located at the bottom of the via hole VH are removed by etching. The pad electrode 53 is exposed at the bottom of the via hole VH.

  As described above, in the present embodiment, after the formation of the via hole VH, the second insulating film 59 is formed in the via hole VH, and after the buffer layer 60 is formed, the second insulating film 59 positioned at the bottom of the via hole VH and The interlayer insulating film 52 is removed by etching, and the pad electrode 53 is exposed.

  On the contrary, it is possible to form the buffer layer 60 after etching the bottom of the via hole VH to expose the pad electrode 53, but in this case, when the buffer layer 60 is formed, the exposed via hole is exposed. There is a possibility that the bottom of the VH is contaminated and the electrical connection between the wiring layer 63 and the pad electrode 53 to be formed in the via hole VH later becomes poor. Therefore, as in the present embodiment, it is preferable to etch the bottom of the via hole VH after forming the via hole VH in order to obtain a good electrical connection between the wiring layer 63 and the pad electrode 53.

  Further, in the step of FIG. 5, after the buffer layer 60 is formed, the insulating film in the via hole VH is etched to form the side wall insulating film 59A. There is also an advantage that adhesion to the layer 61 is improved.

  When the formation of the first insulating film 57 is omitted, as shown in FIG. 5B, the first insulating film 57 is formed on the back surface of the silicon wafer 51 including the via hole VH without using the photoresist layer. Anisotropic etching is performed on the second insulating film 59a. As a result, the second insulating film 59a remains on the side wall of the via hole VH, and this becomes the side wall insulating film 59a. Further, since the second insulating film 59a formed on the back surface of the silicon wafer 51 is formed thicker than the second insulating film 59a located at the bottom of the via hole VH, the anisotropic etching is performed. After that, it remains as an insulating film. That is, only the second insulating film 59a located at the bottom of the via hole VH is removed.

Next, a process for forming the wiring layer 63 will be described. As shown in FIG. 6, the seed layer 61 is formed on the silicon wafer 5 by any method such as sputtering, MOCVD, or electroless plating.
1 is formed on the entire back surface of the silicon wafer 51 including the inside of the via hole VH. The seed layer 61 is, for example, a copper (Cu) layer, a barrier metal layer such as a titanium tungsten (TiW) layer, a titanium nitride (TiN) layer, or a tantalum nitride (TaN) layer, or a copper (Cu) layer and a barrier metal. It consists of a laminated structure with layers. Here, in the via hole VH, the seed layer 61 is formed so as to be electrically connected to the pad electrode 53 and cover the sidewall insulating film 59A.

  The seed layer 61 also covers the buffer layer 60. Here, the barrier metal layer constituting the seed layer 61 prevents copper (Cu) from diffusing into the silicon wafer 51 through the sidewall insulating film 59A. However, in the case where the sidewall insulating film 59A is formed of a silicon nitride film (SiN film), the silicon nitride film (SiN film) serves as a barrier against copper diffusion. Absent.

  This seed layer 61 becomes a plating electrode for plating growth at the time of electrolytic plating described later. Its thickness may be about 1 μm. When the via hole VH is processed to have a forward taper, the seed layer 61 can be formed by sputtering.

  Then, before the electroplating of copper (Cu) is performed on the seed layer 61, as shown in FIG. 7, a photoresist layer 62 is selectively formed in a region where the electroplating is not performed. This region is a region excluding the region where the wiring layer 63 and the solder ball 66 are formed.

  Next, as shown in FIG. 8, the wiring layer 63 is formed by performing electrolytic plating of copper (Cu). The wiring layer 63 is taken out from the via hole VH to the back surface of the silicon wafer 51 and extends on the back surface to cover the buffer layer 60. As a result, the wiring layer 63 is electrically connected to the pad electrode 53.

  Note that a desired number of wiring layers 63 can be formed in a desired region on the back surface of the silicon wafer 51.

  In FIG. 8, the wiring layer 63 is completely embedded in the via hole VH, but may be embedded incompletely by adjusting the plating time. The wiring layer 63 is formed so as to be embedded in the bihole VH by electrolytic plating of copper (Cu), but is not limited to this, and may be formed by other methods. For example, the wiring layer 63 may be formed by performing plating formation of copper (Cu) after plating formation of tin (Sn). Alternatively, the wiring layer 63 may be formed by a method of embedding a metal such as copper (Cu) in the via hole VH by a CVD method or an MOCVD method. The wiring layer 63 may be formed by sputtering using a metal such as aluminum (Al).

  Then, the photoresist layer 62 is removed, and the seed layer 61 remaining under the photoresist layer 62 is removed by etching using the wiring layer 63 as a mask. At this time, the wiring layer 63 is also etched, but there is no problem because the wiring layer 63 is thicker than the seed layer.

  7 and 8, the photoresist layer 62 is formed in a partial region on the back side of the silicon wafer 51, and then the wiring layer 63 is formed using this as a mask. However, the present invention is not limited to this. Instead, the wiring layer 63 may be formed as follows, for example. That is, although not shown, after a metal layer for the wiring layer 63 is formed on the entire back surface of the silicon wafer 51 including the via hole VH, a photoresist layer is formed on the metal layer, and patterning is performed using the photoresist layer as a mask. Thus, the wiring layer 63 may be formed.

Next, as shown in FIG. 9, a silicon oxide film (SiO ₂ film) or a silicon nitride film (SiN film) is formed on the wiring layer 63 and the first insulating film 57 so as to cover the wiring layer 63. A reinforcing layer 64 is formed. Further, as shown in FIG. 10, a solder mask 65 that is a protective layer is formed on the reinforcing layer 64. Then, a part of the solder mask 65 and the reinforcing layer 64 corresponding to the formation position of the buffer layer 60 is selectively removed, for example, by etching or the like, and an opening K that exposes the wiring layer 63 is provided at the part. .

  Next, as shown in FIG. 11, using a screen printing method, solder is printed on a predetermined region of the wiring layer 63, that is, on the wiring layer 63 exposed at the opening K, and the solder is reflowed by heat treatment. Thus, the solder ball 66 is formed. The solder ball 66 is not limited to solder, and may be formed using a lead-free low melting point metal material. Further, by appropriately selecting the number of openings K and formation regions, the solder balls 66 can be formed by freely selecting the number and formation regions. Instead of forming the solder balls 66 by solder, conductive terminals (provided at the locations where the solder balls 66 are formed) may be formed by plating.

  Then, as shown in FIG. 12, a dicing process is performed along the dicing line center DS of the dicing line region DL to divide the silicon wafer 51 into a plurality of silicon chips 51A. In this dicing process, cutting is performed using a dicing blade.

  As described above, in the present embodiment, the wiring layer 63 from the pad electrode 53 to the solder ball 66 formed on the back surface of the silicon chip 51A is wired through the via hole VH. It is hard to occur and has excellent step coverage.

  Further, since the wiring layer 63 is covered with the reinforcing layer 64, the strength of the wiring layer 63 is reinforced, and distortion of the wiring layer 63 (deformation of the wiring layer 63) when the semiconductor device as the main body is mounted on a printed circuit board. And the like are less likely to occur, and the wiring layer 63 is more resistant to corrosion. In addition, the so-called copper contamination caused by copper (Cu) in the wiring layer 63 can be suppressed as much as possible.

  Further, the solder mask 65 protects the silicon chip 51A by covering only the reinforcing layer 64 without covering a plurality of different layers (the wiring layer 63 and the first insulating film 57). Thereby, the adhesiveness with respect to the silicon chip 51A of the solder mask 65 improves.

  The solder ball 66 is formed at a position higher than the back surface of the silicon chip 51A by the thickness of the buffer layer 60. As a result, stress and impact generated when the semiconductor device is mounted on a printed circuit board are easily absorbed, and damage to the solder balls 66 can be prevented as much as possible. Further, since the solder ball 66 is formed on the buffer layer 60, the impact when mounting the semiconductor device on the printed circuit board is mitigated, and damage to the semiconductor device can be prevented.

  In the above-described embodiment, the pad electrode 53 formed by extending the pad electrode used for normal wire bonding to the dicing line region DL is formed. However, the present invention is not limited to this. Alternatively, a pad electrode used for normal wire bonding that is not extended to the dicing line region DL may be used as it is. In this case, the formation position of the via hole VH may be aligned with this pad electrode, and the other steps are exactly the same.

  Although the present invention is applied to the BGA type semiconductor device in which the solder ball 66 is formed and the manufacturing method thereof, the present invention is not limited to this. That is, the present invention is also applicable to a semiconductor device in which solder balls are not formed and a method for manufacturing the same as long as it has a wiring layer formed in a via hole penetrating a silicon wafer. For example, the present invention is also applied to an LGA (Land Grid Array) type semiconductor device and a manufacturing method thereof.

It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the semiconductor device which concerns on embodiment of this invention, and its manufacturing method. It is a figure explaining the conventional semiconductor device. It is a figure explaining the conventional semiconductor device.

Claims (7)

A pad electrode formed on the first main surface of the semiconductor chip;
A support bonded to the first main surface of the semiconductor chip;
A via hole penetrating from the second main surface of the semiconductor chip to the surface of the pad electrode;
A wiring layer electrically connected to the pad electrode through the via hole and extending from the via hole onto the second main surface of the semiconductor chip;
And a reinforcing layer formed to cover the wiring layer and reinforcing the wiring layer. An insulating film formed from the second main surface of the semiconductor chip to the sidewall of the via hole;
A protective layer formed so as to cover the reinforcing layer;
An opening for opening a part of the reinforcing layer and the protective layer;
A conductive terminal formed on the wiring layer exposed at the opening,
The wiring layer is electrically connected to the pad electrode through the via hole and extends from the via hole onto a second main surface of the semiconductor chip including on the insulating film. 1. The semiconductor device according to 1. 3. The semiconductor device according to claim 1, wherein the reinforcing layer is made of a silicon oxide film or a silicon nitride film. Prepare a semiconductor substrate on which pad electrodes are formed,
Adhering a support to the first main surface of the semiconductor substrate;
Forming a via hole reaching the surface of the pad electrode from the second main surface of the semiconductor substrate;
Forming a wiring layer electrically connected to the pad electrode through the via hole and extending from the via hole onto the second main surface of the semiconductor substrate;
Forming a reinforcing layer that reinforces the wiring layer so as to cover the wiring layer;
A method for manufacturing a semiconductor device, comprising: Forming a first insulating film on the second main surface of the semiconductor substrate after bonding a support to the first main surface of the semiconductor substrate;
Forming a second insulating film on the entire second main surface of the semiconductor substrate including the inside of the via hole after forming the via hole;
Anisotropically etching the second insulating film to remove the second insulating film located at the bottom of the via hole, and forming a sidewall insulating film on the sidewall of the via hole;
After forming the wiring layer and the reinforcing layer, forming a protective layer so as to cover the reinforcing layer;
Etching the reinforcing layer and part of the protective layer to form an opening exposing a part of the wiring layer;
Forming a conductive terminal on the wiring layer exposed at the opening;
The method for manufacturing a semiconductor device according to claim 4, further comprising: dividing the semiconductor substrate into a plurality of semiconductor chips. Forming an insulating film on the entire second main surface of the semiconductor substrate including the inside of the via hole after forming the via hole;
Anisotropically etching the insulating film, removing the insulating film located at the bottom of the via hole, and forming a sidewall insulating film on the side wall of the via hole;
After forming the wiring layer and the reinforcing layer, forming a protective layer so as to cover the reinforcing layer;
Etching the reinforcing layer and part of the protective layer to form an opening exposing a part of the wiring layer;
Forming a conductive terminal on the wiring layer exposed at the opening;
The method for manufacturing a semiconductor device according to claim 4, further comprising: dividing the semiconductor substrate into a plurality of semiconductor chips. The method of manufacturing a semiconductor device according to claim 4, wherein the reinforcing layer is made of a silicon oxide film or a silicon nitride film.

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