JP2005260079A5 - - Google Patents
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- JP2005260079A5 JP2005260079A5 JP2004071294A JP2004071294A JP2005260079A5 JP 2005260079 A5 JP2005260079 A5 JP 2005260079A5 JP 2004071294 A JP2004071294 A JP 2004071294A JP 2004071294 A JP2004071294 A JP 2004071294A JP 2005260079 A5 JP2005260079 A5 JP 2005260079A5
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- JP
- Japan
- Prior art keywords
- groove
- wiring layer
- main surface
- via hole
- pad electrode
- Prior art date
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Claims (14)
前記半導体チップの第１の主面に接着された支持体と、
前記半導体チップの第２の主面から前記パッド電極上に到達するビアホールと、
前記半導体チップの第２の主面に所定の深さを有して形成された溝と、
前記ビアホール内及び前記溝内に形成されて前記パッド電極と電気的に接続され、かつ前記ビアホール及び前記溝から前記半導体チップの第２の主面上に延びる配線層と、を有することを特徴とする半導体装置。 A pad electrode formed on the first main surface of the semiconductor chip;
A support bonded to the first main surface of the semiconductor chip;
A via hole reaching the pad electrode from the second main surface of the semiconductor chip;
A groove formed on the second main surface of the semiconductor chip with a predetermined depth;
A wiring layer formed in the via hole and in the groove and electrically connected to the pad electrode and extending from the via hole and the groove on the second main surface of the semiconductor chip. Semiconductor device.
前記半導体チップの第２の主面から前記パッド電極上に到達するビアホールと、A via hole reaching the pad electrode from the second main surface of the semiconductor chip;
前記半導体チップの第２の主面に所定の深さを有して形成された溝と、A groove formed on the second main surface of the semiconductor chip with a predetermined depth;
前記ビアホール内及び前記溝内に形成されて前記パッド電極と電気的に接続され、かつ前記ビアホール及び前記溝から前記半導体チップの第２の主面上に延びる配線層と、を有することを特徴とする半導体装置。A wiring layer formed in the via hole and in the groove and electrically connected to the pad electrode and extending from the via hole and the groove on the second main surface of the semiconductor chip. Semiconductor device.
前記配線層は、前記絶縁膜上に形成されていることを特徴とする請求項１、２、３、４、５のいずれか１項に記載の半導体装置。 An insulating film formed on the second main surface of the semiconductor chip including the via hole and the groove so as to expose a part of the pad electrode at the bottom of the via hole;
The semiconductor device according to claim 1, wherein the wiring layer is formed on the insulating film .
前記開口部で露出する前記配線層上に形成された導電端子と、を有することを特徴とする請求項１、２、３、４、５、６のいずれか１項に記載の半導体装置。The semiconductor device according to claim 1, further comprising: a conductive terminal formed on the wiring layer exposed at the opening.
前記半導体基板の第２の主面から前記パッド電極上に到達するビアホールを形成する工程と、Forming a via hole reaching the pad electrode from the second main surface of the semiconductor substrate;
前記半導体チップの第２の主面に、所定の深さを有した溝を形成する工程と、Forming a groove having a predetermined depth in the second main surface of the semiconductor chip;
前記ビアホール内及び前記溝内を通して前記パッド電極と電気的に接続され、かつ前記ビアホール及び前記溝から前記半導体基板の第２の主面上に延びる配線層を形成する工程と、を有することを特徴とする半導体装置の製造方法。Forming a wiring layer electrically connected to the pad electrode through the via hole and the groove and extending from the via hole and the groove onto the second main surface of the semiconductor substrate. A method for manufacturing a semiconductor device.
前記半導体基板の第２の主面から前記パッド電極上に到達するビアホールを形成する工程と、Forming a via hole reaching the pad electrode from the second main surface of the semiconductor substrate;
前記半導体チップの第２の主面に、所定の深さを有した溝を形成する工程と、Forming a groove having a predetermined depth in the second main surface of the semiconductor chip;
前記ビアホール内及び前記溝内を通して前記パッド電極と電気的に接続され、かつ前記ビアホール及び前記溝から前記半導体基板の第２の主面上に延びる配線層を形成する工程と、を有することを特徴とする半導体装置の製造方法。Forming a wiring layer electrically connected to the pad electrode through the via hole and the groove and extending from the via hole and the groove onto the second main surface of the semiconductor substrate. A method for manufacturing a semiconductor device.
前記ビアホール及び前記溝を含む前記半導体基板の第２の主面の全面に絶縁膜を形成する工程と、
前記ビアホールの底部をエッチングして、前記パッド電極の一部を露出する工程と、を有することを特徴とする請求項８、９、１０、１１、１２のいずれか１項に記載の半導体装置の製造方法。 Before the step of forming the wiring layer,
Forming an insulating film over the entire second main surface of the semiconductor substrate including the via hole and the groove;
13. The method according to claim 8, further comprising: etching a bottom portion of the via hole to expose a part of the pad electrode. 13 . Production method.
前記配線層を覆う保護層を形成する工程と、
前記保護層の一部に前記配線層の一部を露出する開口部を形成して、当該開口部で露出する前記配線層上に、導電端子を形成する工程と、
前記半導体基板を複数の半導体チップに分割する工程と、を有することを特徴とする請求項８、９、１０、１１、１２、１３のいずれか１項に記載の半導体装置の製造方法。 After the step of forming the wiring layer,
Forming a protective layer covering the wiring layer;
Forming an opening exposing a part of the wiring layer in a part of the protective layer, and forming a conductive terminal on the wiring layer exposed in the opening;
The method for manufacturing a semiconductor device according to claim 8, further comprising a step of dividing the semiconductor substrate into a plurality of semiconductor chips .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004071294A JP4282514B2 (en) | 2004-03-12 | 2004-03-12 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004071294A JP4282514B2 (en) | 2004-03-12 | 2004-03-12 | Manufacturing method of semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2005260079A JP2005260079A (en) | 2005-09-22 |
| JP2005260079A5 true JP2005260079A5 (en) | 2007-04-19 |
| JP4282514B2 JP4282514B2 (en) | 2009-06-24 |
Family
ID=35085497
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004071294A Expired - Fee Related JP4282514B2 (en) | 2004-03-12 | 2004-03-12 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4282514B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101697573B1 (en) | 2010-11-29 | 2017-01-19 | 삼성전자 주식회사 | Semiconductor device, fabricating method thereof, and semiconductor package comprising the semiconductor device |
| FR2970118B1 (en) | 2010-12-30 | 2013-12-13 | St Microelectronics Crolles 2 | INTEGRATED CIRCUIT CHIP AND METHOD OF MANUFACTURE. |
| FR2970119B1 (en) * | 2010-12-30 | 2013-12-13 | St Microelectronics Crolles 2 Sas | INTEGRATED CIRCUIT CHIP AND METHOD OF MANUFACTURE. |
| US9711403B2 (en) | 2011-01-17 | 2017-07-18 | Xintec Inc. | Method for forming chip package |
| SE538058C2 (en) | 2012-03-30 | 2016-02-23 | Silex Microsystems Ab | Method of providing a via hole and a routing structure |
| CN115084082B (en) * | 2022-07-19 | 2022-11-22 | 甬矽电子(宁波)股份有限公司 | Fan-out type packaging structure and fan-out type packaging method |
-
2004
- 2004-03-12 JP JP2004071294A patent/JP4282514B2/en not_active Expired - Fee Related
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