JP2005101268A5 - - Google Patents
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- JP2005101268A5 JP2005101268A5 JP2003333070A JP2003333070A JP2005101268A5 JP 2005101268 A5 JP2005101268 A5 JP 2005101268A5 JP 2003333070 A JP2003333070 A JP 2003333070A JP 2003333070 A JP2003333070 A JP 2003333070A JP 2005101268 A5 JP2005101268 A5 JP 2005101268A5
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- JP
- Japan
- Prior art keywords
- main surface
- forming
- semiconductor substrate
- via hole
- pad electrode
- Prior art date
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Claims (8)
前記パッド電極に対応する前記半導体基板の第２の主面上を等方的にエッチングして、当該第２の主面の一部上に凹部を形成する工程と、
前記凹部の底部を異方的にエッチングして、前記パッド電極上に前記半導体基板を貫通するビアホールを形成する工程と、
前記ビアホールを含む前記半導体基板の第２の主面上に、絶縁膜を形成する工程と、
前記ビアホールの底部の前記絶縁膜を選択的に除去し、前記パッド電極を露出する工程と、
前記ビアホールを通して、前記パッド電極と電気的に接続され、かつ前記ビアホールから前記半導体基板の第２の主面上に延びる配線層を形成する工程と、
前記半導体基板を複数の半導体チップに分割する工程と、
を具備することを特徴とする半導体装置の製造方法。 Adhering a support substrate to the first main surface including the pad electrode formed on the first main surface of the semiconductor substrate;
Forming a recess on part of the second main surface by isotropically etching the second main surface of the semiconductor substrate corresponding to the pad electrode;
Etching the bottom of the recess anisotropically to form a via hole penetrating the semiconductor substrate on the pad electrode;
Forming an insulating film on the second main surface of the semiconductor substrate including the via hole;
Selectively removing the insulating film at the bottom of the via hole and exposing the pad electrode;
Forming a wiring layer electrically connected to the pad electrode through the via hole and extending from the via hole onto the second main surface of the semiconductor substrate;
A step of dividing the semiconductor substrate into a plurality of semiconductor chips,
A method for manufacturing a semiconductor device, comprising:
前記パッド電極に対応する前記半導体基板の第２の主面上に凸部を形成するように、前記半導体基板の第２の主面の一部上をエッチングする工程と、
前記凸部に隣接し、かつ前記パッド電極の上方に位置する前記半導体基板の第２の主面上を等方的にエッチングして、当該第２の主面の一部上に凹部を形成する工程と、
前記凹部の底部を異方的にエッチングして、前記パッド電極上に前記半導体基板を貫通するビアホールを形成する工程と、
前記凸部、前記ビアホールを含む前記半導体基板の第２の主面上に、絶縁膜を形成する工程と、
前記ビアホールの底部の前記絶縁膜を選択的に除去し、前記パッド電極を露出する工程
と、
前記ビアホールを通して、前記パッド電極と電気的に接続され、かつ前記ビアホールから前記凸部上に延びる配線層を形成する工程と、
前記半導体基板を複数の半導体チップに分割する工程と、
を具備することを特徴とする半導体装置の製造方法。 Adhering a support substrate to the first main surface including the pad electrode formed on the first main surface of the semiconductor substrate;
Etching a part of the second main surface of the semiconductor substrate so as to form a protrusion on the second main surface of the semiconductor substrate corresponding to the pad electrode;
A recess is formed on a part of the second main surface by isotropically etching the second main surface of the semiconductor substrate adjacent to the protrusion and above the pad electrode. Process,
Etching the bottom of the recess anisotropically to form a via hole penetrating the semiconductor substrate on the pad electrode;
Forming an insulating film on the second main surface of the semiconductor substrate including the convex portion and the via hole;
Selectively removing the insulating film at the bottom of the via hole and exposing the pad electrode;
Forming a wiring layer electrically connected to the pad electrode through the via hole and extending from the via hole onto the convex portion;
A step of dividing the semiconductor substrate into a plurality of semiconductor chips,
A method for manufacturing a semiconductor device, comprising:
前記シード層上に、メッキ法により配線層を形成する工程と、
を含むことを特徴とする請求項１，２，３，４のいずれかに記載の半導体装置の製造方法。 The step of forming the wiring layer includes a step of forming a seed layer on the insulating film by a plating method or a sputtering method,
Forming a wiring layer on the seed layer by a plating method ;
5. The method of manufacturing a semiconductor device according to claim 1, comprising:
前記配線層上に、メッキ法によりメッキ層を形成する工程と、Forming a plating layer on the wiring layer by a plating method;
前記メッキ層上に、開口部を有したソルダーマスクを形成する工程と、Forming a solder mask having an opening on the plating layer;
前記開口部において露出した前記メッキ層の一部上に、導電端子を形成する工程と、Forming a conductive terminal on a portion of the plating layer exposed in the opening;
を含むことを特徴とする請求項１，２，３，４，５，６のいずれかに記載の半導体装置の製造方法。The method of manufacturing a semiconductor device according to claim 1, wherein:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003333070A JP2005101268A (en) | 2003-09-25 | 2003-09-25 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003333070A JP2005101268A (en) | 2003-09-25 | 2003-09-25 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2005101268A JP2005101268A (en) | 2005-04-14 |
| JP2005101268A5 true JP2005101268A5 (en) | 2006-11-02 |
Family
ID=34461188
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003333070A Pending JP2005101268A (en) | 2003-09-25 | 2003-09-25 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2005101268A (en) |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4694305B2 (en) * | 2005-08-16 | 2011-06-08 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor wafer |
| US7935977B2 (en) * | 2006-07-25 | 2011-05-03 | Lg Chem, Ltd. | Method of manufacturing organic light emitting device and organic light emitting device manufactured by using the method |
| JP5143382B2 (en) * | 2006-07-27 | 2013-02-13 | オンセミコンダクター・トレーディング・リミテッド | Semiconductor device and manufacturing method thereof |
| US7791199B2 (en) | 2006-11-22 | 2010-09-07 | Tessera, Inc. | Packaged semiconductor chips |
| US8569876B2 (en) | 2006-11-22 | 2013-10-29 | Tessera, Inc. | Packaged semiconductor chips with array |
| EP2575166A3 (en) * | 2007-03-05 | 2014-04-09 | Invensas Corporation | Chips having rear contacts connected by through vias to front contacts |
| KR101538648B1 (en) | 2007-07-31 | 2015-07-22 | 인벤사스 코포레이션 | Semiconductor packaging process using through silicon vias |
| JP2010205921A (en) | 2009-03-03 | 2010-09-16 | Olympus Corp | Semiconductor apparatus, and method of manufacturing semiconductor apparatus |
| US8796135B2 (en) | 2010-07-23 | 2014-08-05 | Tessera, Inc. | Microelectronic elements with rear contacts connected with via first or via middle structures |
| US8791575B2 (en) | 2010-07-23 | 2014-07-29 | Tessera, Inc. | Microelectronic elements having metallic pads overlying vias |
| US9640437B2 (en) | 2010-07-23 | 2017-05-02 | Tessera, Inc. | Methods of forming semiconductor elements using micro-abrasive particle stream |
| JP5656501B2 (en) * | 2010-08-06 | 2015-01-21 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | Semiconductor device and manufacturing method thereof |
| US8659152B2 (en) * | 2010-09-15 | 2014-02-25 | Osamu Fujita | Semiconductor device |
| US8847380B2 (en) | 2010-09-17 | 2014-09-30 | Tessera, Inc. | Staged via formation from both sides of chip |
| US8610259B2 (en) | 2010-09-17 | 2013-12-17 | Tessera, Inc. | Multi-function and shielded 3D interconnects |
| US8736066B2 (en) | 2010-12-02 | 2014-05-27 | Tessera, Inc. | Stacked microelectronic assemby with TSVS formed in stages and carrier above chip |
| US8637968B2 (en) | 2010-12-02 | 2014-01-28 | Tessera, Inc. | Stacked microelectronic assembly having interposer connecting active chips |
| US8587126B2 (en) | 2010-12-02 | 2013-11-19 | Tessera, Inc. | Stacked microelectronic assembly with TSVs formed in stages with plural active chips |
| US8610264B2 (en) | 2010-12-08 | 2013-12-17 | Tessera, Inc. | Compliant interconnects in wafers |
| US9711403B2 (en) * | 2011-01-17 | 2017-07-18 | Xintec Inc. | Method for forming chip package |
| KR102605400B1 (en) | 2015-03-31 | 2023-11-24 | 하마마츠 포토닉스 가부시키가이샤 | Semiconductor device and manufacturing method thereof |
| CN110867432A (en) * | 2019-11-28 | 2020-03-06 | 苏州晶方半导体科技股份有限公司 | Chip packaging structure and packaging method |
| US20230178579A1 (en) * | 2020-03-31 | 2023-06-08 | Sony Semiconductor Solutions Corporation | Light receiving element and electronic device |
-
2003
- 2003-09-25 JP JP2003333070A patent/JP2005101268A/en active Pending
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