JP2002050715A - Manufacturing method of semiconductor package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a full number of conductor patterns for plating, even if the gaps between vias constituting groups of the vias, formed interposingly between bonding pads, are formed in a narrow gap. SOLUTION: At the time of the manufacture of a semiconductor package interposingly forming a group of bonding pads on the side of one surface of a substrate 30 and a group 16 of pads for external connection terminals on the side of the other surface of the substrate 30 between a group 14A of outside vias and a group 14B of inside vias, a bus-line 32 for plating formed on the side outer than the group 14A and each via 14a of the group 14A are connected with each other through conductor patterns 34 on the side of the one surface of the substrate 30. At the same time, the bus-line 32 formed on the side further inward than the group 14B and a common line for plating are electrically connected with each other through each via 14b of the group 14B and the conductor patterns 34 on the side of the other surface of the substrate 30; and power is supplied to the package from the bus-line formed on the side of the other surface of the substrate 30 and on the side which is further outward than the group 14A to apply an electroplating to the package.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor package, and more particularly, to a plating conductor pattern electrically connected to a plating bus line when electrolytic plating is performed on a bonding pad and an external connection pad. The present invention relates to a method for manufacturing a semiconductor package capable of minimizing the problem.

[0002]

2. Description of the Related Art A semiconductor device shown in FIG. 4 is used as a semiconductor device. In the semiconductor device shown in FIG.
Bonding pad 16a formed around the mounting portion 12 on which the semiconductor element 12 is mounted, the bonding pad 16a being electrically connected to each of the electrode terminals of the semiconductor element 12 mounted on one surface of the semiconductor element 12 by a wire 18. Group 16
Are formed. Further, the bonding pads 16a,
16a, which are electrically connected to each of 16a by the conductor pattern 20 and penetrate through the substrate 10, are composed of via-hole vias 14a, 14a,.
14B is formed with the bonding pad group 16 interposed therebetween. The via group 14A is an outer via group formed outside the bonding pad group 16 on the edge side of the substrate 10, and the via group 14B is formed on the semiconductor element 12 side inside the bonding pad group 16. It is. On the other hand, on the other side of the substrate 10, the external connection terminal pads 24a, 2 electrically connected to the through-hole vias 14a, 14a,.
The external connection terminal pad group 24 composed of 4a... Is formed between the via groups 14A and 14B. The semiconductor element 12 and the wire 1 mounted on one surface of the substrate 10
, 18 and so on are resin-sealed by a sealing resin 28.

The bonding pads 16a, 16a,... And the external connection terminal pads 24a, 24a,. Noble metal plating such as gold is applied by plating. For this reason, FIG.
Is formed, and electrolytic plating is applied to a predetermined portion. On the substrate 100 on which the outer via group 14A, the inner via group 14B, the bonding pad group 16 and the external connection terminal pad group 24 are formed, a bonding portion 16a or a through-hole via 14a and an outermost via Bus line 1 for plating formed outside
04 for electrically connecting to the conductor pattern 10
2,102... Are formed. The plating conductor patterns 102 pass through gaps between the through-hole vias 14a constituting the outer via group 14A.
The plating bus line 104 and the plating conductor pattern 102 are not formed on the other surface of the substrate 100 as shown in FIG.

[0004]

According to the substrate 100 shown in FIGS. 5 and 6, power is supplied from the plating bus line 104 to the bonding portions 16a, 16a, and the external connection terminal pads 24a, 24a,. Desired electrolytic plating can be performed. However, as the size of the semiconductor device is reduced and the number of pins is increased, the gap between the through-hole vias 14a constituting the outer via group 14A becomes a narrow gap, and the number of plating conductive patterns 102 that can pass through the gap decreases. For this reason, in the semiconductor device shown in FIG. 4, there is a limit to the size reduction and the increase in the number of pins depending on the number of conductive patterns 102 for plating. Therefore, an object of the present invention is to provide a semiconductor package in which bonding pads and external connection pads are formed between via groups, even if the gap between vias in the outer via group is a narrow gap, An object of the present invention is to provide a method of manufacturing a semiconductor package capable of forming a conductive pattern for plating.

[0005]

In order to solve the above-mentioned problems, the inventors of the present invention have proposed a method of forming an outer via group located outside the bonding pad group and an inner via group located inside the bonding pad group. By electrically connecting the vias to each of the plating bus lines formed on both sides of the substrate, it is possible to reduce the number of plating conductor patterns passing through the gaps between the vias forming the via group. As a result, the present invention has been achieved. That is, the present invention provides a bonding pad group comprising a bonding pad formed by wire bonding with each of electrode terminals of a semiconductor element mounted on one surface side of a substrate around a mounting portion of the semiconductor element; An outer via group formed of vias penetrating the substrate, the outer via group being formed outside the edge side of the substrate from the group and electrically connected to each bonding pad of the bonding pad group by a conductor pattern; and the bonding pad group. An inner via group formed of vias penetrating the substrate, formed inside the mounting portion side of the semiconductor element, and electrically connected to each bonding pad of the bonding pad group by a conductor pattern; and The other surface is formed between the via groups, and each of the vias is When manufacturing a semiconductor package having an external connection terminal pad group consisting of external connection terminal pads electrically connected by a ground, the outermost via of the outer via group on one side of the substrate and the outer via group Further, the plating bus line formed further outside and the vias of the outer via group are electrically connected to each other by a conductive pattern for plating, and the innermost via on the other surface side of the substrate and the inner via group. A plating common line formed further inside and electrically connected to each via of the inner via group by a plating conductor pattern, and formed on the other surface side of the substrate and outside the outermost via. Electrically connected to the plated bus line by the conductive pattern for plating, and the bonding pad and the pad for external connection terminal are connected to both sides of the substrate. In a method of manufacturing a semiconductor package, characterized by electrolytic plating with power from the formed plating bus lines.

In the present invention, the plating bus lines formed on both sides of the substrate are electrically connected by vias penetrating the substrate, and power is supplied to the plating bus lines formed on one side of the substrate to perform electrolytic plating. , Electrolytic plating can be performed by supplying power only from one side of the substrate. When applying this electrolytic plating,
Except for bonding pads and pads for external connection terminals,
By covering both surfaces of the substrate with the plating resist, it is possible to apply electrolytic plating only to the bonding pad surface and the external connection terminal pad surface. Furthermore, by applying an underlying plating such as nickel on the bonding pad surface and the pad surface for the external connection terminal by electrolytic plating, and applying a noble metal plating such as gold on the underlying plating, external connection such as a wire or a solder ball is performed. The connection reliability with the terminal can be further improved. Further, after the electrolytic plating is performed, the common line for plating formed inside the innermost via of the inner via group is removed by etching to electrically separate adjacent bonding pads and pads for external connection terminals. be able to.

Conventionally, in a semiconductor package in which a bonding pad and an external connection pad are formed between via groups, one plating bus line formed on one surface side of the substrate and outside the outer via group includes: The conductive pattern for plating pulled out from the via and the bonding pad was electrically connected. In this regard, according to the present invention, the plating bus lines are formed on both sides of the substrate, and the plating conductor pans drawn from the outer via group are electrically connected to the plating bus lines formed on one surface side of the substrate. The conductive pattern for plating drawn out from the inner via group is electrically connected to a bus line for plating formed on the other surface side of the substrate. As a result, the number of conductive patterns for plating passing through the gaps between the vias forming the outer via group can be reduced as compared with the related art, and the gap between the vias can be narrower than the related art.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 and 2 show an example of a substrate on which electrolytic plating is performed on bonding pads and external connection pads formed between via groups in the present invention. FIG. 1 is a partial plan view showing one surface side of a substrate 30 on which electrolytic plating is performed on bonding pads and external connection pads, and FIG. 2 is a partial plan view showing the other surface side of the substrate 30. As shown in FIG. 4, a bonding pad 16a electrically connected to each of the electrode terminals of the mounted semiconductor element 12 by wires 18 is mounted on one surface side of the substrate 30 shown in FIG. And a bonding pad group 16 formed around the mounting portion to be formed. Are electrically connected to each of the bonding pads 16a, 16a,... By the conductor pattern 20, and penetrate through the substrate 30.
are formed with the bonding pad group 16 interposed therebetween. Among the via groups 14A and 14B, the via group 14A is the outer via group 14A formed on the edge side of the substrate 30 outside the bonding pad group 16 and the via group 14A.
B is an inner via group 14B formed on the semiconductor element 12 side inside the bonding pad group 16. A plating bus line 32 is formed outside the outermost via of the outer via group 14A, and the plating bus line 32 is provided with each through-hole via 14a of the outer via group 14A (hereinafter simply referred to as a via 14a). May be drawn out of the conductive pattern for plating 34, 34
.. are electrically connected. Of the outer via group 14A, vias 14a, 14a,.
Is directly electrically connected to the plating bus line 32,
Vias 14a, 14a located inside the outermost via
The conductor pattern 34 for plating passes through the gap between the vias 14a of the outermost vias, and the plating bus line 3
2 is electrically connected.

On the other hand, a via 14 is formed on the other side of the substrate 10.
a, 14a... and external connection terminal pads 24a, 24a.
Are formed between the outer via group 14A and the inner via group 14B. On the other side of the substrate 10, an outer via group 14A
The plating bus line 36 is formed on the outside of the substrate 10, and the plating bus line 36 is electrically connected to the plating bus line 32 formed on one surface side of the substrate 10 by vias (not shown). . Also, inner via group 14B
A plating common line 38 is formed on the inner side of the innermost via located at the innermost side, and the via 1 forming the inner via group 14B is formed on the plating common line 38.
4a, 14a,... Are electrically connected to the plating conductor patterns 40, 40,. Further, the plating common line 38 is electrically connected to the plating bus line 36 by a plating conductor pattern 42 passing through a gap between the vias 14a constituting the outer via group 14A. This conductive pattern for plating 42
As shown in FIG. 2, it is sufficient to form a single line on the common line 38 for plating.

In the substrate 30 to be subjected to electrolytic plating shown in FIG. 1 and FIG.
4A, each of the vias 14a, 14a,... And the plating bus line 32 are formed by the conductive patterns 34, 3 for plating.
4 ... are electrically connected. Further, the substrate 3
0, the vias 14a constituting the inner via group 14B, and the plating common line 38 electrically connected to the plating bus line 36 are connected to the plating conductor patterns 40, 40.. Are electrically connected. As described above, in the substrate 30 to be subjected to electrolytic plating shown in FIGS. 1 and 2, the vias 14a, 14a,... Of the outer via group 14A and the vias 14a, 14a,. Line 3
2 and 36 are electrically connected. For this reason, like the conventional substrate 100 for performing electrolytic plating shown in FIGS. 5 and 6,
Each of the vias 14a of the outer via group 14A and each of the bonding pads 16a, 16a,... Electrically connected to the respective vias 14a of the inner via group 14B form the plating conductor patterns 102, 102,. The number of plating conductor patterns 34 passing through the gap between the vias 14a of the outer via group 14A can be reduced as much as possible without drawing out to one plating bus line 104.

The plating conductor patterns 34 and 40 and the plating bus lines 32 and 36 shown in FIGS. 1 and 2 are formed simultaneously with the bonding pads 16a, the conductor patterns 20, 26 and the external connection terminal pads 24a, for example, by a subtractive method. Can be formed by According to such a subtractive method, first, electroless copper plating is applied to the substrate 30 in which a through hole is formed at a position where the vias 14a, 14a,. After forming the thin-film copper layer, a photoresist is applied to each surface of the substrate 30. Further, the applied photoresist is patterned to expose the inner wall surface of the through hole and a portion of the thin film copper layer where the conductor pattern 20 and the like are formed. Next, by performing electrolytic plating using the thin film copper layer as a power supply layer, stacking copper along the exposed thin film copper layer, removing the photoresist, and then removing the thin film copper layer by etching or the like. , Plating conductor patterns 34, 4
0, plating bus lines 32 and 36, vias 14a, bonding pads 16a, conductor patterns 20, 26, and external connection terminal pads 24a. Plating conductor patterns 34 and 40 and plating bus lines 32 and 36
A resist is applied to both surfaces of the substrate 30 on which only the necessary portions such as the bonding pads 16a and the external connection terminal pads 24a are exposed. In addition, Via 1
4a, 14a,... May be formed by forming a conductive pattern 20 or the like and then forming a thin-film copper layer on the inner wall surface of a through hole formed by a drill or the like by electroless copper plating or the like, and electrically connecting them. .

When the bonding pads 16a, 16a... And the external connection terminal pads 24a, 24a... Of the substrate 30 thus formed are plated by electrolytic plating, the bonding pads 16a and the external connection terminal pads are used. After applying a resist on both sides of the substrate 30 so that only 24a is exposed, the plating bus lines 32, 3
6, the bonding pad 16
a, 16a... and external connection terminal pads 24a, 24
A desired electrolytic plating can be applied to each surface of a.
As such electrolytic plating, it is preferable to apply a base metal such as nickel and then apply a noble metal plating such as gold on the base metal. Examples of the noble metal plating include palladium plating and silver plating in addition to gold plating.

After the desired electrolytic plating is applied to the bonding pads 16a, 16a, and the external connection terminal pads 24a, 24a,..., The plating common line 38 formed inside the inner via group 14B is etched. Remove. By removing the plating common line 38 by etching, the line from the bonding pad 16a to the external connection terminal pad 24a via the inner via group 14B via 14a can be electrically insulated from the adjacent line. it can. FIG. 3 shows the removal of the plating common line 38 by etching. FIG.
, The external connection terminal pad 24a having the gold plating 46 applied to the other surface of the substrate 30 or the plating common line 38
The resist 44 is applied in a state where only these necessary parts are exposed [FIG. 3 (a)]. After applying the resist 48 in this state, the resist 48 is patterned so that the plating common line 38 is exposed [FIG. 3B]. Further, the other surface of the substrate 30 is etched to remove the plating common line 38 exposed from the resists 40 and 48 [FIG. 3C], and then remove the resist 48 [FIG. )]. Further, the plating conductor patterns 34, 42 and the like electrically connected to the plating bus lines 32, 36 may be removed by etching as shown in FIG. By separating the bus lines 32 and 36 from the outermost vias, a line extending from the bonding pad 16a to the external connection terminal pad 24a via the vias 14a of the outer via group 14A and an adjacent line thereof can be formed. It can be electrically insulated. Thus, the plating bus line 3
After mounting the semiconductor element 12 at a predetermined position of the semiconductor package obtained by separating the semiconductor element 12 from the bonding pads 2 and 36, and electrically connecting the electrode terminals of the semiconductor element 12 to the bonding pads 16 a by wires 18, the semiconductor element 12 and the wires 18. By resin sealing, the semiconductor device shown in FIG. 4 can be obtained.

In the substrate 30 to be subjected to electrolytic plating shown in FIGS. 1 and 2, since the number of plating conductor patterns 34 passing through the gap between the vias 14a of the outer via group 14A can be reduced as much as possible, the outer via group 14A Via 14a
The gap between them can be narrower than the conventional substrate 100 shown in FIGS. As a result, when miniaturizing the semiconductor device or increasing the number of pins, it is possible to sufficiently cope with a narrow gap between the vias 14a of the outer via group 14A.

[0015]

According to the present invention, in a semiconductor package having a bonding pad and an external connection pad formed between via groups, a method for applying electrolytic plating to the bonding pad and the external connection terminal pad formed on the substrate is provided. The number of plating conductor patterns passing through the gaps between vias can be reduced as much as possible. As a result, the gap between the vias can be made narrower than the conventional substrate, and when miniaturizing the semiconductor device or increasing the number of pins, it is possible to sufficiently cope with the narrow gap between the vias. .

[Brief description of the drawings]

FIG. 1 is a partial plan view showing one surface side of a substrate to be subjected to electrolytic plating used in the present invention.

FIG. 2 is a partial cross-sectional view showing the other side of a substrate to be subjected to electrolytic plating used in the present invention.

FIG. 3 is a process diagram illustrating a removal process for removing a common line for plating.

FIG. 4 is a partial cross-sectional view of the semiconductor device.

FIG. 5 is a partial cross-sectional view showing one surface side of a substrate on which conventional electrolytic plating is performed.

FIG. 6 is a partial cross-sectional view showing the other side of a substrate on which conventional electrolytic plating is performed.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 12 Semiconductor element 14a Through-hole via 14 Via group 14A Outer via group 14B Inner via group 16a Bonding pad 16 Bonding pad group 20, 26 Conductive pattern 24a Pad for external connection terminal 24 Pad group for external connection terminal 30 Substrate to be subjected to electrolytic plating 32 , 36 Plating bus line 34,40,42 Plating conductor pattern 38 Plating common line

Claims (5)

[Claims] A bonding pad group formed by forming a bonding pad for wire bonding with each of electrode terminals of a semiconductor element mounted on one surface side of a substrate around a mounting portion of the semiconductor element; and the bonding pad group. An outer via group formed of vias penetrating the substrate, formed outside of the edge side of the substrate, and electrically connected to each bonding pad of the bonding pad group by a conductor pattern; and An inner via group formed of vias penetrating the substrate, formed inside the mounting portion side of the semiconductor element, and electrically connected to each bonding pad of the bonding pad group by a conductor pattern; and It is formed on the surface side sandwiched by the via group,
When manufacturing a semiconductor package including each of the vias and an external connection terminal pad group including an external connection terminal pad electrically connected by a conductor pattern, the outer via group on one surface side of the substrate; Electrically connecting plating bus lines formed further outside the outermost vias with the vias of the outer via group by plating conductor patterns, and the other side of the substrate and the inner vias. A common line for plating formed further inside than the innermost via of the group and electrically connected to each via of the inner via group by a conductive pattern for plating, and the outermost via on the other surface side of the substrate Electrically connecting a plating bus line formed outside of the bonding pad with a conductive pattern for plating, the bonding pad and an external connection end; To use pad,
A method for manufacturing a semiconductor package, comprising supplying power from a plating bus line formed on both surfaces of the substrate to perform electrolytic plating. 2. The method according to claim 1, wherein the plating bus lines formed on both sides of the substrate are electrically connected by vias penetrating the substrate, and the plating bus lines formed on one of the substrates are supplied with power to perform electrolytic plating. Item 2. The method for manufacturing a semiconductor package according to Item 1. 3. The method of manufacturing a semiconductor package according to claim 1, wherein when performing the electrolytic plating, both surfaces of the substrate are covered with a plating resist except for a bonding pad and a pad for an external connection terminal. 4. The method according to claim 1, wherein the bonding pad and the external connection terminal pad are plated with a base such as nickel by electrolytic plating, and then the noble metal such as gold is plated on the base plating.
4. The method for manufacturing a semiconductor package according to claim 1. 5. The semiconductor package according to claim 1, wherein after the electrolytic plating is performed, the plating common line formed inside the innermost via of the inner via group is removed by etching. Production method.