TWI242399B - Method of selected plating - Google Patents

Abstract

A method of selecting plating is suited for a circuit substrate. A circuit substrate provided has a first surface and a corroding second surface and has at least a first bonding pad, at least a second pad, and a pattered under coating layer. The first bonding pad and the second bonding pad are deposited on the first surface and the second surface respectively, and are electrically connected with each other. The under coating layer is deposited on the first surface neighbor to the first bonding pad. A plating seed layer is formed on the second surface of the circuit substrate, and then a first metal layer and a second metal layer are plating on the first bonding pad and the second bonding pad respectively. Finally, the exposed portion(s) of the plating seed layer is removed.

Description

1242399 V. Description of the invention (1) The technical field to which the invention belongs The present invention relates to an electroplating method, and in particular to a selective electric ore method, which does not need to make a plating line on a circuit substrate. That is, the electroplated metal layer is on the bonding pads on both sides of the circuit substrate. Previous technologies In recent years, with the rapid development of production technology in the electronics industry, the emergence of printed circuit boards (printed circuit boards, PCBs), plus the printed circuit boards can carry a variety of delicate electronic components, making printed circuit boards almost replaced The original wire bonding component system is widely used in various electronic products with different functions. In addition, with the development of integrated circuits (ICs) and computer systems, single-panel printed circuit boards can no longer provide sufficient wiring when integrated circuit designs become more and more sophisticated. The density (routing density) makes the printed circuit boards with high wiring density in the form of double-sided boards and multilayer boards appear one after another. In the practical application of printed circuit boards, printed circuit boards can be used as circuit carriers for main boards of computer systems, and printed circuit boards with fine circuits can also be used as chips. Circuit substrates for packaging o As for circuit substrates for chip packaging, 'known circuit substrates typically have multiple patterned conductive layers, at least one insulating layer, and multiple conductive vias, where the insulating layers are arranged adjacent to each other Between two conductive layers, and these conductive holes penetrate at least one insulating layer for electrically connecting at least two

11477T ~ 1.PTD Page 7 1242399 V. Description of the invention (2) Conductive layers on both sides of the insulating layer. Therefore, the integrated circuit chip can be electrically connected to the top surface of the circuit substrate through flip chip bonding or wire bonding, and then indirectly through the internal circuits of the circuit substrate and The contacts on the bottom surface (such as conductive balls or pins) are further electrically connected to other electronic devices on the outside. For wire bonding and ball grid array (W ire ο nding / B a 1 1 Grid Array, WB / BGA) type chip packages, the patterned conductive layer on the top surface of the circuit substrate will form multiple bonding pads (Bonding pad) is used to connect the ends of multiple wires respectively, and the patterned conductive layer on the bottom surface of the circuit substrate forms multiple bonding pads, which are used to electrically connect multiple conductive balls, respectively. It is worth noting that because the commonly used material of the patterned conductive layer is copper, in order to avoid oxidation of the bonding pads made of copper, and to improve the yield and reliability of the end of the wire connected to the bonding pads, A metal layer, such as a nickel / gold layer (Ni / Au layer), is formed on each of the upper electrodes. In order to form a metal layer on the surface of the bonding pads on both sides of the circuit substrate, usually one to several plating lines are formed around the circuit substrate, and a plurality of plating stubs are formed to form a metal layer. These bonding pads and the above-mentioned plating lines are electrically connected respectively, so that the current for electroplating can be provided to the bonding pads of the circuit substrate through the above-mentioned plating lines and short plating sections, so as to facilitate plating on the surfaces of these bonding pads, respectively. A metal layer is formed. However, this method will leave many plating short wires on the surface of the circuit substrate.

11477T-1.PTD Page 8 1242399 V. Description of the invention (3). It is worth noting that these plated short line segments will occupy the wiring area of the circuit substrate, and as a result, the wiring density of the circuit substrate cannot be effectively improved. In addition, these plated short line segments will further interfere with the signal transmission of the circuit substrate, thereby reducing the electrical performance of the circuit substrate. During the process of forming a metal layer by electroplating on the bonding pads on the surface of the circuit substrate, in order to make these bonding pads to obtain the current used for electroplating to form the metal layer without using the conventional plating lines and short plating segments, the conventional technology has been developed A selective electric bonding method, the key of which is that a plating seed layer must be formed on both sides of the circuit substrate, and after the two plating seed layers are patterned, the current for plating can be provided to the circuit through the two plating seed layers. These bonding pads on both sides of the substrate. However, the conventional selective electric bonding method must form two electric ore seed layers, and a considerable number of steps are required in patterning and subsequent removal of these plating seed layers, which will lead to a circuit substrate manufacturing process using the conventional selective electroplating method. Requires longer production cycles and higher production costs. SUMMARY OF THE INVENTION In view of this, an object of the present invention is to provide a selective electroplating method for forming at least one metal layer on a bonding pad on both sides of a circuit substrate by electroplating. According to the above object of the present invention, the present invention proposes a selective plating method. First, a circuit substrate is provided, which has a first surface and a corresponding second surface, and has at least a first bonding pad, at least a second bonding pad, and a patterned inter-circuit insulation layer, wherein the first bonding pad And the second bonding pad are respectively disposed on the first surface and the second surface of the circuit substrate, and the

11477T ~ 1.PTD Page 9 1242399 V. Description of the invention (4) The first bonding pad is electrically connected to the second bonding pad, and the inter-circuit insulation layer is arranged on the first side of the circuit substrate and is adjacent to A first bonding pad is then formed with a plating seed layer on the second surface of the circuit substrate, and then a first metal layer and a second metal layer are plated on the first bonding pad and the second bonding pad, respectively, and finally moved Remove the exposed part of the plating seed layer. Based on the above, the circuit substrate provided by the present invention at the beginning of the process has a patterned inter-circuit insulation layer, which is arranged on the first side of the circuit substrate and adjacent to the first bonding pad to fill the first The space surrounded by the bonding pad and other bonding pads or wires adjacent to the bonding pad makes the surface of the first bonding pad and the insulation layer between the lines a smooth surface, which can increase the yield of subsequent processes. In addition, in the present invention, a plating seed layer is formed on the second surface of the circuit substrate respectively, and then an internal circuit for electrically connecting the first bonding pad and the second bonding pad through the plating seed layer and the circuit substrate to The first metal layer is electroplated on the first bonding pad, and a second metal layer is electroplated on the second bonding pad through the plating seed layer. In addition, in the present invention, the second metal layer can be defined on the second bonding pad with a patterned mask layer or a patterned solder mask layer during the plating of the second metal layer to the electric ore seed layer. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a number of embodiments are given below and described in detail with the accompanying drawings. First Embodiment

11477T ~ 1.PTD Page 10 1242399 V. Description of the invention (5) Please refer to FIGS. 1A ~ 1D, which are cross-sectional views showing a selective plating method according to the first embodiment of the present invention. As shown in FIG. 1A, a circuit substrate 100 is first provided, which is composed of a multilayer patterned conductive layer, at least one insulating layer, and a plurality of conductive vias, wherein the insulating layer is arranged in any two adjacent patterning patterns. At least two patterned conductive layers are electrically connected between the conductive layers and via the conductive holes, and the patterned conductive layers and the conductive vias together form an internal circuit of the circuit substrate 100. As shown in FIG. 1A, the circuit board 100 has a plurality of first bonding pads 10 2 a and a plurality of second bonding pads 10 2 b, which are respectively disposed on a first surface of the circuit board 1 0 0. 100a and a corresponding second surface 100b, and the first bonding pads 10 2 a and the second bonding pads 10 2 b can be respectively formed by two outermost patterned conductive layers of the circuit substrate 1 0 0 Make up. As shown in FIG. 1A, the circuit substrate 100 further has a patterned inter-circuit insulation layer 1 12a, which is disposed on the first surface 100a of the circuit substrate 100 and is adjacent to the first substrate 100. A bonding pad 1 0 2 a is used to fill the space surrounded by the first bonding pad 1 0 2 a and other bonding pads or wires adjacent thereto, so that the first bonding pad 1 0 2 a and the insulation layer between the lines The surface of 1 1 2 a forms a smooth surface to increase the yield of subsequent processes. In addition, the circuit substrate 100 may optionally have a patterned inter-circuit insulation layer 1 12b, which is disposed on the second surface 100b of the circuit substrate 100 and is adjacent to the second bonding pad 102b for Fill the space surrounded by the second bonding pad 1 0 2 b and other bonding pads or wires adjacent to it, so that the surface of the second bonding pad 1 0 2 b and the interlayer insulation layer 1 1 2 b forms a smooth surface It is also used to increase the yield of subsequent processes.

11477T ~ 1.PTD Page 11 1242399 V. Description of the invention (6) As shown in FIG. 1A, the circuit substrate 100 further has a patterned first solder mask layer 104a, which is arranged on the first surface and Cover at least part of the first inter-circuit insulation layer 1 1 2 a, and can be defined by a solder mask (S ο 1 der

Mask Define (SMD) or Non Solder Mask Define (NSMD) method to expose these first bonding pads 1 0 2 a. Here, the non-solder mask definition (n SM D) is used. the way. In addition, the circuit substrate 100 further has a patterned second solder mask layer 104b, which is disposed on the second surface 100b, and covers at least a part of the second inter-circuit insulation layer 112b ', and can also be defined by a solder mask. (SMD) or non-solder mask definition (NSMD) method to expose these second bonding pads 102b. Here, the solder mask definition (SMD) method is used. As shown in FIG. 1B, after the above-mentioned circuit substrate is provided, a plating seed layer is comprehensively formed on the second surface 100b 'of the circuit substrate 100, and the plating seed layer 106 further covers these. The second bonding pad 102b is exposed to portions of the second solder mask layer 104b. As shown in FIG. 1B, after the plating seed layer 106 is formed, a patterned mask layer 108 is then formed on the second surface 100b of the circuit substrate 100, where the mask layer 108 is Parts of the power ore seed layer 106 above the second bonding pads 102b are exposed. As shown in FIG. 1C, after forming the cover layer 108, an electric current is then supplied to the first bonding pads 102a through the internal wiring of the plating seed layer 106 and the circuit substrate 100, for A first metal layer iia is plated on the first bonding pads 102a, respectively. In addition, while the first metal layers 1 1 0 a are being plated, a current can be provided to the plating seed layer for separation.

11477TM.PTD Page 12 1242399 V. Description of the invention (7) Don't electroplate one-two second metal layer 11 Ob to these second bonding pads 102b. The first metal layer 11 0 a and the second metal layer 11 Ob described above may be a single metal layer or multiple metal layers such as a nickel-gold layer. As shown in FIG. 1D, the first metal layers 11 0 a and these After the second metal layer 11 Ob, the cover layer 1 08 of FIG. 1C is removed, and the exposed portion of the plating seed layer 106 is used to pattern the electric key; the heavy sublayer 1 06 is exposed, and The portion of the 22 solder mask layer 1 08 that is not covered by these second metal layers 11 Ob. The above-mentioned method for removing the plating seed layer 1 06 is, for example, 1 etch in g: and grinding (P ο 1 is h;)-etc. Based on the above j, the first embodiment of the present invention is to sequentially form a plating seed layer and a patterned mask layer on one side of the circuit substrate, and pass the plating seed layer and the mask layer to Electroplating a metal layer to a plurality of bonding pads on the surface of the circuit substrate Furthermore, a metal layer can be electroplated to a plurality of bonding pads on the other side of the circuit substrate through the plating seed layer and the internal circuit of the circuit substrate. Finally, the mask layer is removed. Therefore, the first embodiment of the present invention only needs to be fabricated. A single plating seed layer and a single patterned mask layer, and through the plating seed layer, the internal circuit of the circuit substrate and the mask layer can simultaneously form a metal layer on the bonding pads on both sides of the circuit substrate. In the first embodiment, the plating seed layer is sequentially formed. The patterned mask layer and the metal layer are sequentially formed. The second embodiment is the plating seed layer and the patterned mask layer are sequentially formed. Please refer to FIG. 2A and 2D. Selection of the first embodiment of the present invention

11477T ~ l.PTD Page 13 1242399 V. Description of the invention (8) Sectional view of selective plating method. As shown in FIG. 3A, a circuit substrate 2000 is first provided, and its composition has been disclosed in the circuit substrate 100 of the first embodiment, and details are not described herein again. The circuit substrate 200 has a plurality of first bonding pads 202a and a plurality of second bonding pads 202b, which are respectively disposed on one of the first surfaces 200a of the circuit substrate 200a and the corresponding one of the second surfaces 200b. A bonding pad 202a and these second bonding pads 2 2 b can be respectively composed of two outermost patterned conductive layers of the circuit substrate 200. As shown in FIG. 2A, the circuit substrate 2 0 has a patterned inter-circuit insulation layer 2 1 2 a, which is disposed on the first surface 2 0 0 a of the circuit substrate 2 0 and is adjacent to the first substrate 2 0 0. A bonding pad 2 0 2 a is used to fill the space surrounded by the first bonding pad 2 2 a and other bonding pads or wires adjacent to it, so that the first bonding pad 2 0 2 a and the insulation layer between the lines The surface of 2 1 2 a forms a smooth surface to increase the yield of subsequent processes. In addition, the circuit substrate 200 may optionally have a patterned inter-circuit insulation layer 2 1 2 b, which is disposed on the second surface 200 b of the circuit substrate 200 and is adjacent to the second bonding pad 202 b for Fill the space surrounded by the second bonding pad 2 0 2 b and other bonding pads or wires adjacent to it, so that the surface of the second bonding pad 2 0 2 b and the insulation layer 2 1 2 b between the lines forms a smooth surface It is also used to increase the yield of subsequent processes. As shown in FIG. 2A, the circuit substrate 200 further has a patterned first solder mask layer 204a, which is disposed on the first surface 200a and covers at least a part of the first inter-circuit insulation layer 2 1 2 a. Welding mask definition (SMD) or non-soldering mask definition (NSMD) method to partially or completely expose these first bonding pads 2 002 a. Here, the non-soldering mask definition (NSMD) is used.

11477Τ ~ 1.PTD Page 14 1242399 V. Description of the invention (9) Method, that is, the first bonding pads 2 0 2 a are all exposed. In addition, the circuit substrate 200 further has a patterned second solder mask layer 204b, which is disposed on the second surface 200b, and covers at least a portion of the second inter-circuit insulation layer 212b, and can also be defined as a solder mask (SMD ) Or non-solder mask definition (NSMD) method to partially or completely expose these second joints 0 2 0 2 b, here is to use the welding mask definition (SMD) method, that is, to partially expose these first joints Two bonding pads 2 0 2 b. As shown in FIG. 2B, after the above-mentioned circuit substrate 200 is provided, a plating seed layer 206 is then comprehensively formed on the second surface 200b of the circuit substrate 200, and the plating seed layer 206 further covers these A portion of the second bonding pad 202b exposed to the second solder mask layer 204b. As shown in FIG. 2B, after the plating seed layer 206 is formed, current is then supplied to the first bonding pads 2 0 2 a through the plating seed layer 206 and the internal wiring of the circuit substrate 200 for plating. A first metal layer 210a is disposed on the first bonding pads 202a. In addition, while the first metal layers 210a are being plated, a current can be provided to the plating seed layer 206 for comprehensively plating a second metal layer 210b onto the plating seed layer 206. The first metal layer 210a and the second metal layer 210b described above may be a single metal layer or multiple metal layers, such as a gold recording layer. As shown in FIG. 2B, after forming the first metal layer 210a and the second metal layer 210b, a patterned mask layer 208 is formed on the second metal layer 210b. The mask layer 208 is A plurality of portions of the second metal layer 210b overlying the second bonding pads 202b are covered. As shown in FIG. 2C, a plating seed layer 206 and a second metal are sequentially formed.

11477TM.PTD Page 15 1242399 V. Description of the invention (ίο) After the layer 210b and the mask layer 208, the exposed portion of the second metal layer 210b is removed to pattern the second metal layer 210b, and then moved The exposed part of the electroplated metal layer 206 is used to pattern the electroplated metal layer 206. The above-mentioned method for removing the plating seed layer 206 is, for example, etching and grinding. As shown in FIG. 2D, after patterning the second metal layer 210b and the electroplated metal layer 206, the mask layer 208 of FIG. 2C is removed, and the surface of the patterned second metal layer 210b is exposed. Based on the above, the second embodiment of the present invention is to form an electric ore seed layer on one side of the circuit substrate, and to plate a metal layer to the other side of the circuit substrate via the key seed layer and the internal circuit of the circuit substrate, respectively. A bonding pad, and simultaneously forming a metal layer on the plating seed layer through the plating seed layer, and then forming a patterned mask layer on the plating seed layer and the metal layer, and then removing the exposed metal layer Then, the exposed part of the plating seed layer is removed, and finally the mask layer is removed. Therefore, the second embodiment of the present invention only needs to make a single plating seed layer, and form a metal layer on the bonding pads on both sides of the circuit substrate through the plating seed layer and the internal circuit of the circuit substrate, and then pass a single patterned mask Layer to pattern a metal layer on one side of the circuit substrate that has not been patterned. Compared with the first and second embodiments, the third embodiment has two solder mask layers formed on both sides of the circuit substrate in advance. The third embodiment is based on these bonding pads, which respectively form a metal layer on both sides of the circuit substrate. In the future, it will be formed separately

11477T-1.PTD Page 16 1242399 V. Description of the invention (11) One of the patterned solder mask layers is on both sides of the circuit substrate, and the metal layers on these bonding pads are exposed. Please refer to FIGS. 3A to 3D, which are cross-sectional views showing a selective plating method according to a third embodiment of the present invention. As shown in FIG. 3A, a circuit substrate 300 is first provided, and its composition has also been disclosed in the circuit substrate 300 of the first embodiment, and details are not described herein again. The circuit substrate 300 has a plurality of first bonding pads 302a and a plurality of second bonding pads 3 0 2 b, which are respectively disposed on one of the first surfaces 3 0 0 a of the circuit substrate 300 and the corresponding one of the second surfaces 300 b. In addition, the first bonding pads 302a and the second bonding pads 3 2 b may be respectively composed of two outermost patterned conductive layers of the circuit substrate 300. As shown in FIG. 3A, the circuit substrate 3 0 0 further has a patterned inter-line insulation layer 3 1 2 a, which is disposed on the first surface 3 0 0 a of the circuit substrate 3 0 0 and is adjacent to the first A bonding pad 3 0 2 a is used to fill the space surrounded by the first bonding pad 3 0 2 a and other bonding pads or wires adjacent to it, so that the first bonding pad 3 0 2 a and the insulation layer between the lines The surface of 3 1 2 a forms a smooth surface to increase the yield of subsequent processes. In addition, the circuit substrate 3 0 may optionally have a patterned inter-circuit insulation layer 3 1 2 b, which is disposed on the second surface 300 b of the circuit substrate 300 and is adjacent to the second bonding pad 302 b for Fill the space surrounded by the second bonding pad 3 0 2 b and other bonding pads or wires adjacent to it, so that the surface of the second bonding pad 3 0 2 b and the insulation layer 3 1 2 b between the lines forms a smooth surface It is also used to increase the yield of subsequent processes. As shown in FIG. 3B, after the above-mentioned circuit substrate 300 is provided, a plating seed layer 3 06 is formed on the second surface of the circuit substrate 300 in a comprehensive manner.

11477T ~ 1.PTD Page 17 1242399 V. Description of the Invention (12) 300b, in which the plating seed layer 306 covers the second bonding pads 302b and the inter-circuit insulation layer 312b, and the plating seed layer 306 covers the second bonding. The other parts of the patterned conductive layer of the pad 3 2, such as the wire part. As shown in FIG. 3B, after forming the electric power seed layer 306, a patterned first mask layer 308a is formed on the first surface 300a of the circuit substrate 300, and a patterned second mask is formed at the same time. The layer 308b is on the plating seed layer 306 on the second surface 300b of the circuit substrate 300. In addition, the first cover layer 3 0 8 a covers at least a part of the first inter-circuit insulation layer 3 1 2 a, and the first bonding pads 302 a may be fully (or partially) exposed. In addition, the second cover screen layer 3 0 8 b also covers at least a part of the second inter-circuit insulation layer 3 1 2 b, and may partially (or completely) expose those located above the second bonding pads 302 b. Portions of the seed layer 306 are plated. As shown in FIG. 3C, after the first cover layer 308a and the second cover layer 3 0 8 b are formed, the current is then supplied to the internal circuit through the plating seed layer 3 06 and the circuit substrate 3 0 0. The first bonding pads 3 0 2 a are used to electroforge a first metal layer 310 a onto the first bonding pads 302 a respectively. In addition, while these first metal layers 310a are being plated, a current can be provided to the plating seed layer 306 for plating a second metal layer 310b to portions of the plating seed layer 306 on the second bonding pad 302b, respectively. The first metal layer 310a and the second metal layer 310b described above may be a single metal layer or multiple metal layers, such as a nickel-gold layer. As shown in FIG. 3D, a plating seed layer 306 and a first cover curtain layer are formed.

11477T ~ 1.PTD Page 18 1242399 V. Description of the invention (13) 308a, second mask layer 308b, these first metal layers 310a and these second metal layers 310b, then remove the first mask of FIG. 3C Layer 308a, the second mask layer 308b, and then the exposed part of the plating seed layer 306 is removed to pattern the plating seed layer 306. The aforementioned method for removing the plating seed layer 206 is, for example, etching and polishing. As shown in FIG. 3D, after the exposed portion of the key metal layer 206 is removed, a patterned first solder mask layer 304a can be selectively formed on the first surface 300a of the circuit substrate 300, where the first The solder mask layer 304a covers at least a part of the first inter-circuit insulation layer 3 1 2a, and the first metal layer 310a can be completely (or partially) exposed. In addition, a patterned second solder mask layer 3 0 4b can be selectively formed on the second surface 300b of the circuit substrate 3 00, where the second solder mask layer 304b covers at least a part of the second circuit insulation and edge. Layer 3 1 2 b, and these second metal layers 310b may be fully (or partially) exposed. Based on the above, the third embodiment of the present invention is to form a plating seed layer and a patterned mask layer on one surface of the circuit substrate, and form another patterned mask layer on the other surface of the circuit substrate, and pass Plating the seed layer to plate a metal layer to the bonding pads on that side of the circuit substrate, and plating the metal layer to the bonding pads on the other side of the circuit substrate via the plating seed layer and the internal wiring of the circuit substrate, Then, the two cover layers are removed, and then the exposed part of the key seed layer is removed. Finally, a patterned solder mask layer is formed on both sides of the circuit substrate, and the solder mask layer is completely or partially exposed. These metal layers. Fourth embodiment

11477T ~ 1.PTD Page 19 1242399 V. Description of the invention (14) Compared with the third embodiment, a plurality of metal layers are formed on the bonding pad by using a plating seed layer and a patterned cover layer. The fourth embodiment is the first After the plating seed layer and the metal layer are formed, a patterned mask layer is then formed on the metal layer, and then the exposed portion of the metal layer and the exposed portion of the plating seed layer are sequentially removed. Please refer to FIGS. 4A to 4D, which are cross-sectional views showing a selective plating method according to a fourth embodiment of the present invention. As shown in FIG. 4A, a circuit substrate 400 is first provided, and its composition has also been disclosed in the circuit substrate 400 of the first embodiment, and details are not described herein again. The circuit board 400 has a plurality of first bonding pads 402a and a plurality of second bonding pads 402b, which are respectively disposed on a first surface 400a and a corresponding second surface 400b of the circuit substrate 400, and these first bonding pads 4 02a and these second bonding pads 4 2 b can be respectively composed of two outermost patterned conductive layers of the circuit substrate 400. As shown in FIG. 4A, the circuit substrate 3 0 0 further has a patterned inter-circuit insulation layer 3 1 2 a, which is arranged on the first surface 3 0 0 a of the circuit substrate 2 0 0 and is adjacent to the first A bonding pad 302a is used to fill the space surrounded by the first bonding pad 302a and other bonding pads or wires adjacent to the first bonding pad 302a, so that the surfaces of the first bonding pad 3 0 2 a and the inter-circuit insulation layer 3 1 2 a Form a smooth surface to increase the yield of subsequent processes. In addition, the circuit substrate 3 0 0 may optionally have a patterned inter-circuit insulation layer 3 1 2 b, which is disposed on the second surface 3 0 0 b of the circuit substrate 3 0 0 and is adjacent to the second bonding The pad 3 0 2 b is used to fill the space surrounded by the second bonding pad 3 0 2 b and other bonding pads or wires adjacent thereto, so that the second bonding pad 3 0 2 b and the insulation layer between the lines 3 1 Table of b

11477T ~ 1.PTD Page 20 1242399 V. Description of the invention (15) The surface constitutes a smooth surface, which is also used to increase the yield of subsequent processes. As shown in FIG. 4B, after the above-mentioned circuit substrate 400 is provided, a plating seed layer 406 is then comprehensively formed on the second surface 400b of the circuit substrate 400, wherein the plating seed layer 406 covers the second bonding pads. 4 02b and the inter-circuit insulation layer 4 1 2 b, and the plating seed layer 4 0 6 covers other parts of the patterned conductive layer constituting the second bonding pads 4 2, such as a wire portion. As shown in FIG. 4B, after the above-mentioned power ore seed layer 406 is provided, a patterned first cover layer 408a is then formed on the first surface 400a of the circuit substrate 400, where the first cover layer 408a covers at least The first inter-circuit insulation layer 4 1 2 a is partially, and the first bonding pads 4 0 2 a may be fully (or partially) exposed. As shown in FIG. 4B, after the first cover layer 408a is formed, an electric current is then supplied to the first bonding pads 4 0 2 a through the plating seed layer 4 06 and the internal wiring of the circuit substrate 4 0 0. For plating the first metal layer 410a on the first bonding pads 402a, respectively. In addition, while the first metal layers 410a are being plated, a current can be supplied to the clock seed layer 406 to comprehensively charge a second metal layer 410b to the key seed layer 406. The first metal layer 410a and the second metal layer 410b described above may be a single metal layer or multiple metal layers, such as a gold recording layer. As shown in FIG. 4B, after forming the first metal layer 410a and the second metal layer 410b, a patterned second cover layer 408b is formed on the second metal layer 410b, where the second cover layer 408b is covered in

11477TM.PTD Page 21 1242399 V. Description of the invention (16) Multiple portions of the second metal layer 410b above the second bonding pads 402b. As shown in FIG. 4C, after the second mask layer 408b is formed, the exposed portion of the second metal layer 410b is then removed to pattern the second metal layer 410b, and then the exposed portion of the plating seed layer 406 is removed. Part for patterning the plating seed layer 406. The above-mentioned method for removing the plating seed layer 406 and the second metal layer 408b is, for example, etching. As shown in FIG. 4D, after removing the exposed portion of the second metal layer 410b and the exposed portion of the plating seed layer 406, the first cover layer 408a and the second cover are then removed as shown in FIG. 7B. Curtain layer 408b. It is worth noting that after forming these first metal layers 410a, the first cover layer 408a can be removed, and as shown in FIG. 4D, after removing the first cover layer 408a and the second cover After layer 4 0 8 b, a patterned first solder mask layer 404 a may be optionally formed on the first surface 400 a of the circuit substrate 400, wherein the first solder mask layer 4 0 4 a covers at least a part of The first inter-circuit insulation layers 4 1 2 a may completely (or partially) expose these first metal layers 410 a. In addition, a patterned second solder mask layer 4 0 4 b may be selectively formed on the second surface 400 b of the circuit substrate 400, where the second solder mask layer 404 b covers at least a part of the second inter-circuit insulation layer. 4 1 2 b, and the portions of the second metal layer 410b above the second bonding pads 402b may be fully (or partially) exposed. Based on the above, the fourth embodiment of the present invention is to form a plating seed layer on one side of the circuit substrate, which covers the surface of the circuit substrate.

11477T ~ 1.PTD Page 22 1242399 V. Description of the invention (17) bonding pads and forming a patterned one mask layer on the other side of the circuit substrate, wherein the mask layer is more exposed on the other side of the circuit substrate Bonding pads. Next, a metal layer is comprehensively formed on the surface of the circuit substrate through the plating seed layer, and a metal layer is respectively plated on the plurality of bonding pads on the other side of the circuit substrate through the plating seed layer and the internal wiring of the circuit substrate. . Next, the cover layer on the other side of the circuit substrate is removed, and the electric ore seed layer and the metal layer on the one side of the circuit substrate are patterned, so that a plurality of bonding pads on the one side of the circuit substrate are respectively provided with a plating seed layer. And part of the metal layer. According to the above embodiments of the present invention, the present invention forms a plating seed layer on the second surface of the circuit substrate, and then electrically connects the first bonding pad and the second bonding through the plating seed layer and the circuit substrate. The pad's internal circuit is used to plate a first metal layer onto the first bonding pad, and at the same time, a second metal layer is plated onto the second bonding pad through the plating seed layer. It is worth noting that during the plating of the second metal layer to the plating seed layer, a patterned mask layer or a patterned solder mask layer can be used to define the second metal layer on the second bonding pad. In summary, the selective plating method of the present invention has the following advantages: (1) Since the circuit substrate provided by the present invention at the beginning of the process already has a patterned inter-circuit insulation layer, which is arranged on one side of the circuit substrate, and A bonding pad adjacent to the surface of the circuit substrate is used to fill the space surrounded by the bonding pad and other bonding pads or wires on the adjacent side, so that the surface of the bonding pad and the insulation layer between the lines forms a smooth surface. Therefore, the yield of subsequent processes can be increased.

11477TM.PTD Page 23 1242399 V. Description of the invention (18) (2) Since the present invention does not require a conventional plating line and plating short line segment to electrically connect the bonding pads on the top surface of the circuit substrate, and can pass through a single plating seed layer and wiring The internal circuit of the substrate, and the metal layer is formed on the bonding pads on both sides of the circuit substrate by electroplating, so that the circuit substrate of the present invention can obtain a larger wiring space and a higher wiring density. (3) Since the present invention does not need to know the electroplated wire and electroplated short line segments to electrically connect the bonding pads on the top surface of the circuit substrate, the metal layer can be formed by electroplating through a single electroplated seed layer and the internal circuits of the circuit substrate. On the surfaces of the bonding pads on both sides of the circuit substrate, the circuit substrate of the present invention will not have the above-mentioned plating short line segments to interfere with signal transmission, so the circuit substrate of the present invention will have better electrical performance. (4) Compared with the conventional selective plating method, it is necessary to form two plating seed layers and the steps and costs derived therefrom. Because the present invention only needs a single plating seed layer and internal circuits with a circuit substrate, it can provide plating. The current flows to the bonding pads on both sides of the circuit substrate, and a metal layer is formed on the surfaces of the bonding pads on both sides of the circuit substrate by electroplating, so the present invention can effectively reduce the cycle and cost of the manufacturing process of the circuit substrate. Although the present invention has been disclosed as above with multiple embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and retouch without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.

11477T-1.PTD Page 24 1242399 Brief description of the drawings Figs. 1A to 1D are sectional views showing the selective plating method according to the first embodiment of the present invention. 2A to 2D are sectional views showing a selective plating method according to a second embodiment of the present invention. 3A to 3D are sectional views showing a selective plating method according to a third embodiment of the present invention. 4A to 4D are sectional views showing a selective plating method according to a fourth embodiment of the present invention. [The legend does not explain] 1 0 0: circuit board 1 0 0 a: first surface 1 00b: second surface 1 0 2 a: first bonding pad 1 0 2 b: second bonding pad 1 0 4 a: First solder mask layer 1 0 4 b: Second solder mask layer 1 0 6: Plating seed layer 1 08: Mask layer 110 a · First metal layer 1 1 Ob: Second metal layer 1 1 2 a: First Insulation layer between lines 1 1 2 b: Second insulation layer between lines 2 0 0: Line substrate 2 0 0 a: First side

11477T ~ 1.PTD Page 25 1242399 Brief description of the drawing 2 0 0 b Second surface 2 0 2 a First bonding pad 2 0 2 b Second bonding pad 2 0 4 a First solder mask layer 2 0 4 b No. 2 solder cover layer 2 0 6: plating seed layer 2 0 8 ·· mask layer 2 10a first metal layer 2 10b second metal layer 2 12a first inter-circuit insulation layer 212b second inter-circuit insulation layer 3 0 0: Circuit board 3 0 0 a first surface 3 0 0 b second surface 3 0 2 a first bonding pad 3 0 2 b second bonding pad 3 0 4 a first solder mask layer 3 0 4b second solder mask layer 3 0 6: plating seed layer 3 0 8 a first cover layer 3 0 8 b second cover layer 310a first metal layer 310b second metal layer 312a first inter-circuit insulation layer

11477T-1.PTD Page 26 1242399 Brief description of the drawing 3 1 2 b: Second inter-circuit insulation layer 4 0 0: Circuit board 4 0 0 a: First surface 4 0 0 b ·· Second surface 4 0 2 a: First bonding pad 402b: Second bonding pad 404a: First solder mask layer 404b: Second solder mask layer 4 0 6: Plating seed layer 4 0 8 a: First mask layer 4 0 8 b: Second Cover layer 41 0a: first metal layer 4 1 Ob: second metal layer 4 1 2 a: first inter-circuit insulation layer 4 1 2 b: second inter-circuit insulation layer

11477T ~ 1.PTD Page 27

Claims (1)

1242399 6. Scope of patent application 1. A selective plating method includes at least: providing a circuit substrate having a first surface and a corresponding second surface, and the circuit substrate having at least a first bonding pad, At least a second bonding pad, a patterned first inter-circuit insulation layer, a patterned first solder mask layer, and a patterned second solder mask layer, and the first bonding pad and the second bonding pad Respectively disposed on the first surface and the second surface, and the first bonding pad is electrically connected to the second bonding pad, and the first inter-circuit insulation layer is disposed on the first surface of the circuit substrate, And is adjacent to the first bonding pad, and the first solder mask layer is disposed on the first surface and covers at least a part of the first inter-circuit insulation layer to expose the first bonding pad, and the first bonding pad Two solder mask layers are disposed on the second surface and expose the second bonding pad; forming a plating seed layer on the second surface of the circuit substrate; forming a patterned mask layer on the circuit substrate; The second side, but the cover layer exposes the plating A portion of the seed layer above the second bonding pad; electroplating a first metal layer and a second metal layer on the first bonding pad and the second bonding pad, respectively; removing the cover layer And removing the exposed portion of the plating seed layer. 2. The selective plating method as described in item 1 of the scope of patent application, wherein the circuit substrate further comprises a patterned second inter-circuit insulation layer, which is disposed on the second side of the circuit substrate and adjacent to the second surface. The second bonding pad, and the second solder mask layer covers at least a part of the second line insulation 11477TM.PTD Page 28 1242399 Sixth, the scope of patent application. 3. The selective plating method according to item 1 of the patent application scope, wherein the method of removing the plating seed layer includes one of etching and grinding. 4. A selective plating method, comprising at least: providing a circuit substrate having a first surface and a corresponding second surface, and the circuit substrate having at least a first bonding pad and at least a second bonding pad. , A patterned first inter-circuit insulation layer, a patterned first solder mask layer, and a patterned second solder mask layer, and the first bonding pad and the second bonding pad are respectively disposed on the first Surface and the second surface, and the first bonding pad is electrically connected to the second bonding pad, and the first inter-circuit insulation layer is disposed on the first surface of the circuit substrate and is adjacent to the first bonding pad. A bonding pad, and the first solder mask layer is disposed on the first surface and covers at least a part of the first inter-circuit insulation layer to expose the first bonding pad, and the second solder mask layer is configured On the second surface and exposing the second bonding pad; forming a plating seed layer on the second surface of the circuit substrate; a key metal layer and a second metal layer on the first bonding pad, respectively Over the plating seed layer; forming a patterned mask Layer on the second side of the circuit substrate, and the cover layer covers the portion of the second metal layer above the second bonding pad; removes the exposed portion of the second metal layer; Removing the exposed portion of the plating seed layer; and removing the mask layer. 11477TM.PTD Page 29 1242399 VI. Patent Application Range 5. The selective plating method described in item 4 of the patent application range, wherein the circuit substrate further includes a patterned second inter-circuit insulation layer, which is disposed in the The second surface of the circuit substrate is adjacent to the second bonding pad, and the second solder mask layer covers at least a part of the second inter-circuit insulation layer. 6. The selective electroplating method according to item 4 of the scope of patent application, wherein the method of removing the second metal layer includes etching. 7. The selective electroplating method according to item 4 of the scope of patent application, wherein the method of removing the plating seed layer includes one of etching and grinding. 8. A selective plating method, at least comprising: providing a circuit substrate having a first surface and a corresponding second surface, and the circuit substrate having at least a first bonding pad and at least a second bonding Pad and a patterned first inter-circuit insulation layer, and the first bonding pad and the second bonding pad are respectively disposed on the first surface and the second surface, and the first bonding pad is electrically connected to the first bonding pad and the second bonding pad. A second bonding pad, and the first inter-circuit insulation layer is disposed on the first surface of the circuit substrate and is adjacent to the first bonding pad; and forming a plating seed layer on the second surface of the circuit substrate Forming a patterned first mask layer and a patterned second mask layer on the first surface of the circuit substrate and the plating seed layer, respectively, and the first mask layer is exposed to the A portion of the plating seed layer above the second bonding pad; a first metal layer and a second metal layer of the electric key are respectively on the first bonding pad and the second bonding pad; 11477T-1.PTD Page 30 1242399 6. Scope of patent application Remove the cover layer; and remove the exposed part of the plating seed layer. 9. The selective plating method as described in item 8 of the scope of patent application, further comprising forming a patterned first solder mask layer on the first surface, and the first solder mask layer covers at least part of the first solder mask layer. An insulation layer between lines, but the first metal layer is exposed. 10. The selective electroplating method according to item 9 of the scope of patent application, further comprising forming a patterned second solder mask layer on the second surface, and the second solder mask layer exposes the second metal. Floor. 1 1. The selective electroplating method according to item 8 of the scope of patent application, wherein the circuit substrate further includes a patterned second inter-circuit insulation layer, which is disposed on the second surface of the circuit substrate and adjacent to each other. On the second bonding pad, and the second solder mask layer covers at least a part of the second inter-circuit insulation layer. 12. The selective electroplating method according to item 8 of the scope of the patent application, wherein the method of removing the plating seed layer includes one of etching and grinding. 1 3. A selective plating method at least includes: providing a circuit substrate having a first surface and a corresponding second surface, and the circuit substrate having at least a first bonding pad and at least a second A bonding pad and a patterned first inter-circuit insulation layer, and the first bonding pad and the second bonding pad are respectively disposed on the first surface and the second surface, and the first bonding pad is electrically connected to The second bonding pad, and the first inter-circuit insulation layer is disposed on the first surface of the circuit substrate and is adjacent to the first bonding pad; 11477T ~ 1.PTD, page 31, 1242399 6. The scope of the patent application forms a plating seed layer on the second side of the circuit substrate; a first metal layer and a second metal layer are plated on the first bonding pad, respectively And the plating seed layer; forming a patterned first cover layer and a patterned second cover layer on the first surface of the circuit substrate and the plating seed layer, respectively, and the first The mask layer is exposed to the first metal layer, and the second mask layer is to cover a portion of the second metal layer above the second bonding pad; removing the exposed portion of the second metal layer A portion; removing an exposed portion of the plating seed layer; and removing the mask layer. 14. The selective electroplating method described in item 13 of the scope of patent application, further comprising forming a patterned first solder mask layer on the first surface, and the first solder mask layer covers at least a part of the The first inter-line insulation layer, but the first metal layer is exposed. 15. The selective plating method as described in item 14 of the scope of patent application, further comprising forming a patterned second solder mask layer on the second surface, and the second solder mask layer exposes the second Metal layer. 16. The selective plating method as described in item 13 of the scope of patent application, wherein the circuit substrate further includes a patterned second inter-circuit insulation layer, which is disposed on the second surface of the circuit substrate and is Adjacent to the second bonding pad, and the second solder mask layer covers at least a part of the second inter-circuit insulation layer. 1 7. The selective plating method as described in item 13 of the scope of patent application, which 11477T ~ 1.PTD Page 32 1242399 6. The scope of the patent application for removing the plating seed layer includes one of etching and grinding. 1 8. A selective plating method, including at least: providing a circuit substrate having a first surface and a corresponding second surface, and the circuit substrate having at least a first bonding pad and at least a second A bonding pad and a patterned first inter-circuit insulation layer, wherein the first bonding pad and the second bonding pad are respectively disposed on the first surface and the second surface, and the first bonding pad is electrically connected To the second bonding pad, and the first inter-circuit insulation layer is disposed on the first surface of the circuit substrate and adjacent to the first bonding pad; forming a plating seed layer on the second substrate of the circuit substrate A first metal layer and a second metal layer are plated on the first bonding pad and the second bonding pad, respectively; and the exposed portion of the plating seed layer is removed. 19. The selective plating method as described in item 18 of the scope of patent application, wherein the circuit substrate further comprises a patterned second inter-circuit insulation layer, which is disposed on the second side of the circuit substrate and is opposite to Adjacent to the second bonding pad, and the second solder mask layer covers at least a part of the second inter-circuit insulation layer. 20. The selective plating method as described in item 18 of the scope of patent application, wherein the method of removing the plating seed layer includes one of etching and grinding. 11477T ~ 1.PTD Page 33