TWI393229B - Packing substrate and method for manufacturing the same - Google Patents

Description

Packaging substrate manufacturing method and structure thereof

The invention relates to a package substrate and a manufacturing method thereof, in particular to a package substrate suitable for simplifying a process, shortening a signal transmission path and reducing noise interference, and a manufacturing method thereof.

With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional, high-performance research and development. In order to meet the packaging requirements of semiconductor package high integration and miniaturization, most active and passive components and circuit-connected circuit boards are also gradually evolved from single-layer boards to multi-layer boards to make them limited. In space, the interlayer area is used to expand the available wiring area on the board to meet the high circuit density integrated circuit requirements.

At present, a semiconductor package structure is generally obtained by bonding a semiconductor wafer to a top surface of a substrate, performing wire bonding, or electrically connecting the semiconductor wafer to a substrate by flip chip bonding, and then implanting the substrate on the back surface of the substrate. A solder ball is electrically connected to an external electronic component such as a printed circuit board.

In the manufacturing method of the conventional package substrate, the carrier board is started from a core substrate, and the inner layer structure is completed through a process such as drilling, metal plating, plugging, and line forming. The multilayer carrier is then completed via a build-up process, as shown in Figures 1A through 1E, which is a method of making a build-up multilayer. As shown in FIG. 1A, first, a core substrate 11 is formed which is composed of a core layer 111 having a predetermined thickness and a wiring layer 112 formed on the surface of the core layer 111. At the same time, a plurality of plated vias (PTH) 113 are formed in the core layer 111. Thereby, the circuit layer 112 of the core layer 111 opposite to the two surfaces is electrically connected. As shown in FIG. 1B, the core substrate 11 is subjected to a build-up process. First, a dielectric layer 12 is disposed on the surface of the core substrate 11. The dielectric layer 12 is provided with a plurality of openings to expose the circuit layer 112 as electricity. The connection pad 112a portion. As shown in FIG. 1C, a seed layer 14 is formed on the exposed surface of the dielectric layer 12 by electroless plating or sputtering, and a patterned resist layer 15 is formed on the seed layer 14, and the resist layer is formed. A plurality of openings 150 are formed to expose the electrical connection pads 112a. As shown in FIG. 1D, a patterned wiring layer 16 and a conductive via hole 16a are formed in the barrier opening 150 by electroplating, and the wiring layer 16 is electrically connected to the conductive via hole 16a. The pad 112a is then connected, and then the seed layer covered by the resist layer and the resist layer is removed to form a first line build-up structure 10a. As shown in FIG. 1E, similarly, the second line build-up structure 10b is repeatedly formed on the outermost surface of the first line build-up structure 10a by the same method to gradually form a multi-layer carrier 10.

However, the above process starts from a core substrate, and the inner layer structure is completed through a process such as drilling, metal plating, plugging, and line forming, and then the multilayer carrier is completed through the build-up process, thereby having the disadvantages of complicated process steps. In addition, since the core substrate needs to be formed into a plated through hole (PTH) through drilling, electroplating, etc., the aperture and hole depth of the plated through hole are much larger than the conductive blind hole, so the signal transmission path is too long, and crosstalk is easily generated ( Cross-talk, noise, or signal attenuation; in addition, the portion of the plated via that extends beyond the surface of the dielectric layer also occupies the wiring space. Therefore, the above problems are indeed urgent issues that the industry has to solve.

In view of the disadvantages of the prior art, the main object of the present invention is to provide a package substrate structure and method for simplifying the process, shortening the signal transmission path, reducing noise interference, and increasing the wiring density.

In order to achieve the above, the present invention provides a package substrate comprising: a first dielectric layer having a plurality of patterned opening regions penetrating through the first dielectric layer; a first circuit layer disposed at the first In the patterned opening regions of the dielectric layer, and the first circuit layer is flush with the opposite surfaces of the first dielectric layer; and a line build-up structure is disposed on the first circuit layer and the first dielectric layer The two opposite surfaces of the layer, wherein the line build-up structure has a plurality of conductive blind holes electrically connected to the first circuit layer, and the circuit build-up structure surface is formed with a plurality of electrical connection pads. Accordingly, the two side lines can be electrically connected by the first circuit layer and the conductive blind holes without separately forming the plating via holes, thereby solving the problem that the plating via holes extend over the surface of the dielectric layer to occupy the wiring space; The signal transmission path of the structure is short, which can effectively reduce noise interference, thereby improving electrical functions.

The present invention also provides a method for fabricating a package substrate, comprising: providing a support plate; forming a first dielectric layer on a surface of the support plate; and forming a plurality of patterned opening regions penetrating through the first dielectric layer; Plating a first wiring layer in the patterned opening regions and aligning the first wiring layer with the surface of the first dielectric layer; removing the support plate; and forming a line build-up structure on the first circuit layer The two opposite surfaces of the first dielectric layer, wherein the circuit build-up structure has a plurality of conductive blind holes electrically connected to the first circuit layer, and the circuit build-up structure surface is formed with a plurality of electrical connection pads. Accordingly, the method for fabricating a package substrate provided by the present invention can effectively simplify the manufacturing process and improve the complexity of the conventional packaging substrate manufacturing process.

In the package substrate of the present invention and the method of fabricating the same, the line build-up structure may be one or more layers, and may include at least one second dielectric layer, at least one second circuit layer, and a plurality of conductive blind vias. In detail, the line build-up structure may include at least one second dielectric layer, at least one second circuit layer stacked on the second dielectric layer, and a plurality of conductive blind holes formed in the second dielectric layer. . Alternatively, the line build-up structure may include at least one second dielectric layer, at least one second circuit layer embedded in the second dielectric layer, and the conductive via holes formed in the second dielectric layer. The exposed surface of the second circuit layer is flush with the surface of the second dielectric layer.

In the package substrate of the present invention and the method of fabricating the same, the first dielectric layer may be a photosensitive dielectric material, and the patterned opening region of the first dielectric layer may be formed by patterning by exposure and development; or The first dielectric layer is a non-photosensitive dielectric material, and the patterned open area of the first dielectric layer can be formed using mechanical or laser drilling.

In the package substrate of the present invention and the method for fabricating the same, the opposite surfaces of the first circuit layer and the first dielectric layer may be roughened to be roughened to increase the first circuit layer and the first dielectric layer. The bonding force between the second dielectric layers. Wherein, the opposite surfaces of the first circuit layer and the first dielectric layer can be roughened by micro-etching, such as chemical etching, plasma etching, and the like.

The type of the support plate of the present invention is not limited, and may be a conductive plate or an insulating plate having a conductive layer on the surface. Accordingly, the conductive layer of the conductive plate and the insulating plate can be used as a current conduction path required for plating the first circuit layer. . In addition, the material of the first circuit layer, the second circuit layer and the conductive blind hole of the present invention may be selected from the group consisting of copper, tin, nickel, chromium, titanium, lead, gold and copper-chromium alloy. Among them, copper is preferred.

The package substrate and the method for manufacturing the same according to the present invention include a solder mask layer formed on the surface of the circuit build-up structure, wherein the solder resist layer has a plurality of solder mask opening holes to expose the power of the line build-up structure Sex connection pad. In addition, the solder pads or solder bumps may be attached to the electrical connection pads to electrically connect to the electrode pads or other electronic components of the wafer.

In summary, the through-hole-free structure provided by the present invention can improve the wiring density, shorten the signal transmission path, reduce the thickness of the package substrate, reduce noise interference, and simplify the process flow; meanwhile, the present invention forms a symmetrical line build-up structure. It is necessary to avoid the problem of bending the board.

The embodiments of the present invention are described by way of specific examples, and those skilled in the art can readily appreciate the other advantages and advantages of the present invention. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes can be made without departing from the spirit and scope of the invention.

The drawings in the embodiments of the present invention are simplified schematic diagrams. However, the drawings only show the components related to the present invention, and the components shown therein are not in actual implementation, and the actual number of components in the actual implementation is a selective design and the component layout. The pattern may be more complicated.

Example 1

2A to 2E are cross-sectional views showing a process of fabricating a package substrate according to a preferred embodiment of the present invention.

First, as shown in FIG. 2A, a support plate 21 is provided. In the embodiment, the support plate 21 is an insulating plate having a conductive layer 211 on the surface, wherein the conductive layer 211 is used as a current conduction required for a subsequent electroplating process. The path is used. Next, a first dielectric layer 22 is formed on the surface of the conductive layer 211, and a plurality of patterned opening regions 221 are formed through the first dielectric layer 22. In the embodiment, the first dielectric layer 22 is a photosensitive dielectric material, and the patterned opening regions 221 are formed by patterning by exposure and development.

Subsequently, as shown in FIG. 2B, the first wiring layer 23 is plated in the patterned opening regions 221, and the first wiring layer 23 is flush with the surface of the first dielectric layer 22. In this embodiment, the material of the first circuit layer 23 can be selected from one group consisting of copper, tin, nickel, chromium, titanium, lead, gold, and copper-chromium alloy, in this embodiment. Use copper.

As shown in FIG. 2C, the support plate having the conductive layer is removed, and the roughening treatment of the opposite surfaces of the first circuit layer 23 and the first dielectric layer 22 is performed in a microetching manner.

Next, as shown in FIG. 2D, a line build-up structure 24 is formed by a line build-up technique on the opposite surfaces of the first circuit layer 23 and the first dielectric layer 22. The circuit build-up structure 24 includes: a second dielectric layer 241; and a second circuit layer 242 stacked on the second dielectric layer 241, which is exposed and developed by a resist layer (not shown). The method is further formed by electroplating; and the conductive blind vias 243 are formed in the second dielectric layer 241 by laser drilling to form blind vias (not shown), and simultaneously with the second wiring layer 242 by electroplating. form. Here, the conductive blind vias 243 of the line build-up structure 24 are electrically connected to the first circuit layer 23, and the surface of the circuit build-up structure 24 is also formed with a plurality of electrical connection pads 242a. In addition, the material used in the second circuit layer 242 and the conductive blind via 243 may be one selected from the group consisting of copper, tin, nickel, chromium, titanium, lead, gold, and copper-chromium alloy. The example uses copper.

Finally, as shown in FIG. 2E, a solder resist layer 25 is formed on the surface of the line build-up structure 24, and the solder resist layer 25 has a plurality of solder resist openings 251 to expose the electrical connection pads 242a of the line build-up structure 24. . The solder pads 242a are soldered to solder balls (not shown) or solder bumps (not shown) for electrically connecting to the electrode pads of the wafer or other electronic components.

Accordingly, the package substrate of the present invention, as shown in FIG. 2E, includes: a first dielectric layer 22 having a plurality of patterned opening regions 221 extending through the first dielectric layer 22; a first wiring layer 23 The first circuit layer 23 is flush with the opposite surfaces of the first dielectric layer 22; a line build-up structure 24 is disposed in the patterned opening regions 221 of the first dielectric layer 22, The second layer is formed on the opposite surface of the first circuit layer 23 and the first dielectric layer 22, wherein the line layering structure 24 includes at least one second dielectric layer 241, at least one of which is placed on the second layer. a second circuit layer 242 on the electrical layer 241, and the conductive vias 243 formed in the second dielectric layer 241, and the conductive vias 243 are electrically connected to the first circuit layer 23, and A plurality of electrical connection pads 242a are formed on the surface of the line build-up structure 24; and a solder resist layer 25 is disposed on the surface of the line build-up structure 24, and the solder resist layer 25 has a plurality of solder resist openings 251. The electrical connection pads 242a of the line build-up structure 24 are exposed.

Example 2

3A and 3E are cross-sectional views showing a process of fabricating a package substrate according to another preferred embodiment of the present invention.

First, as shown in FIG. 3A, a support plate 31 is provided. In this embodiment, the support plate 31 is a conductive plate. Next, a first dielectric layer 32 is formed on the surface of the support plate 31, and a plurality of patterned opening regions 321 extending through the first dielectric layer 32 are formed. In the embodiment, the first dielectric layer 32 is a non-photosensitive dielectric material, and the patterned opening regions 321 are formed by laser drilling.

Subsequently, as shown in FIG. 3B, the first wiring layer 33 is plated in the patterned opening regions 321, and the first wiring layer 33 is flush with the surface of the first dielectric layer 32. In this embodiment, the material that can be used for the first circuit layer 33 is selected from the group consisting of copper, tin, nickel, chromium, titanium, lead, gold, and copper-chromium alloy. Use copper.

As shown in FIG. 3C, the support plate is removed, and the roughening treatment of the opposite surfaces of the first wiring layer 33 and the first dielectric layer 32 is performed in a microetching manner.

Next, as shown in FIG. 3D, a line build-up structure 34 is formed by a build-up technique on the opposite surfaces of the first circuit layer 33 and the first dielectric layer 32. The circuit build-up structure 34 includes: a second dielectric layer 341; a second circuit layer 342 embedded in the second dielectric layer 341, which is formed in the second dielectric layer 341 to form a plurality of circuit openings (not shown) And then plating, and forming the plated metal by brushing or etching; and a conductive blind hole 343 which is formed in the second dielectric layer 341 to form a blind hole by laser drilling ( The figure is not shown) and is formed by electroplating simultaneously with the second wiring layer 342. Here, the conductive via 343 of the line build-up structure 34 is electrically connected to the first circuit layer 33, and the surface of the line build-up structure 34 is also formed with a plurality of electrical connection pads 342a. In addition, the material used in the second circuit layer 342 and the conductive blind via 343 may be one selected from the group consisting of copper, tin, nickel, chromium, titanium, lead, gold, and copper-chromium alloy. The example uses copper.

Finally, as shown in FIG. 3E, a solder resist layer 35 is formed on the surface of the line build-up structure 34, and the solder resist layer 35 has a plurality of solder resist openings 351 to expose the electrical connection pads 342a of the line build-up structure 34. . The solder pads 342a can be soldered to solder balls (not shown) or solder bumps (not shown) to electrically connect to the electrode pads or other electronic components of the wafer.

Accordingly, the package substrate of the present invention, as shown in FIG. 3E, includes: a first dielectric layer 32 having a plurality of patterned opening regions 321 extending through the first dielectric layer 32; a first circuit layer 33 The first circuit layer 33 is flush with the opposite surfaces of the first dielectric layer 32; a line build-up structure 34 is disposed in the patterned opening regions 321 of the first dielectric layer 32. The circuit is formed on the opposite surface of the first circuit layer 33 and the first dielectric layer 32, wherein the circuit build-up structure 34 includes at least one second dielectric layer 341, at least one embedded in the second dielectric layer. a second circuit layer 342 of the electrical layer 341 and the conductive vias 343 formed in the second dielectric layer 341, wherein the exposed surface of the second wiring layer 342 and the second dielectric layer 341 The conductive blind vias 343 are electrically connected to the first circuit layer 33, and a plurality of electrical connection pads 341a are formed on the surface of the circuit build-up structure 34; and a solder resist layer 35 is disposed on the surface The line build-up structure 34 has a surface, and the solder resist layer 35 has a plurality of solder mask opening 351 to expose the line build-up structure 3 4 of the electrical connection pads 342a.

In summary, the electroless plating via structure provided by the present invention can improve the wiring density, shorten the signal transmission path, reduce the thickness of the package substrate, reduce noise interference, and simplify the process flow; meanwhile, the present invention forms a symmetrical line buildup structure. To avoid the problem of plate bending.

The above-mentioned embodiments are merely examples for convenience of description, and the scope of the claims is intended to be limited to the above embodiments.

10. . . Multi-layer carrier

10a. . . First line build-up structure

10b. . . Second line buildup structure

11. . . Core substrate

111. . . Core layer

112,16. . . Circuit layer

112a, 242a, 342a. . . Electrical connection pad

113. . . Plating via

12. . . Dielectric layer

14. . . Seed layer

15. . . Resistance layer

150. . . Opening

16a, 243, 343. . . Conductive blind hole

21,31. . . Support plate

211. . . Conductive layer

22,32. . . First dielectric layer

221,321. . . Patterned open area

23,33. . . First circuit layer

24,34. . . Line buildup structure

241,341. . . Second dielectric layer

242,342. . . Second circuit layer

25,35. . . Solder mask

251,351. . . Solder mask opening

1A to 1E are cross-sectional views showing a manufacturing process of a package substrate.

2A to 2E are cross-sectional views showing a manufacturing process of a package substrate according to a preferred embodiment of the present invention.

3A to 3E are cross-sectional views showing a process of fabricating a package substrate according to another preferred embodiment of the present invention.

twenty two. . . First dielectric layer

221. . . Patterned open area

twenty three. . . First circuit layer

twenty four. . . Line buildup structure

241. . . Second dielectric layer

242. . . Second circuit layer

242a. . . Electrical connection pad

243. . . Conductive blind hole

25. . . Solder mask

251. . . Solder mask opening

Claims (21)

A method for fabricating a package substrate, comprising: providing a support plate; forming a first dielectric layer on a surface of the support plate; and forming a plurality of patterned opening regions penetrating the first dielectric layer; a wiring layer in the patterned opening regions, and the first wiring layer is flush with a surface of the first dielectric layer; removing the support plate; and forming a line build-up structure on the first circuit layer And two opposite surfaces of the first dielectric layer, wherein the circuit build-up structure has a plurality of conductive blind holes electrically connected to the first circuit layer, and the circuit of the circuit build-up structure is formed with a plurality of electrical connections pad. The manufacturing method of claim 1, wherein the circuit build-up structure comprises at least one second dielectric layer, at least one second circuit layer stacked on the second dielectric layer, and formed on The conductive blind holes in the second dielectric layer. The manufacturing method of claim 1, wherein the circuit build-up structure comprises at least one second dielectric layer, at least one second circuit layer embedded in the second dielectric layer, and formed on the The conductive vias in the second dielectric layer, wherein the exposed surface of the second circuit layer is flush with the surface of the second dielectric layer. The manufacturing method of claim 1, wherein the line build-up structure is one or more layers. The manufacturing method of claim 1, wherein the support plate is a conductive plate. The manufacturing method of claim 1, wherein the support plate is an insulating plate having a conductive layer on the surface, and the first dielectric layer is formed on a surface of the conductive layer. The manufacturing method of claim 1, wherein the opposite surfaces of the first circuit layer and the first dielectric layer are roughened. The manufacturing method of claim 7, wherein the opposite surfaces of the first circuit layer and the first dielectric layer are roughened by microetching. The manufacturing method of claim 1, further comprising: forming a solder resist layer on the surface of the line build-up structure, wherein the solder resist layer has a plurality of solder mask openings, to reveal the line increase The electrical connection pads of the layer structure. A package substrate, which is obtained according to any one of claims 1 to 9, wherein the package substrate comprises: a first dielectric layer; a first circuit layer; and a line build-up structure; a plurality of conductive blind holes; and a plurality of electrical connection pads. The package substrate of claim 10, wherein the circuit build-up structure comprises at least one second dielectric layer, at least one of which is placed on the first a second circuit layer on the second dielectric layer and the conductive vias formed in the second dielectric layer. The package substrate of claim 10, wherein the circuit build-up structure comprises at least one second dielectric layer, at least one second circuit layer embedded in the second dielectric layer, and formed on the The conductive vias in the second dielectric layer, wherein the exposed surface of the second circuit layer is flush with the surface of the second dielectric layer. The package substrate of claim 10, wherein the line build-up structure is one or more layers. The package substrate according to claim 10, further comprising a solder resist layer disposed on a surface of the line build-up structure, wherein the solder resist layer has a plurality of solder mask openings, to reveal the line increase The electrical connection pads of the layer structure. The package substrate of claim 10, wherein the opposite surfaces of the first circuit layer and the first dielectric layer are roughened surfaces. A package substrate comprising: a first dielectric layer having a first surface, a second surface, and a plurality of patterned opening regions extending through the first dielectric layer; a first circuit layer disposed on In the patterned open areas of the first dielectric layer, the first circuit layer is flush with the first surface and the second surface of the first dielectric layer; and a line build-up structure is Arranging on two opposite surfaces of the first circuit layer and the first dielectric layer, wherein the line build-up structure has a plurality of The conductive blind vias are electrically connected to the first circuit layer, and the surface of the circuit build-up structure is formed with a plurality of electrical connection pads. The package substrate of claim 16, wherein the circuit build-up structure comprises at least one second dielectric layer, at least one second circuit layer stacked on the second dielectric layer, and formed on The conductive blind holes in the second dielectric layer. The package substrate of claim 16, wherein the circuit build-up structure comprises at least one second dielectric layer, at least one second circuit layer embedded in the second dielectric layer, and formed thereon The conductive vias in the second dielectric layer, wherein the exposed surface of the second circuit layer is flush with the surface of the second dielectric layer. The package substrate of claim 16, wherein the line build-up structure is one or more layers. The package substrate according to claim 16, further comprising a solder resist layer disposed on a surface of the line build-up structure, wherein the solder resist layer has a plurality of solder mask openings, to reveal the line increase The electrical connection pads of the layer structure. The package substrate of claim 16, wherein the opposite surfaces of the first circuit layer and the first dielectric layer are roughened surfaces.