CN112118682A - Method for forming copper layer on circuit board and circuit board with sputtered copper layer - Google Patents
Method for forming copper layer on circuit board and circuit board with sputtered copper layer Download PDFInfo
- Publication number
- CN112118682A CN112118682A CN201910540708.9A CN201910540708A CN112118682A CN 112118682 A CN112118682 A CN 112118682A CN 201910540708 A CN201910540708 A CN 201910540708A CN 112118682 A CN112118682 A CN 112118682A
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- Prior art keywords
- circuit board
- copper layer
- plated
- sputtered
- conductive area
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
- H05K3/16—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation by cathodic sputtering
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
The invention provides a method for forming a copper layer on a circuit board, which comprises the following steps: providing a circuit board structure, wherein the circuit board structure is provided with a surface to be plated, and the surface to be plated is provided with a conductive area and a non-conductive area; and sputtering the surface to be plated to form a sputtered copper layer on the conductive area and the non-conductive area of the surface to be plated. The invention can replace the chemical plating process in the prior art circuit board process.
Description
Technical Field
The present invention relates to a circuit board technology, and more particularly, to a copper layer of a circuit board and a method for fabricating the same.
Background
In the conventional circuit board manufacturing process, a copper layer is generally required to be formed on a substrate by chemical plating or electroplating, and the formed copper layer can be further manufactured into a patterned circuit. Compared with electroplating, electroless plating has the advantage that a thin layer of copper can be plated on the surface of a non-conductor after appropriate surface treatment, which greatly improves the freedom of circuit arrangement and is widely applied to circuit board manufacturing.
However, electroless copper plating has disadvantages in that the plating solution composition is complicated, the process difficulty is high, and the cost of electroless copper plating is high.
Disclosure of Invention
It is therefore a primary object of the present invention to provide an alternative method and structure for forming a copper layer on a circuit board.
In order to achieve the above and other objects, the present invention provides a method of forming a copper layer on a circuit board, comprising:
providing a circuit board structure, wherein the circuit board structure is provided with a surface to be plated, and the surface to be plated is provided with a conductive area and a non-conductive area; and
and sputtering the surface to be plated to form a sputtered copper layer on the conductive area and the non-conductive area of the surface to be plated.
In order to achieve the above and other objects, the present invention provides a circuit board with a sputtered copper layer, which includes a circuit board structure and a sputtered copper layer, wherein the circuit board structure has a surface to be plated, the surface to be plated has a conductive region and a non-conductive region, and the sputtered copper layer is formed on the conductive region and the non-conductive region of the surface to be plated.
Through the technology, the copper ions can be deposited on the surface to be plated in a physical mode, the diffraction performance of the copper ions is good, and the surface to be plated with a complex shape can be sputtered, so that copper layers are formed in the conductive area and the non-conductive area of the surface to be plated, the chemical plating process in the prior art circuit board process can be replaced, the use of plating solution is reduced, and the cost is reduced.
Other effects and embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 to 7 are schematic process diagrams of one embodiment of the present invention.
Description of the symbols
1 Circuit Board Structure 11 to-be-plated surface
111 conductive region 112 nonconductive region
20 sputtering copper layer 30 electroplating copper layer
40 photoresist layer
Detailed Description
The invention discloses a method for forming a copper layer on a circuit board and the circuit board with a sputtering copper layer.
The following describes a process according to one embodiment of the present invention with reference to fig. 1 to 7.
Referring to fig. 1, first, a circuit board structure 1 is provided, the circuit board structure 1 has a surface to be plated 11, the surface to be plated 11 has conductive regions 111 and non-conductive regions 112, the number of the conductive regions and the non-conductive regions 112 depends on the circuit design, and in the circuit board structure with high complexity of circuit design, the surface to be plated 11 may have a plurality of conductive regions 111 and non-conductive regions 112. It will be appreciated that as the circuit complexity of the circuit board structure increases, the surface to be plated is also generally rougher, and the heights of the conductive and non-conductive regions are not necessarily the same. The conductive region 111 is, for example, an underlying circuit layer, such as a copper underlying circuit copper layer, of a circuit board structure that has been pre-fabricated with a portion of circuitry. The non-conductive region 112 is, for example, a dielectric layer, a solder mask layer or a packaging adhesive in a circuit board structure, such as polyimide, epoxy resin or other resins commonly used in circuit board structures. The circuit board structure illustrated in this embodiment is a single-sided single-layer board, and in other possible embodiments, the circuit board structure can also be a double-sided board or a multi-layer board.
Referring to fig. 2, the sputtering process is performed on the surface to be plated 11, so as to form a sputtered copper layer 20 on the conductive area 111 and the non-conductive area 112 of the surface to be plated 11, the sputtering process utilizes the principle of physical vapor deposition, and utilizes the arc discharge technology of low pressure and large current under vacuum condition, the copper atoms in the copper target are bombarded by the plasma body through gas discharge and leave the copper target, the sputtered copper atoms are deposited on the surface to be plated 11 by the acceleration action of electrons, and because the sputtered copper atoms have good diffraction capability, a layer of thin copper can be deposited on the irregular surface of the surface to be plated 11, so that the conductive area 111 and the non-conductive area 112 can both form the sputtered copper layer 20.
Referring to fig. 3, the sputtered copper layer 20 is electroplated to form an electroplated copper layer 30 on the sputtered copper layer 20, wherein the electroplating process is implemented by supplementing a layer of copper on the sputtered copper layer 20 by using the principle of electrolysis to increase the thickness of the overall copper layer.
Then, the sputtered copper layer 20 and the electroplated copper layer 30 may be further patterned to form a patterned circuit. The patterning process is exemplarily represented by fig. 4 to 7.
First, referring to fig. 4, a photoresist layer 40 is formed on the electroplated copper layer 30, and the photoresist layer 40 is selectively irradiated and exposed.
Then, as shown in fig. 5, the partial photoresist layer 40 is selectively removed by a developing solution to expose the underlying electroplated copper layer 30.
Then, as shown in fig. 6, the exposed electroplated copper layer 30 and the underlying sputtered copper layer 20 are selectively removed by the etching solution, so that the sputtered copper layer 20 and the electroplated copper layer 30 are patterned.
Finally, as shown in fig. 7, the photoresist layer is removed, and the manufactured circuit board includes the circuit board structure 1, and the patterned sputtered copper layer 20 and the electroplated copper layer 30, and finally, the sputtered copper layer 20 is formed on the partial surfaces of the conductive region 111 and the non-conductive region 112 on the surface 11 to be plated of the circuit board structure 1, and the electroplated copper layer 30 covers the sputtered copper layer 20. The circuit board shown in fig. 7 may be further subjected to additional layer formation, solder mask treatment, surface treatment and/or other post-treatments conventionally used in circuit board manufacturing processes according to the desired circuit design.
Through the technology, the copper ions can be deposited on the surface to be plated in a physical mode, the diffraction performance of the copper ions is good, and the surface to be plated with a complex shape can be sputtered, so that copper layers are formed in the conductive area and the non-conductive area of the surface to be plated, the chemical plating process in the prior art circuit board process can be replaced, the use of plating solution is reduced, and the cost is reduced.
The above-described embodiments and/or implementations are only for illustrating the preferred embodiments and/or implementations of the present technology, and are not intended to limit the implementations of the present technology in any way, and those skilled in the art can make many modifications or changes without departing from the scope of the technology disclosed in the present disclosure, but should be construed as technology or implementations that are substantially the same as the present technology.
Claims (7)
1. A method of forming a copper layer on a circuit board, comprising:
providing a circuit board structure, wherein the circuit board structure is provided with a surface to be plated, and the surface to be plated is provided with a conductive area and a non-conductive area; and
and sputtering the surface to be plated to form a sputtered copper layer on the conductive area and the non-conductive area of the surface to be plated.
2. The method of forming a copper layer on a circuit board of claim 1, further comprising: electroplating the sputtered copper layer to form an electroplated copper layer on the sputtered copper layer.
3. The method of forming a copper layer on a circuit board of claim 2, further comprising: and carrying out imaging treatment on the sputtered copper layer and the electroplated copper layer.
4. A method for forming a copper layer on a circuit board according to any one of claims 1 to 3, wherein the non-conductive region is made of polyimide.
5. The method of forming a copper layer on a circuit board according to any one of claims 1 to 3, wherein the non-conductive area is made of resin.
6. A circuit board having a sputtered copper layer, comprising:
the circuit board structure is provided with a surface to be plated, and the surface to be plated is provided with a conductive area and a non-conductive area; and
and a copper sputtering layer formed on the conductive region and the non-conductive region of the surface to be plated.
7. The circuit board of claim 6, further comprising an electroplated copper layer formed on said sputtered copper layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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CN201910540708.9A CN112118682A (en) | 2019-06-21 | 2019-06-21 | Method for forming copper layer on circuit board and circuit board with sputtered copper layer |
Applications Claiming Priority (1)
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CN201910540708.9A CN112118682A (en) | 2019-06-21 | 2019-06-21 | Method for forming copper layer on circuit board and circuit board with sputtered copper layer |
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CN112118682A true CN112118682A (en) | 2020-12-22 |
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CN201910540708.9A Pending CN112118682A (en) | 2019-06-21 | 2019-06-21 | Method for forming copper layer on circuit board and circuit board with sputtered copper layer |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114427077A (en) * | 2021-12-23 | 2022-05-03 | 青岛歌尔智能传感器有限公司 | Selective sputtering method and electronic product thereof |
Citations (5)
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CN1678167A (en) * | 2004-03-31 | 2005-10-05 | 全懋精密科技股份有限公司 | Multi-layer circuit board and mfg. method |
CN101364586A (en) * | 2007-08-10 | 2009-02-11 | 全懋精密科技股份有限公司 | Construction for packaging substrate and preparation thereof |
CN101409238A (en) * | 2007-10-11 | 2009-04-15 | 全懋精密科技股份有限公司 | Method for preparing seedless layer package substrate |
TW200926372A (en) * | 2007-12-04 | 2009-06-16 | Phoenix Prec Technology Corp | Packing substrate and method for manufacturing the same |
CN103974549A (en) * | 2014-05-26 | 2014-08-06 | 深圳市智武科技有限公司 | Manufacturing method for circuit board line |
-
2019
- 2019-06-21 CN CN201910540708.9A patent/CN112118682A/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1678167A (en) * | 2004-03-31 | 2005-10-05 | 全懋精密科技股份有限公司 | Multi-layer circuit board and mfg. method |
CN101364586A (en) * | 2007-08-10 | 2009-02-11 | 全懋精密科技股份有限公司 | Construction for packaging substrate and preparation thereof |
CN101409238A (en) * | 2007-10-11 | 2009-04-15 | 全懋精密科技股份有限公司 | Method for preparing seedless layer package substrate |
TW200926372A (en) * | 2007-12-04 | 2009-06-16 | Phoenix Prec Technology Corp | Packing substrate and method for manufacturing the same |
CN103974549A (en) * | 2014-05-26 | 2014-08-06 | 深圳市智武科技有限公司 | Manufacturing method for circuit board line |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114427077A (en) * | 2021-12-23 | 2022-05-03 | 青岛歌尔智能传感器有限公司 | Selective sputtering method and electronic product thereof |
CN114427077B (en) * | 2021-12-23 | 2023-08-15 | 青岛歌尔智能传感器有限公司 | Selective sputtering method and electronic product thereof |
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