CN101409238A - Method for preparing seedless layer package substrate - Google Patents
Method for preparing seedless layer package substrate Download PDFInfo
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- CN101409238A CN101409238A CN 200710180728 CN200710180728A CN101409238A CN 101409238 A CN101409238 A CN 101409238A CN 200710180728 CN200710180728 CN 200710180728 CN 200710180728 A CN200710180728 A CN 200710180728A CN 101409238 A CN101409238 A CN 101409238A
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- H01—ELECTRIC ELEMENTS
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Abstract
The invention relates to a method for manufacturing a package substrate without a core layer and a conductive structure of the package substrate. The structure manufactured by the method comprises a storey-adding structure which is provided with a first solder mask layer and a second solder mask layer, wherein, a plurality of openings are formed at the first solder mask layer and the second solder mask layer to expose an electric connection gasket of the storey-adding structure, and the structure also comprises a plurality of solder projections formed on the electric connection gasket and a solder layer. Therefore, the package substrate without the core layer manufactured by the invention can provide a shorter conductive path, improves the wiring density of a circuit and reduces the manufacturing procedures, and the thickness of a whole product is reduced to achieve the light, thin and small function.
Description
Technical field
The present invention relates to a kind of method for making of seedless layer package substrate and a kind of conductive structure of this base plate for packaging, this method for making refers to a kind of manufacture method that is applicable to no through-hole structure, can improves the seedless layer package substrate of line layout density and minimizing making flow process especially.
Background technology
Flourish along with electronic industry, electronic product also progresses into multi-functional, high performance R﹠D direction.For satisfying the encapsulation requirement of the high integration of semiconductor package part (Integration) and microminiaturized (Miniaturization), offer the base plate for packaging that a plurality of main passive devices and circuit connect usefulness, also develop into multi-layer sheet by lamina gradually, so that under limited space, enlarge available wiring area on the base plate for packaging by interlayer interconnection technique (Interlayer connection), to cooperate integrated circuit (Integrated circuit) demand of high electron density.
The technology of general semiconductor device, at first produce the chip support plate that is applicable to semiconductor device by the chip support plate manufacturer, as substrate or lead frame, afterwards, these chip support plates being transferred to the semiconductor packages dealer puts crystalline substance, pressing mold and plants technology such as ball again, at last, can finish the semiconductor device of the required electric function of client.
The conventional semiconductor packages structure is that the semiconductor chip back side is sticked in substrate top surface in addition, engaging (wire bonding) mode with routing encapsulates, or semiconductor chip acting surface and substrate top surface encapsulated in chip bonding (Flip chip) mode, plant with the tin ball to electrically connect in the back side of substrate again.So, though can reach the purpose of high pin number, but when high frequency more uses or during high speed operation, because of its can't provide more the short-range missile power path and more elevated track density limit to some extent.
In the method for making of base plate for packaging, generally the technology of existing support plate is begun by a core substrate,, increases a layer technology via circuit again and finishes multilager base plate to finish endothecium structure through technology such as boring, plating, consent, circuit moulding.Figure 1A to Fig. 1 E is the existing generalized section that the stratum nucleare base plate for packaging is arranged, and at first, shown in Figure 1A, prepares a core substrate 11, and core substrate 11 is by the sandwich layer 111 of a tool predetermined thickness and be formed at sandwich layer 111 lip-deep circuit layers 112 and constituted.Simultaneously, in sandwich layer 111, form a plurality of plating vias 113, can electrically connect sandwich layer 111 lip-deep circuit layers 112 thus.Then, shown in Figure 1B, core substrate 11 is implemented circuit layer reinforced structure technology, lay dielectric layers 12, on dielectric layer 12 and offer a plurality of openings 13 that are communicated to circuit layer 112 prior to core substrate 11 surfaces.Come, shown in Fig. 1 C, form a conductive layer 14 in dielectric layer 12 exposed surfaces in modes such as electroless-plating or sputters, and form a patterning resistance layer 15 on conductive layer 14, this patterning resistance layer 15 has a plurality of openings 150 to appear partially conductive layer 14.Continuation is shown in Fig. 1 D, utilization is plated on and forms a patterned circuit layer 16 and a plurality of conductive blind hole 13a in this resistance layer opening, this patterned circuit layer 16 by those conductive blind holes 13a to be electrically conducted to circuit layer 112, the etching partially conductive layer 14 that removes patterning resistance layer 15 and covered then is to form one first circuit layer reinforced structure 10a.At last, shown in Fig. 1 E, similarly, on the first circuit layer reinforced structure 10a outermost surface, use constructed step to repeat to form one second circuit layer reinforced structure 10b again, form a multilager base plate 10 products progressively to increase layer.
Yet above-mentioned prior art is begun by a sandwich layer, through forming circuit to finish a core substrate, increases layer technology to finish a multilager base plate that meets electrical design requirement via circuit in its surface again.Its result can't reduce its thickness for final multilager base plate, and is unfavorable for the microminiaturization trend of conductor package substrate.Below core substrate thin thickness to 60 μ m, the manufacturing of this multilager base plate will face harsh challenge, and it produces also seriously decline of yield.
In addition, a plurality of plating vias of the essential formation of this core substrate, its through hole must be with machine drilling, so often more than 100 μ m, compared to conductive blind hole, its through hole is with laser hole burning for its diameter, its diameter is about 50 μ m, and the technology of electroplating via as can be known is unfavorable for forming the fine rule line structure.
Therefore, how to provide a kind of package substrate construction and its method for making, satisfying short-range missile power path more and more the elevated track density of thin space is required, become the difficult problem that present industry is demanded urgently overcoming in fact.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art and defective, propose a kind of manufacture method of seedless layer package substrate and the conductive structure of this base plate for packaging,, reduce the making flow process to improve line layout density, and the thickness of monolithic article reduces, and reaches compact function.
For reaching above-mentioned purpose, the invention provides a kind of method for making of seedless layer package substrate, include following steps:
(A) provide a support plate, and form one first resistance layer, and form a plurality of first perforates, to appear partly this support plate in first resistance layer in this support plate surface;
(B) form an etching stopping layer and a first metal layer in regular turn in those first perforates, remove first resistance layer then;
(C) form a dielectric layer on this support plate and the first metal layer surface, and form a plurality of second perforates,, form one second metal level then in those second perforates to appear the first metal layer under it in this dielectric layer;
(D) on this dielectric layer and second layer on surface of metal, form one second resistance layer, and form a plurality of the 3rd perforates corresponding to second metal level, form one the 3rd metal level then in the 3rd perforate, and remove second resistance layer in second resistance layer;
(E) form a circuit layer reinforced structure in this dielectric layer and the 3rd layer on surface of metal, it comprises the 4th metal level of at least one dielectric layer, at least one patterned circuit, a plurality of conductive blind hole and a plurality of electric connection pad;
(F) remove this support plate and this etching stopping layer, to appear the first metal layer; And
(G) on this circuit layer reinforced structure surface, form one first welding resisting layer, and form a plurality of the 4th perforates to appear those electric connection pads in first welding resisting layer, and in this dielectric layer and the first metal layer surface formation one second welding resisting layer, and form a plurality of the 5th perforates in second welding resisting layer, to appear the bottom surface of the first metal layer.
Thus, the seedless layer package substrate of manufacturing of the present invention can improve line layout density, and reduce and make flow process, and the reduction of the thickness of monolithic article, can reach compact function.
In addition, above-mentioned method for making, it is in more comprising a step (H) after the step (G): form a plurality of solder projections and reach a plurality of solder layers in those the 4th perforates in those the 5th perforates.
In addition, above-mentioned method for making, it more can comprise a step (I) after step (H): form at least one metal support in the first welding resisting layer surface, to increase the rigidity of this circuit layer reinforced structure.
Moreover, above-mentioned method for making, it is in the preceding step (G1) that more can comprise of step (H): form one the 5th metal level one at least in following structure: in those the 4th perforates of first welding resisting layer and in those the 5th perforates of second welding resisting layer, with the scolder consumption of those solder projections of economization and those solder layers.
In the above-mentioned method for making, the method that forms this circuit layer reinforced structure is known by industry, so do not give unnecessary details.
For reaching above-mentioned purpose, the present invention also provides a kind of conductive structure of seedless layer package substrate, comprising:
One dielectric layer has a plurality of first perforates and a plurality of second perforate, and first perforate and second perforate be towards the relative both sides of this dielectric layer, and wherein second perforate is out of the ordinary corresponding and less than first perforate; One the first metal layer is disposed in first perforate, and with as electric connection pad, wherein the thickness of the first metal layer is less than the degree of depth of first perforate, and the first metal layer contacts with second perforate again; And one second metal level, be disposed in second perforate, with as conductive blind hole, wherein second metal level fills up second perforate, and contacts with the first metal layer in first perforate.
In the said structure, also can comprise a welding resisting layer, be disposed on this dielectric layer and the first metal layer surface, and have a plurality of perforates in this welding resisting layer that those perforates are out of the ordinary corresponding and less than first perforate.
In the said structure, also can comprise a solder layer, be disposed in those perforates of this welding resisting layer.
In the said structure, also can comprise a metal level, be disposed in those perforates of this welding resisting layer, under this solder layer, with the scolder consumption of those solder layers of economization.
In the said structure, first metal and second metal level be selected from tin, gold, nickel, chromium, titanium, silver, copper, aluminium, lead and group that above-mentioned metal becomes alloy one of them.
In the said structure, this solder layer be selected from tin, gold, nickel, chromium, titanium, silver, copper, aluminium, lead and group that above-mentioned metal becomes alloy one of them.
In the said structure, this metal level be selected from copper, aluminium, tin, nickel, chromium and group that above-mentioned metal becomes alloy one of them.
Description of drawings
Figure 1A to Fig. 1 E is the existing generalized section that the stratum nucleare base plate for packaging is arranged;
Fig. 2 A to 2Q is the generalized section of the seedless layer package substrate of a preferred embodiment of the present invention.
Symbol description among the figure
10 core substrate 10a, the first circuit layer reinforced structure
The 10b second circuit layer reinforced structure 11 core substrates
111 sandwich layers, 112 circuit layers
113 electroplate via 12 dielectric layers
13 opening 13a conductive blind holes
14 conductive layers, 15 patterning resistance layers
150 openings, 16 patterned circuit layer
201 support plates, 202 first resistance layers
202a first perforate 204 etching stopping layers
205 the first metal layers, 206 dielectric layers
206a second perforate 207 second metal levels
208 second resistance layer 208a the 3rd perforate
209 the 3rd metal levels, 210 second welding resisting layers
210a the 5th perforate 211,305 the 5th metal level
30,30 ' circuit layer reinforced structure 301 the 4th metal level
304 first welding resisting layer 304a the 4th perforate
306 solder projections, 307 metal supports
Embodiment
See also the generalized section of the seedless layer package substrate of Fig. 2 A to 2Q a preferred embodiment of the present invention.At first, shown in Fig. 2 A, provide the support plate 201 of a metal material.Then, shown in Fig. 2 B, first resistance layer 202 of 201 pressings, one high photosensitive macromolecular material on this support plate.Shown in Fig. 2 C, on first resistance layer 202, form a plurality of first perforate 202a with exposure and developing method, for another example to appear this support plate 201 under it.Then, as Fig. 2 D, and Fig. 2 E shown in, the first metal layer 205 of electroplating the etching stopping layer 204 of a nickel metal and a bronze medal metal in regular turn is in those first perforates 202a.In the present embodiment, first resistance layer 202 is a dry film photoresist layer.
See also Fig. 2 F, peel off and remove first resistance layer 202.For another example shown in Fig. 2 G, one dielectric layer 206 of pressing one ABF (Ajinomoto Build-up Film) resin material is on the surface of this support plate 201 and the first metal layer 205, and this dielectric layer 206 also forms a plurality of second perforate 206a with laser hole burning, to appear the part the first metal layer 205 under it.Then shown in Fig. 2 H, electroplate one second metal level 207 in those second perforates 206a.Continuation forms one second resistance layer 208 on the surface of this dielectric layer 206 and second metal level 207 shown in Fig. 2 I, and makes second resistance layer 208 form a plurality of the 3rd perforate 208a in the exposure imaging mode, to appear second metal level 207 under it.Shown in Fig. 2 J, electroplate one the 3rd metal level 209 in those the 3rd perforates 208a for another example.Then, shown in Fig. 2 K, remove second resistance layer 208 with exposure and visualization way.In the present embodiment, second metal level 207 and the 3rd metal level 209 are copper metal layer.
Then, shown in Fig. 2 L, form a circuit layer reinforced structure 30 on dielectric layer 206 and the 3rd metal level 209, it comprises the 4th metal level 301 and a plurality of conductive blind hole 302 of a dielectric layer 300, a patterned circuit.Wherein, the technology that forms this circuit layer reinforced structure is known by industry, so do not give unnecessary details.
Please continue to consult Fig. 2 M, in these circuit layer reinforced structure 30 tops, form two layer line road layer reinforced structures 30 ' in addition, it comprises a plurality of electric connection pads 303.Please consult Fig. 2 N again, remove this support plate 201 and this etching stopping layer 204 with etching mode.Then; shown in Fig. 2 O; first welding resisting layer 304 that applies the green lacquer material that one deck insulation protection uses is in this circuit layer reinforced structure 30 ' surface, and forms the electric connection pad 303 of a plurality of the 4th perforate 304a to appear this circuit layer reinforced structure 30 ' with exposure and developing method on first welding resisting layer 304.And second welding resisting layer 210 that applies the green lacquer material that one deck insulation protection uses forms a plurality of the 5th perforate 210a to appear the part bottom surface of this first metal layer 205 with exposure and developing method again in these dielectric layer 206 surfaces on second welding resisting layer 210.
Please consult Fig. 2 P again, the 5th metal level 305 of electroplating a bronze medal layer is in a plurality of the 4th perforate 304a of first welding resisting layer 304, and the 5th metal level 211 of electroplating a bronze medal layer is in a plurality of the 5th perforate 210a of second welding resisting layer 210.In the present embodiment, in those the 4th perforate 304a and those the 5th perforates 210a, all form the 5th metal level 305,211 after, the solder projection 306 of electroplating a tin layer more respectively is on the 5th metal level 305,211.At last, shown in Fig. 2 Q, the metal support 307 of fitting in the surface of first welding resisting layer 304 is to increase the integral rigidity of this seedless layer package substrate.
Thus, the seedless layer package substrate of present embodiment manufacturing can improve line layout density, and reduce and make flow process, and the reduction of the thickness of monolithic article, can reach compact function.
The present invention also provides a kind of conductive structure of seedless layer package substrate, shown in Fig. 2 Q, comprising:
One dielectric layer 206 has a plurality of first perforate 202a and a plurality of second perforate 206a, and the first perforate 202a and the second perforate 206a be towards the relative both sides of this dielectric layer 206, and wherein the second perforate 206a is out of the ordinary corresponding and less than the first perforate 202a; One the first metal layer 205 is disposed among the first perforate 202a, and with as electric connection pad, wherein the thickness of the first metal layer 205 is less than the degree of depth of the first perforate 202a, and the first metal layer 205 contacts with the second perforate 206a again; And one second metal level 207, be disposed among the second perforate 206a, with as conductive blind hole, wherein second metal level 207 fills up the second perforate 206a, and contacts with the first metal layer 205 among the first perforate 202a.
In the said structure, also can comprise a welding resisting layer 210, be disposed on this dielectric layer 206 and the first metal layer 205 surfaces, and have a plurality of perforate 210a in this welding resisting layer 210 that those perforates 210a is out of the ordinary corresponding and less than the first perforate 202a.
In the said structure, also can comprise a solder layer 212, be disposed among those perforates 210a of this welding resisting layer 210.
In the said structure, also can comprise a metal level 211, be disposed among those perforates 210a of this welding resisting layer 210, under this solder layer 212, with the scolder consumption of those solder layers of economization.
The foregoing description is only given an example for convenience of description, and the interest field that the present invention advocated should be as the criterion with the scope of claims certainly, but not only limits to the foregoing description.
Claims (17)
1. the method for making of a seedless layer package substrate is characterized in that, may further comprise the steps:
(A) provide a support plate, and form one first resistance layer, and form a plurality of first perforates, to appear partly this support plate in first resistance layer in this support plate surface;
(B) form an etching stopping layer and a first metal layer in regular turn in those first perforates, remove first resistance layer then;
(C) form a dielectric layer on this support plate and the first metal layer surface, and form a plurality of second perforates,, form one second metal level then in those second perforates to appear the first metal layer under it in this dielectric layer;
(D) on this dielectric layer and second layer on surface of metal, form one second resistance layer, and form a plurality of the 3rd perforates corresponding to second metal level, form one the 3rd metal level then in the 3rd perforate, and remove second resistance layer in second resistance layer;
(E) form a circuit layer reinforced structure in this dielectric layer and the 3rd layer on surface of metal, it comprises the 4th metal level of at least one dielectric layer, at least one patterned circuit, a plurality of conductive blind hole and a plurality of electric connection pad;
(F) remove this support plate and this etching stopping layer, to appear the first metal layer; And
(G) on this circuit layer reinforced structure surface, form one first welding resisting layer, and form a plurality of the 4th perforates to appear those electric connection pads in first welding resisting layer, and in this dielectric layer and the first metal layer surface formation one second welding resisting layer, and form a plurality of the 5th perforates in second welding resisting layer, to appear the bottom surface of the first metal layer.
2. method for making as claimed in claim 1, wherein, in more comprising a step (H) after the step (G): form a plurality of solder projections and in those the 4th perforates, reach a plurality of solder layers in those the 5th perforates.
3. method for making as claimed in claim 2, wherein, in the preceding step (G1) that more comprises of step (H): form one the 5th metal level one at least in following structure: in those the 4th perforates of first welding resisting layer and in those the 5th perforates of second welding resisting layer, with the scolder consumption of those solder projections of economization and those solder layers.
4. method for making as claimed in claim 2 wherein, more comprises a step (I) after step (H): form at least one metal support in the first welding resisting layer surface, to increase the rigidity of this circuit layer reinforced structure.
5. method for making as claimed in claim 1, wherein, (A) forms first perforate in first resistance layer in step, and (D) forms the 3rd perforate in second resistance layer in step, and form the 4th perforate and the 5th perforate respectively in first welding resisting layer, second welding resisting layer in step (G), all be to use method for photolithography; Forming second perforate in step (C) in this dielectric layer then is to use the laser hole burning method.
6. method for making as claimed in claim 1, wherein, this etching stopping layer and the first metal layer in step (B), second metal level in step (C), the 3rd metal level in step (D), and at the 4th metal level and the conductive blind hole of step (E), its formation method for electroplate and electroless-plating one of them.
7. method for making as claimed in claim 1, wherein, this etching stopping layer of step (B) be selected from gold, silver, tin, nickel, chromium, titanium, lead, copper, aluminium and group that above-mentioned metal becomes alloy one of them, and at the first metal layer of step (B), second metal level in step (C), at the 3rd metal level of step (D), and at the 4th metal level of step (E), be selected from copper, aluminium, tin, nickel, chromium and group that above-mentioned metal becomes alloy one of them.
8. method for making as claimed in claim 2, wherein, at the solder projection and the solder layer of step (H), be selected from tin, gold, nickel, chromium, titanium, silver, copper, aluminium, lead and group that above-mentioned metal becomes alloy one of them.
9. method for making as claimed in claim 3, wherein, at the 5th metal level of step (G1), be selected from copper, aluminium, tin, nickel, chromium and group that above-mentioned metal becomes alloy one of them.
10. method for making as claimed in claim 1, wherein, the method that removes this support plate and this etching stopping layer in step (F) is etching.
11. the conductive structure of a seedless layer package substrate is characterized in that, comprising:
One dielectric layer has a plurality of first perforates and a plurality of second perforate, and first perforate and second perforate be towards the relative both sides of this dielectric layer, and wherein second perforate is out of the ordinary corresponding and less than first perforate;
One the first metal layer is disposed in first perforate, and with as electric connection pad, wherein the thickness of the first metal layer is less than the degree of depth of first perforate, and the first metal layer contacts with second perforate again; And
One second metal level is disposed in second perforate, and with as conductive blind hole, wherein second metal level fills up second perforate, and contacts with the first metal layer in first perforate.
12. structure as claimed in claim 11 wherein, also comprises a welding resisting layer, is disposed on this dielectric layer and the first metal layer surface, and has a plurality of perforates in this welding resisting layer, those perforates are out of the ordinary corresponding and less than first perforate.
13. structure as claimed in claim 12 wherein, also comprises a solder layer, is disposed in those perforates of this welding resisting layer.
14. structure as claimed in claim 13 wherein, also comprises a metal level, is disposed in those perforates of this welding resisting layer, under this solder layer, with the scolder consumption of those solder layers of economization.
15. structure as claimed in claim 11, wherein, first metal and second metal level be selected from tin, gold, nickel, chromium, titanium, silver, copper, aluminium, lead and group that above-mentioned metal becomes alloy one of them.
16. structure as claimed in claim 13, wherein, this solder layer be selected from tin, gold, nickel, chromium, titanium, silver, copper, aluminium, lead and group that above-mentioned metal becomes alloy one of them.
17. structure as claimed in claim 14, wherein, this metal level be selected from copper, aluminium, tin, nickel, chromium and group that above-mentioned metal becomes alloy one of them.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710180728 CN101409238A (en) | 2007-10-11 | 2007-10-11 | Method for preparing seedless layer package substrate |
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|---|---|---|---|
| CN 200710180728 CN101409238A (en) | 2007-10-11 | 2007-10-11 | Method for preparing seedless layer package substrate |
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| CN101409238A true CN101409238A (en) | 2009-04-15 |
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| CN109427725A (en) * | 2017-09-05 | 2019-03-05 | 恒劲科技股份有限公司 | Intermediary substrate and its preparation method |
| CN109427725B (en) * | 2017-09-05 | 2021-04-27 | 恒劲科技股份有限公司 | Interposer substrate and method of manufacturing the same |
| CN112118682A (en) * | 2019-06-21 | 2020-12-22 | 培英半导体有限公司 | Method for forming copper layer on circuit board and circuit board with sputtered copper layer |
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