200926372 九、發明說明： 【發明所屬之技術領域】 5 ❹ 10 15 20 本發明係關於一種封裝基板及其製作方法，尤指一種 適用於簡化製程、縮短訊號傳遞路徑及減少雜訊干擾之封 裝基板及其製作方法。 【先前技術】 隨著電子產業的蓬勃發展，電子產品亦逐漸進入多功 能、高性能的研發方向。為滿足半導體封裝件高積集度 (Integration)以及微型化（Miniaturization)的封裝要求，提供 多數主被動元件及線路連接之電路板，亦逐漸由單層板演 變成多層板，以使在有限的空間下，藉由層間連接技術 (Interlayer connection)擴大電路板上可利用的佈線面積而 配合高線路密度之積體電路（Integrated circuit)需求。 目前，半導體封裝結構大多是將半導體晶片黏貼於基 板頂面後進行打線接合（wire bonding)或是將半導體晶片以 覆晶接合（Flip chip)方式與基板電性連接，爾後再於基板之 背面植以錫球，以電性連接至如印刷電路板之外部電子元 件。 在習知封裝基板的製作方法中，載板係由一核心基板 開始，經過鑽孔、鍍金屬、塞孔、線路成型等製程完成内 層結構。再經由增層製程完成多層載板，如圖1A至1E所示， 係製作增層式的多層板的方法。如圖1A所示，首先，製備 一核心基板11，該核心基板11係由一具預定厚度的芯層111 5 200926372 5 10 15 ❷ 及形成於該芯層111表面上之線路層112所構成。同時，於 該芯層111中形成有複數個電鍍導通孔（PTH)113。藉此電性 連接該芯層111相對兩表面之線路層112。如圖1B所示，將 該核心基板11實施增層製程，首先於該核心基板U表面佈 設一介電層12,該介電層12上開設有複數個開孔曝露出該 線路層112作為電性連接墊112a部分。如圖1C所示，於該介 電層12曝露表面以無電電鍍或濺鍍等方式形成一晶種層 14 ’並於該晶種層14上形成一圖案化阻層15，俾使該阻層 15形成有複數個開孔丨5〇以曝露出電性連接墊n2a。如圖1D 所示’利用電鍍方式於該阻層開孔15〇中形成有圖案化線路 層16與導電盲孔16a ’並使該線路層16得以透過該導電盲孔 16a電性導接至該電性連接墊112a，然後移除該阻層及阻層 所覆蓋之晶種層’俾以形成一第一線路增層結構1〇a<)如圖 1E所示’同樣地，於該第一線路增層結構1〇a最外層表面上 亦得運用相同方法重複形成第二線路增層結構1〇b，以逐步 增層形成一多層載板1〇。 然上述製程係由一核心基板開始，經過鑽孔、鍵金屬、 塞孔、線路成型等製程完成内層結構，再經由增層製程完 成多層載板’因而有製程步驟流程複雜之缺點。此外，此 作法因該核心基板需經鑽孔、電鍍等製程形成電鍍導通孔 (PTH) ’電鍍導通孔之孔徑及孔深均遠大於導電盲孔，因而 訊號傳遞路徑過長，易產生串擾（Cross-talk)、雜訊（Noise) 或訊號衰減之問題；此外，電鍍導通孔延伸出介電層表面 20 200926372 之部分亦會佔據佈線空間。 須解決的課題。 故前述問題實為現今業界所急 5 【發明内容】 有鐘於習知之缺點，本發明之 種可簡化製程、縮短訊號傳遞路徑 佈線密度的封裝基板結構與製法。 主要目的係在於提供一 、減少雜訊干擾及提高200926372 IX. Description of the invention: [Technical field of invention] 5 ❹ 10 15 20 The present invention relates to a package substrate and a method of fabricating the same, and more particularly to a package substrate suitable for simplifying a process, shortening a signal transmission path, and reducing noise interference. And its production method. [Prior Art] With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional and high-performance research and development. In order to meet the packaging requirements of semiconductor package high integration and miniaturization, most active and passive components and circuit-connected circuit boards are also gradually evolved from single-layer boards to multi-layer boards to make them limited. In space, the interlayer area is used to expand the available wiring area on the board to meet the high circuit density integrated circuit requirements. At present, a semiconductor package structure is generally obtained by bonding a semiconductor wafer to a top surface of a substrate, performing wire bonding, or electrically connecting the semiconductor wafer to a substrate by flip chip bonding, and then implanting the substrate on the back surface of the substrate. A solder ball is electrically connected to an external electronic component such as a printed circuit board. In the manufacturing method of the conventional package substrate, the carrier board is started from a core substrate, and the inner layer structure is completed through a process such as drilling, metal plating, plugging, and line forming. The multilayer carrier is then completed via a build-up process, as shown in Figures 1A through 1E, which is a method of making a build-up multilayer. As shown in Fig. 1A, first, a core substrate 11 is formed which is composed of a core layer 111 5 200926372 5 10 15 预定 having a predetermined thickness and a wiring layer 112 formed on the surface of the core layer 111. At the same time, a plurality of plated vias (PTH) 113 are formed in the core layer 111. Thereby, the circuit layer 112 of the core layer 111 opposite to the two surfaces is electrically connected. As shown in FIG. 1B, the core substrate 11 is subjected to a build-up process. First, a dielectric layer 12 is disposed on the surface of the core substrate U. The dielectric layer 12 is provided with a plurality of openings to expose the circuit layer 112 as electricity. The connection pad 112a portion. As shown in FIG. 1C, a seed layer 14' is formed on the exposed surface of the dielectric layer 12 by electroless plating or sputtering, and a patterned resist layer 15 is formed on the seed layer 14, and the resist layer is formed. 15 is formed with a plurality of openings 丨5〇 to expose the electrical connection pads n2a. As shown in FIG. 1D, a patterned wiring layer 16 and a conductive via hole 16a are formed in the barrier opening 15 by electroplating, and the wiring layer 16 is electrically connected to the conductive via 16a. Electrically connecting the pad 112a, and then removing the resist layer and the seed layer covered by the resist layer to form a first line build-up structure 1〇a<; as shown in FIG. 1E'. Similarly, in the first The second line build-up structure 1〇b is also repeatedly formed on the outermost surface of the line build-up structure 1〇a by the same method to gradually form a multi-layer carrier 1〇. However, the above process starts from a core substrate, and the inner layer structure is completed through a process such as drilling, key metal, plug hole, and line forming, and then the multilayer carrier is completed through the build-up process, thereby having the disadvantages of complicated process steps. In addition, since the core substrate needs to be formed by drilling, electroplating, etc. to form a plated via (PTH), the aperture and hole depth of the plated via are much larger than the conductive blind holes, so that the signal transmission path is too long and crosstalk is easily generated ( Cross-talk, noise, or signal attenuation; in addition, the portion of the plated via extending beyond the surface of the dielectric layer 20 200926372 also occupies wiring space. The subject to be solved. Therefore, the foregoing problems are urgent in the industry today. [Explanation] There is a drawback of the prior art, and the package substrate structure and method for simplifying the process and shortening the wiring density of the signal transmission path of the present invention. The main purpose is to provide one, reduce noise interference and improve
10 15 ❹ 為達上揭目的’本發明係提供一種封裝基板其包括 :第-介電層’其具有複數貫穿第—介電層之圖案化開口 區；-第-線路層’係配置於第—介電層之該些圖案化開 口區中，且第一線路層與第一介電層之相對兩表面齊平； 以及一線路增層結構，其係配置於第一線路層與第一介電 層之兩相對表面’其中，線路增層結構中具有複數個導電 盲孔以電性連接至第一線路層，且線路增層結構表面形成 有複數電性連接墊。據此，兩側線路可藉由第一線路層及 導電盲孔導通’而無需另製作電料通孔，進而可解決電 鍍導通孔延伸出介電層表面之部分而佔據佈線空間之問 題，同時，本結構之訊號傳遞路徑較短，可有效減少雜訊 干擾，進而提升電性功能。 ° 20 本發明亦提供一種封裝基板之製作方法，其包括：提 供一支撐板；形成一第一介電層於該支撐板之一表面上， 並形成複數貫穿第一介電層之圖案化開口區；電鍍一第一 線路層於該些圖案化開口區中，並使第一線路層與第一介 電層之表面齊平；移除支撐板；以及形成一線路增層結構 7 200926372 5 於第一線路層與第一介電層之兩相對表面，其中，線路增 層結構中具有複數個導電盲孔以電性連接至第一線路層，S 且線路增層結構表面形成有複數電性連接墊。據此，本發 明所提供之封裝基板製作方法可有效簡化製作流程，改善 習知封裝基板製作流程複雜之缺點。 於本發明之封衮基板及其製法 為一層或多層，其可包括至少一第 〜爆吩苜層結構可 介電層、至少一第二 Ο 10 15 ❹ 線路層、以及複數導電盲孔。詳細地說，此線路增層結構 可包括至少一第二介電層、至少一疊置於第二介電層上之 第二線路層、以及形成於第二介電層中之複數導電盲孔。 或者，此線路增層結構可包括至少一第二介電層、至少一 嵌埋於第二介電層之第二線路層、以及形成於該第二二電 層中之該些導電盲孔，，兮健— a § ^具中該第一線路層之裸露表面係 與該第一介電層之表面齊平。 於本發明之封裝基板及其製法中，此第—介電層可為 感光型介電材料’而第一介電層之圖案化開口區可利用曝 :及顯影之圖案化方式形成；或者，此第一介電層為非感 光型介電材料’而第一介電層之 鑽孔或雷射鑽孔形成。 [刊用機械 △ Φ ;本發明之封裝基板及其製法中，第一線路層與第一 1層之兩相對表面可藉由粗化處理而成為粗化表面，以 增加第—線路層及第—介電層與第二介電層間之结合力。 2粗=線路層與第一介電層之兩相對表面可藉由微餘 仃粗化處理’如：化學式_、電㈣刻等。 20 200926372 本發明之支律板種類不限，其可為導電m面且 有-導電層之絕緣板’據此，導電板及絕緣板之導電層可 作為電鍍第-線路層所需之電流㈣轉用。此外，本發 明之第-線路層、第二線路層及導電盲孔使用之材料可選 5 10 15 ❹ 20 自由銅、錫、錄、路、鈦、船、金以及銅_絡合金所組成之 群組之其中一者’其中較佳為銅。 於本發明之封裝基板及其製法復可包括一防焊層，其 係形成於線路增層結構表面’其中’此防焊層具有複數防 焊層開孔，俾以顯露線路增層結構之電性連接墊。此外， 該些電性連接墊上復可接置焊料球或焊料凸塊，以與晶片 之電極墊或其他電子元件電性連接。 综上所述，本發明所提供之無通孔結構可提高佈線密 度，縮短訊號傳遞路徑，降低封裝基板厚度，減少雜訊干 擾且簡化製程流程；同時，本發明形成對稱之線路增層結 構，得以避免板彎翹之問題發生。 【實施方式】 以下係藉由特定的具體實施例說明本發明之實施方 式，熟習此技藝之人士可由本說明書所揭示之内容輕易地 了解本發明之其他優點與功效。本發明亦可藉由其他不同 的具趑實施例加以施行或應用，本說明書中的各項細節亦 可基於不同觀點與應用’在不悖離本發明之精神下進行各 種修飾與變更* 9 200926372 本發明之實施例中該等圖式均為簡化之示意圖。惟該 等圖式僅顯示與本發明有關之元#，其所顯示之元件非為 實際實施時之態樣，其實際實施時之元件數目、形狀等比 5 ❹ 10 15 Ο 例為一選擇性之設計，且其元件佈局型態可能更複雜。 實施例1 請參考圖2Α至2Ε，係為本發明一較佳實施例之封裝基 板製作流程剖視圖。 首先，如圖2Α所示，提供一支撐板21，於本實施例中， 此支撐板21為一表面具有導電層211之絕緣板，其中，導電 層211係作為後續電鍍製程所需之電流傳導路徑用。接著， 形成第一介電層22於該導電層211之表面上，並形成複數貫 穿此第一介電層22之圖案化開口區22卜於本實施例中，該 第一介電層22係為感光型介電材料，而該些圖案化開口區 221係利用曝光及顯影之圖案化方式形成。 隨後，如圖2Β所示’電鍍第一線路層23於該些圖案化 開口區221中’並使第一線路層23與第一介電層22之表面齊 平。於本實施例中，此第一線路層23可使用的材料選自由 銅、錫、錄、鉻、欽、錯、金以及銅-鉻合金所組成之群組 之一者，在本實施例係使用銅。 如圖2C所示，移除具有導電層之支撐板，並以微蚀方 式進行第一線路層23與第一介電層22兩相對表面之粗化處 理0 接著’如圖2D所不’於第一線路層23與第一介電層22 之兩相對表面以線路增層技術形成一線路增層結構24。其 20 200926372 5 ❹ 10 15 20 中，此線路增層結構24包括：第二介電層241 ;疊置於第二 介電層241上之第二線路層242，其係利用阻層（圖未示），以 曝光及顯影之方式再加以電鍍而形成；以及導電盲孔243， 其係於第二介電層241中以雷射鑽孔形成盲孔（圖未示）後而 與第二線路層242同時利用電鍍之方式而形成。在此，此線 路增層結構24之導電盲孔243係電性連接至第一線路層 23，且線路增層結構24表面亦形成有複數電性連接墊 242a。另，第二線路層242以及導電盲孔243使用的材料係 可為選自由銅、錫、錄、鉻、鈦、船、金以及銅-鉻合金所 組成之群組之一者，在本實施例係使用銅。 最後，如圖2E所示，於線路增層結構24表面形成防焊 層25，且此防焊層25具有複數防焊層開孔251，俾以顯露線 路增層結構24之電性連接墊242a。其中，該些電性連接墊 242a上復可接置焊料球（圖未示）或焊料凸塊（圖未示），以與 晶片之電極墊或其他電子元件電性連接。 據此，本發明之封裝基板係可如圖2E所示，包括：一 第一介電層22,其具有複數貫穿該第一介電層22之圖案化 開口區221 ; —第一線路層23，係配置於該第一介電層22之 該些圖案化開口區221中，且該第一線路層23與該第一介電 層22之相對兩表面齊平；一線路增層結構24，其係配置於 該第一線路層23與該第一介電層22之兩相對表面，其中， 該線路增層結構24包括至少一第二介電層24卜至少一疊置 於該第二介電層241上之第二線路層242、以及形成於該第 二介電層241中之該些導電盲孔243，而該些導電盲孔243係 11 200926372 電性連接至該第一線路層23，且該線路增層結構24表面形 成有複數電性連接墊242a ;以及一防焊層25，係配置於該 線路增層結構24之表面，且該防焊層25具有複數防焊層開 孔251，俾以顯露該線路增層結構24之該些電性連接墊 5 242a 0 實施例2 請參考圖3A及3E，係為本發明另一較佳實施例之封裝 0 基板製作流程剖視圖。 10 首先，如圖3A所示，提供一支撐板31，於本實施例中， 此支撐板31為一導電板。接著，形成第一介電層32於支撐 板31之表面上，並形成複數貫穿此第一介電層32之圖案化 開口區321。於本實施例中，該第一介電層32係為非感光型 介電材料，而該些圖案化開口區321係利用雷射鑽孔方式形 15 成。 隨後，如圖3B所示，電鍍第一線路層33於該些圖案化10 15 ❹ In order to achieve the above, the present invention provides a package substrate comprising: a first dielectric layer having a plurality of patterned opening regions penetrating through the first dielectric layer; and a first circuit layer configured on the first a plurality of patterned open areas of the dielectric layer, wherein the first circuit layer is flush with opposite surfaces of the first dielectric layer; and a line build-up structure disposed on the first circuit layer and the first dielectric layer The two opposite surfaces of the electrical layer have a plurality of conductive blind holes in the line build-up structure to be electrically connected to the first circuit layer, and a plurality of electrical connection pads are formed on the surface of the circuit build-up structure. Accordingly, the two side lines can be electrically connected by the first circuit layer and the conductive blind holes without the need to separately fabricate the electric material through holes, thereby solving the problem that the plating vias extend beyond the surface of the dielectric layer to occupy the wiring space. The signal transmission path of the structure is short, which can effectively reduce noise interference, thereby improving electrical functions. The invention also provides a method for fabricating a package substrate, comprising: providing a support plate; forming a first dielectric layer on a surface of the support plate; and forming a plurality of patterned openings extending through the first dielectric layer And plating a first circuit layer in the patterned opening regions and aligning the first circuit layer with the surface of the first dielectric layer; removing the support plate; and forming a line build-up structure 7 200926372 5 The opposite surface of the first circuit layer and the first dielectric layer, wherein the circuit build-up structure has a plurality of conductive blind holes electrically connected to the first circuit layer, and the surface of the line build-up structure is formed with a plurality of electrical properties. Connection pad. Accordingly, the method for fabricating a package substrate provided by the present invention can effectively simplify the manufacturing process and improve the complexity of the conventional packaging substrate manufacturing process. The sealing substrate of the present invention and the method for producing the same are one or more layers, which may include at least one dielectric layer, at least one second Ο 10 15 线路 circuit layer, and a plurality of conductive blind holes. In detail, the line build-up structure may include at least one second dielectric layer, at least one second circuit layer stacked on the second dielectric layer, and a plurality of conductive blind holes formed in the second dielectric layer. . Alternatively, the line build-up structure may include at least one second dielectric layer, at least one second circuit layer embedded in the second dielectric layer, and the conductive via holes formed in the second second electrical layer.兮健—a § ^ The exposed surface of the first circuit layer is flush with the surface of the first dielectric layer. In the package substrate of the present invention and the method of fabricating the same, the first dielectric layer may be a photosensitive dielectric material and the patterned opening region of the first dielectric layer may be formed by exposure and development; or The first dielectric layer is a non-photosensitive dielectric material' and the first dielectric layer is drilled or laser drilled. [Publishing machine △ Φ; in the package substrate of the present invention and the manufacturing method thereof, the opposite surfaces of the first circuit layer and the first layer can be roughened by roughening treatment to increase the first circuit layer and the first — the bonding force between the dielectric layer and the second dielectric layer. 2 coarse = the opposite surface of the circuit layer and the first dielectric layer can be treated by micro-reduction roughening, such as: chemical formula, electric (four) engraving, and the like. 20 200926372 The type of the law board of the present invention is not limited, and it can be an insulating plate with a conductive m-plane and a conductive layer. Accordingly, the conductive layer of the conductive plate and the insulating plate can be used as a current required for electroplating the first-line layer (4) Switch to use. In addition, the material of the first circuit layer, the second circuit layer and the conductive blind hole of the present invention may be selected from the group consisting of 5 10 15 ❹ 20 free copper, tin, magnet, titanium, ship, gold and copper alloy. One of the groups 'of which is preferably copper. The package substrate and the method for manufacturing the same according to the present invention include a solder resist layer formed on the surface of the line build-up structure, wherein the solder resist layer has a plurality of solder mask openings, and the circuit is formed to reveal the power of the line build-up structure. Sex connection pad. In addition, solder pads or solder bumps may be attached to the electrical connection pads to electrically connect to the electrode pads or other electronic components of the wafer. In summary, the through-hole-free structure provided by the present invention can improve the wiring density, shorten the signal transmission path, reduce the thickness of the package substrate, reduce noise interference, and simplify the process flow; meanwhile, the present invention forms a symmetrical line build-up structure. It is necessary to avoid the problem of bending the board. [Embodiment] The embodiments of the present invention will be described by way of specific examples, and those skilled in the art can readily understand other advantages and effects of the present invention from the disclosure of the present disclosure. The present invention may be embodied or applied by other different embodiments. The details of the present specification can also be modified and changed without departing from the spirit and scope of the present invention* 9 200926372 The drawings in the embodiments of the present invention are simplified schematic diagrams. However, the drawings only show the elements associated with the present invention, and the components shown therein are not in actual implementation, and the number of components and the shape of the actual implementation are 5 ❹ 10 15 Ο. The design and its component layout may be more complicated. Embodiment 1 Please refer to Figs. 2A to 2B, which are cross-sectional views showing a manufacturing process of a package substrate according to a preferred embodiment of the present invention. First, as shown in FIG. 2A, a support plate 21 is provided. In this embodiment, the support plate 21 is an insulating plate having a conductive layer 211 on the surface, wherein the conductive layer 211 is used as a current conduction required for a subsequent electroplating process. The path is used. Next, a first dielectric layer 22 is formed on the surface of the conductive layer 211, and a plurality of patterned opening regions 22 penetrating through the first dielectric layer 22 are formed. In the embodiment, the first dielectric layer 22 is It is a photosensitive dielectric material, and the patterned opening regions 221 are formed by patterning by exposure and development. Subsequently, the electroplated first wiring layer 23 is formed in the patterned opening regions 221 as shown in Fig. 2' and the first wiring layer 23 is flush with the surface of the first dielectric layer 22. In this embodiment, the material that can be used for the first circuit layer 23 is selected from the group consisting of copper, tin, chrome, chrome, chrome, gold, and copper-chromium alloy. Use copper. As shown in FIG. 2C, the support plate having the conductive layer is removed, and the roughening process of the opposite surfaces of the first circuit layer 23 and the first dielectric layer 22 is performed in a micro-etching manner. 0 Then, as shown in FIG. 2D, The two opposite surfaces of the first circuit layer 23 and the first dielectric layer 22 form a line build-up structure 24 by a line build-up technique. In 20 200926372 5 ❹ 10 15 20 , the line build-up structure 24 includes: a second dielectric layer 241; and a second circuit layer 242 stacked on the second dielectric layer 241, which utilizes a resist layer (not shown) And is formed by electroplating by exposure and development; and a conductive blind via 243 is formed in the second dielectric layer 241 to form a blind via (not shown) by laser drilling and the second trace Layer 242 is simultaneously formed by electroplating. Here, the conductive via 243 of the line build-up structure 24 is electrically connected to the first circuit layer 23, and the surface of the circuit build-up structure 24 is also formed with a plurality of electrical connection pads 242a. In addition, the material used in the second circuit layer 242 and the conductive blind via 243 may be one selected from the group consisting of copper, tin, copper, chromium, titanium, ship, gold, and copper-chromium alloy. The example uses copper. Finally, as shown in FIG. 2E, a solder resist layer 25 is formed on the surface of the line build-up structure 24, and the solder resist layer 25 has a plurality of solder resist openings 251 to expose the electrical connection pads 242a of the line build-up structure 24. . The electrical connection pads 242a are electrically connected to solder balls (not shown) or solder bumps (not shown) for electrically connecting to the electrode pads or other electronic components of the wafer. Accordingly, the package substrate of the present invention, as shown in FIG. 2E, includes: a first dielectric layer 22 having a plurality of patterned opening regions 221 extending through the first dielectric layer 22; The first circuit layer 23 is flush with the opposite surfaces of the first dielectric layer 22; a line build-up structure 24 is disposed in the patterned opening regions 221 of the first dielectric layer 22, The second layer is formed on the opposite surface of the first circuit layer 23 and the first dielectric layer 22, wherein the line layering structure 24 includes at least one second dielectric layer 24 at least one stack placed on the second layer. a second circuit layer 242 on the electrical layer 241 and the conductive vias 243 formed in the second dielectric layer 241, and the conductive vias 243 are connected to the first circuit layer 23 And a plurality of electrical connection pads 242a are formed on the surface of the line build-up structure 24; and a solder resist layer 25 is disposed on the surface of the line build-up structure 24, and the solder resist layer 25 has a plurality of solder mask openings 251, 俾 to expose the electrical connection pads 5 242a of the line build-up structure 24. Embodiment 2 Please refer to FIG. 3A and 3E A cross-sectional view of the package system of the present invention, another preferred embodiment of the 0 substrate production process embodiment. 10 First, as shown in FIG. 3A, a support plate 31 is provided. In this embodiment, the support plate 31 is a conductive plate. Next, a first dielectric layer 32 is formed on the surface of the support plate 31, and a plurality of patterned opening regions 321 extending through the first dielectric layer 32 are formed. In the present embodiment, the first dielectric layer 32 is a non-photosensitive dielectric material, and the patterned opening regions 321 are formed by laser drilling. Subsequently, as shown in FIG. 3B, the first wiring layer 33 is plated to be patterned.
開口區321中，並使第一線路層33與第一介電層32之表面齊 A 平。於本實施例中，此第一線路層33可使用的材料選自由 銅、錫、錄、絡、鈦、錯、金以及銅-絡合金所組成之群組 20 之一者，在本實施例係使用銅。 如圖3C所示，移除支撐板，並以微蝕方式進行第一線 路層33與第一介電層32兩相對表面之粗化處理。 接著，如圖3D所示，於第一線路層33與第一介電層32 之兩相對表面以增層技術形成一線路增層結構34。其中， 25 此線路增層結構34包括：第二介電層341 ;嵌埋於第二介電 12 200926372 5 Ο 10 15 ❹ 20 層341之第二線路層342，其係於第二介電層341中形成複數 線路開口（圖未示）後再加以電鍍，並利用刷磨或蝕刻方式將 電鍍出之金屬進行平坦化而形成；以及導電盲孔343，其係 於第二介電層341中以雷射鑽孔形成盲孔（圖未示）後而與第 二線路層342同時利用電鍍之方式而形成。在此，此線路增 層結構34之導電盲孔343係電性連接至第一線路層33，且線 路增層結構34表面亦形成有複數電性連接墊342a。另，第 二線路層342以及導電盲孔343使用的材料係可為選自由 銅、錫、鎳、絡、鈦、錯、金以及銅-絡合金所組成之群組 之一者，在本實施例係使用銅。 最後，如圖3E所示，於線路增層結構34表面形成防焊 層35，且此防焊層35具有複數防焊層開孔351，俾以顯露線 路增層結構34之電性連接墊342a。其中，該些電性連接墊 342a上復可接置焊料球（圖未示）或焊料凸塊（圖未示），以與 晶片之電極墊或其他電子元件電性連接。 據此，本發明之封裝基板係可如圖3E所示，包括：一 第一介電層32，其具有複數貫穿該第一介電層32之圖案化 開口區321 ; —第一線路層33，係配置於該第一介電層32之 該些圖案化開口區321中，且該第一線路層33與該第一介電 層32之相對兩表面齊平；一線路增層結構34，其係配置於 該第一線路層33與該第一介電層32之兩相對表面，其中， 該線路增層結構34包括至少一第二介電層341、至少一嵌埋 於該第二介電層341之第二線路層342、以及形成於該第二 介電層341中之該些導電盲孔343，其中，該第二線路層342 13 200926372 之裸露表面係與該第二介電層341之表面齊平，而該些導電 盲孔343係電性連接至該第一線路層33，且該線路增層結構 34表面形成有複數電性連接墊341a ;以及一防焊層35，係 配置於該線路增層結構34之表面，且該防焊層35具有複數 防焊層開孔35卜俾以顯露該線路增層結構34之該些電性連 接墊342a。 Ο 綜上所述，本發明所提供之無電鍍導通孔結構可提高佈 線密度、縮短訊號傳遞路徑、降低封裝基板厚度、減少雜 訊干擾且簡化製程流程；同時，本發明形成對稱之線路增 層結構，得以避免板彎翹之問題發生。 上述實施例僅係為了方便說明而舉例而已，本發明所 主張之權利範圍自應以申請專利範圍所述為準，而非僅限 於上述實施例。 15 【圖式簡單說明】 圖1A至1E係習知之封裝基板製作流程剖視圖。 ❹ 圖2A至2E係本發明一較佳實施例之封裝基板製作流程 剖視圖。 圖3A至3E係本發明另一較佳實施例之封裝基板製作流 20 程剖視圖。 【主要元件符號說明 10 10a 多層載板 第一線路增層結構 14 200926372In the opening region 321, the first wiring layer 33 is flush with the surface of the first dielectric layer 32. In this embodiment, the material of the first circuit layer 33 can be selected from one of the group 20 consisting of copper, tin, magnet, titanium, titanium, gold, and copper-coalloy, in this embodiment. Copper is used. As shown in Fig. 3C, the support plate is removed, and the roughening treatment of the opposite surfaces of the first wiring layer 33 and the first dielectric layer 32 is performed in a microetching manner. Next, as shown in FIG. 3D, a line build-up structure 34 is formed by a build-up technique on the opposite surfaces of the first circuit layer 33 and the first dielectric layer 32. The wiring layer structure 34 includes: a second dielectric layer 341; a second wiring layer 342 embedded in the second dielectric layer 12 200926372 5 Ο 10 15 ❹ 20 layer 341, which is tied to the second dielectric layer a plurality of line openings (not shown) are formed in 341, and then electroplated, and the plated metal is planarized by brushing or etching; and a conductive blind hole 343 is attached to the second dielectric layer 341. A blind hole (not shown) is formed by laser drilling, and is formed by electroplating simultaneously with the second wiring layer 342. Here, the conductive via 343 of the line build-up structure 34 is electrically connected to the first circuit layer 33, and the surface of the line build-up structure 34 is also formed with a plurality of electrical connection pads 342a. In addition, the material used in the second circuit layer 342 and the conductive blind via 343 may be one selected from the group consisting of copper, tin, nickel, complex, titanium, gold, and copper-coalloy. The example uses copper. Finally, as shown in FIG. 3E, a solder resist layer 35 is formed on the surface of the line build-up structure 34, and the solder resist layer 35 has a plurality of solder resist openings 351 to expose the electrical connection pads 342a of the line build-up structure 34. . The solder pads 342a can be soldered to solder balls (not shown) or solder bumps (not shown) for electrically connecting to the electrode pads or other electronic components of the wafer. Accordingly, the package substrate of the present invention, as shown in FIG. 3E, includes: a first dielectric layer 32 having a plurality of patterned opening regions 321 extending through the first dielectric layer 32; The first circuit layer 33 is flush with the opposite surfaces of the first dielectric layer 32; a line build-up structure 34 is disposed in the patterned opening regions 321 of the first dielectric layer 32. The circuit is formed on the opposite surfaces of the first circuit layer 33 and the first dielectric layer 32, wherein the circuit build-up structure 34 includes at least one second dielectric layer 341, at least one embedded in the second dielectric layer. a second circuit layer 342 of the electrical layer 341, and the conductive vias 343 formed in the second dielectric layer 341, wherein the exposed surface of the second circuit layer 342 13 200926372 and the second dielectric layer The surface of the 341 is flush, and the conductive blind holes 343 are electrically connected to the first circuit layer 33, and the surface of the circuit build-up structure 34 is formed with a plurality of electrical connection pads 341a; and a solder resist layer 35, Disposed on the surface of the line build-up structure 34, and the solder resist layer 35 has a plurality of solder mask openings 35 The plurality of electrical build-up structure 34 of the line connection pad 342a. In summary, the electroless via-via structure provided by the present invention can improve wiring density, shorten signal transmission path, reduce package substrate thickness, reduce noise interference, and simplify process flow. Meanwhile, the present invention forms a symmetric circuit layer. Structure, to avoid the problem of plate bending. The above-described embodiments are merely examples for the convenience of the description, and the scope of the claims is intended to be limited by the scope of the claims. 15A BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1E are cross-sectional views showing a manufacturing process of a package substrate. 2A to 2E are cross-sectional views showing a process of fabricating a package substrate in accordance with a preferred embodiment of the present invention. 3A to 3E are cross-sectional views showing a flow of a package substrate in accordance with another preferred embodiment of the present invention. [Main component symbol description 10 10a Multi-layer carrier board First line build-up structure 14 200926372
10b 11 111 112, 16 112a, 242a, 342a 113 12 14 15 150 16a, 243, 343 21, 31 211 22, 32 221, 321 23, 33 24, 34 241, 341 242, 342 25, 35 251， 351 第二線路增層結構 核心基板 芯層 線路層 電性連接墊 電鍍導通孔 介電層 晶種層 阻層 開孔 導電盲孔 支撐板 導電層 第一介電層 圖案化開口區 第一線路層 線路增層結構 第二介電層 第二線路層 防焊層 防焊層開孔 1510b 11 111 112, 16 112a, 242a, 342a 113 12 14 15 150 16a, 243, 343 21, 31 211 22, 32 221, 321 23, 33 24, 34 241, 341 242, 342 25, 35 251, 351 Two-line build-up structure core substrate core layer circuit layer electrical connection pad plating via hole dielectric layer seed layer barrier layer opening conductive blind hole support plate conductive layer first dielectric layer patterned opening area first line layer line increase Layer structure second dielectric layer second circuit layer solder mask solder mask opening 15