1361483 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種氧化鋁基板及其製法，尤指一種不 易彎曲且具高線路密度之氧化鋁基板及其製法。 5 【先前技術】 隨著電子產業的蓬勃發展，電子產品亦逐漸進入多功 能、高性能的研發方向。為滿足半導體封裝件高積集度 (Integration )以及微型化（Miniaturization )的封裝要求， 10 提供多數主被動元件及線路連接之封裝基板，亦逐漸由單 層板演變成多層板，以使在有限的空間下，藉由層間連接 技術（Interlayer connection)擴大封裝基板上可利用的佈 線面積而配合南電子後度之積體電路（Integrated circuh^ 需求。 15 一般半導體裝置之製程，首先係由晶片載板製造業者 生產適用於該半導體裝置之晶片載板，如基板或導線架。 之後再將該些晶片載板交由半導體封裝業者進行置晶、打 線、封膠以及植球等封裝製程。又一般半導體封裝是將半 導體晶片背面黏貼於封裝基板頂面進行打線接合（wire 2〇 bonding )，或者將半導體晶片之作用面以覆晶接合（flip chip)方式與封裝基板接合，再於基板之背面植以焊料球以 供與其他電子裝置如印刷電路板進行電性連接。 上述之封裝基板可參考圖1所示之結構。目前業界常用 BT 樹脂（BismaleimideTriazineResin)作為核心板 u 的材 5 1361483 料，而後進行線路製程，以於核心板11表面形成線路12及 導通核心板11兩側表面線路12之電鍍導通孔121，再利用增 層技術形成增層結構13,其中，該增層結構13係包括導電 盲孔131及増層線路層132及介電層134，最後於增層結構13 5 表面形成一防焊層14,形成一封裝基板1〇。 然而，因上述核心板採用BT樹脂（Bismaleimide Triazine Resin)作為材料，而增層結構13之介電層134之材 料大多為ABF樹脂（Ajinomoto build-up film)，通常不同 材料所具有之熱膨脹係數（Coefficient of thermal 10 expansion，CTE)不同。封裝基板i〇常因核心板u (BT樹 脂）與介電層134( ABF樹脂）兩者熱膨脹係數之差異（cte difference)，或者因核心板11兩表面之增層結構13不對稱， 致使以BT樹脂為材質之硬度低封裝基板丨〇因不對稱應力產 生彎翹情況，導致生產成品良率偏低且可靠度不佳。 15 另外，上述之封裝基板1〇需要核心板11，而其線路佈 局（例如線路12及增層線路層132)僅配置於核心板11及介 電層134表面，但核心板11内之電鍍導通孔121常佔用較大 空間，且核心板11内亦無法配置線路，而浪費了線路佈局 空間。因此，若能降低封裝基板產生板彎翹情況，並且提 20高封裝基板之生產良率，同時提高線路佈局之密度，將使 封裝基板之應用性提高。 【發明内容】 6 1361483 1361483 ίο 15[Technical Field] The present invention relates to an alumina substrate and a method for producing the same, and more particularly to an alumina substrate which is not easily bendable and has a high line density and a method for producing the same. 5 [Prior Art] With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional and high-performance research and development. In order to meet the packaging requirements of semiconductor package high integration and miniaturization, 10 most of the active and passive components and circuit-connected package substrates are gradually evolved from single-layer boards to multi-layer boards to make them limited. In the space, the interlayer area available on the package substrate is expanded by Interlayer connection to match the integrated circuit of the South Electronics (Integrated circuh^. 15) The process of general semiconductor devices is first carried out by the wafer. The board manufacturer produces a wafer carrier board suitable for the semiconductor device, such as a substrate or a lead frame. The chip carrier board is then transferred to a semiconductor package manufacturer for packaging processes such as crystallization, wire bonding, sealing, and ball implantation. In the semiconductor package, the back surface of the semiconductor wafer is adhered to the top surface of the package substrate for wire bonding, or the active surface of the semiconductor wafer is bonded to the package substrate by flip chip bonding, and then implanted on the back surface of the substrate. Solder balls are used for electrical connection with other electronic devices such as printed circuit boards. The package substrate can be referred to the structure shown in Fig. 1. At present, BT resin (Bismaleimide Triazine Resin) is commonly used as the core material of the core board u, and then the line process is performed to form the line 12 and the core board 11 on the surface of the core board 11. The plating vias 121 of the two side surface lines 12 are further formed into a build-up structure 13 by a build-up technique. The build-up structure 13 includes conductive vias 131 and a germanium layer 132 and a dielectric layer 134. A solder resist layer 14 is formed on the surface of the layer structure 13 5 to form a package substrate 1 . However, since the core plate is made of BT resin (Bismaleimide Triazine Resin), the dielectric layer 134 of the build-up structure 13 is mostly ABF resin (Ajinomoto build-up film), which usually has different coefficients of thermal expansion (CTE). The package substrate is often due to the core plate u (BT resin) and the dielectric layer 134 (ABF resin). The difference in thermal expansion coefficient (cte difference) or the asymmetry of the build-up structure 13 on both surfaces of the core plate 11 results in a low hardness package made of BT resin. The plate is bent due to asymmetric stress, resulting in low yield and poor reliability of the finished product. 15 In addition, the above-mentioned package substrate 1 requires the core board 11 and its wiring layout (for example, the line 12 and the build-up layer) The circuit layer 132) is disposed only on the surface of the core board 11 and the dielectric layer 134. However, the plating vias 121 in the core board 11 often occupy a large space, and the line cannot be disposed in the core board 11, thereby wasting the layout space. Therefore, if the bending of the package substrate is reduced, and the production yield of the package substrate is improved, and the density of the layout is increased, the applicability of the package substrate is improved. SUMMARY OF THE INVENTION 6 1361483 1361483 ίο 15
20 本發明之主要目的係在提供一種氧化鋁基板及其製 法本發明所提供之氧化銘基板，不僅^有不易因應力彎 :之特性’且其厚度較薄並充分利用氧化紹基板線路佈局 空間，俾能取代傳統核心板。 .為達成上述目的，本發明提供一種氧化鋁基板，其包 括 氧化鋁層，係具有複數第一開口區且該複數第一開 口區貫穿該氧化層；以及-第—線路層，係配置並敌入 該乳化層之該複數第―開σ區中；#中，該第―線路層 係齊平於該氡化鋁層相對兩表面。 上述之氣化銘基板可更可包含一防焊層覆蓋該氧化紹 層及該第-線路層表面，且該防谭層具有複數開孔顯露做 為電性連接垫之部分該第-線路層。此外，亦可再包括一 η電層覆蓋該氧化鋁層及該第一線路層表面，其中，該介 電層具有-第二線路層嵌埋其中，且該第二線路層表面係 齊平於該介電層表面，部分該第：線路層電性連接於該第 -線路層。另外’也可復包括—防焊層覆蓋該介電層表面， 且該防焊層具有複數開孔顯露做為電性連接墊之部分該第 二線路層》 本發明亦提供-種氧化铭基板之製法，其包括：提供 -紹層，係具有-第一表面及一相對之第二表面；氧化該 鋁層之該第二表面，以形成一氧化鋁層於該第二表面；圖 案化該氧化銘層’使該氧化紹層具有複數第-開口區;形 成-第-線路層於該複數第一開口區中，且該第一線路層 與該氧化鋁層之表面齊平；以及移除該鋁層。 7 1361483 上述之製法可更包含於移除該鋁層後，形成一介電層 於該氧化紹層及該第一線路層表面，並於該介電層中開設 複數第二開口區，而後電鍍形成一第二線路層於該複數第 二開口區中，其中，該第二線路層表面係齊平於該介電層 表面，並電性連接於該第一線路層。另外，亦可復包括於 形成該介電層後，形成一防焊層於該介電層表面，其中， 該防焊層具有複數開孔顯露做為電性連接墊之部分該第二The main object of the present invention is to provide an alumina substrate and a method for producing the same. The oxidized substrate provided by the present invention is not only difficult to be subjected to stress bending: and its thickness is thin, and the layout space of the substrate of the oxide substrate is fully utilized. , can replace the traditional core board. In order to achieve the above object, the present invention provides an alumina substrate comprising an aluminum oxide layer having a plurality of first open regions and the plurality of first open regions penetrating the oxide layer; and - a first circuit layer, configured and enemies In the plural first-opening σ region of the emulsified layer; in the #, the first-line layer is flush with the opposite surfaces of the bismuth aluminum layer. The vaporization substrate may further comprise a solder mask covering the oxide layer and the surface of the first circuit layer, and the anti-tank layer has a plurality of openings to expose the portion of the first circuit layer as an electrical connection pad. . In addition, an NMOS layer may be further included to cover the surface of the aluminum oxide layer and the first circuit layer, wherein the dielectric layer has a second circuit layer embedded therein, and the surface of the second circuit layer is flush with A surface of the dielectric layer is partially electrically connected to the first circuit layer. In addition, the invention may also include: a solder mask covering the surface of the dielectric layer, and the solder resist layer having a plurality of openings to be exposed as a portion of the electrical connection pad. The second circuit layer is also provided by the present invention. The method includes: providing a layer having a first surface and an opposite second surface; oxidizing the second surface of the aluminum layer to form an aluminum oxide layer on the second surface; patterning the Oxidizing the underlayer 'having the oxide layer having a plurality of first-open regions; forming a -first wiring layer in the plurality of first open regions, and the first wiring layer is flush with a surface of the aluminum oxide layer; and removing The aluminum layer. 7 1361483 The above method may further comprise: after removing the aluminum layer, forming a dielectric layer on the oxide layer and the surface of the first circuit layer, and opening a plurality of second opening regions in the dielectric layer, and then plating Forming a second circuit layer in the plurality of second opening regions, wherein the surface of the second circuit layer is flush with the surface of the dielectric layer and electrically connected to the first circuit layer. In addition, after forming the dielectric layer, a solder resist layer is formed on the surface of the dielectric layer, wherein the solder resist layer has a plurality of open holes exposed as part of the electrical connection pad.
ίο 15Ίο 15
20 線路層。此外，也可再包括於移除該銘層》，形成一防焊 層於該氧仙層表面H該防焊層具有複數開孔以顯 露該第一線路層。 上述之製法中，氧化該鋁層之第二表面時，係透過形 成—第一阻層於該鋁層之該第一表面上，以保 面。而圖案化該氧化鋁層時，係透過形成一圖案^之第二 阻層於該氧㈣層表面’並利賴刻圖案化該氧化紹層， 以形成該複數第-開Π區顯露部分該銘層。通常移除該複 數第一開口區内所顯露之該氧化銘層係利用電聚蝕刻 (plasma etching )、化學蝕刻、或電溶解 (electrodissolution) 〇 另外，形成-第-線路層於該複數第—開口區前， 及：第二阻層，而後形成一第三阻層於該銘層 用。此外Μ且該第三阻層係顯露部分該紐層作為導電 用此外，該第一阻層、^ 液態光阻或乾膜。 弟-阻層可分別為 8 上述之氧化鋁基板及其製法中，該介電層之材質係選 自由 ABF ( Ajinomoto Build-up Film )、聯二苯環 丁二烯 (benzocylobutene，BCB)、液晶聚合物（liquid crystal polymer，LCP )、聚亞驢胺（polyimide，PI )、聚乙烯醚 (poly ( phenylene ether ) ，PPE )、聚四氟乙稀（poly (tetra-fluoroethylene ) ，PTFE ) 、FR4、FR5、雙順 丁醯 二酸醯亞胺/三氮拼（bismaleimide triazine，BT )、芳香尼 龍（aramide )、及環氧樹脂與玻璃纖維之混合物所組群組 其中之一者。該第一線路層或該第二線路層之材質係選自 由銅、錫、錄、絡、鈦、銅絡合金、以及錫錯合金所組成 群組其中之一者。 由上述氧化鋁基板及其製法可知，其將第一線路配置 於氧化鋁層中，第二線路層亦可電性連接至該第一線路 層，故可以充分利用氧化鋁基板線路佈局空間，並取代習 知的電鍍導通孔，以及減少整體封裝基板之厚度，提高封 裝基板之應用性。另一方面，習知以BT樹脂為材質之核心 板常因硬度不足而無法承受增層結構或熱膨脹係數差所產 生之不對稱應力，所會發生基板彎曲情形；然而本發明所 使用之材質為硬度較高之氧化鋁做為基板，因此可減少上 述基板彎曲情形，進而使成品良率及可靠度提高。 【實施方式】 以下係藉由特定的具體實施例說明本發明之實施方 式，熟習此技藝之人士可由本說明書所揭示之内容輕易地 1361483 了解本發明之其他優點與功效。本發明亦可藉由其他不同 的具體實施例加以施行或應用，本說明書中的各項細節亦 可基於不同觀點與應用，在不棒離本發明之精神下進行各 種修飾與變更。 5 本發明之實施例中該等圖式均為簡化之示意圖。惟該 等圖式僅顯示與本發明有關之元件，其所顯示之元件非為 實際實施時之態樣，其實際實施時之元件數目、形狀等比 例為一選擇性之設計，且其元件佈局型態可能更複雜。 10 實施例1 參考圖2A至圖2N，其為製作本發明氧化鋁基板之流程 示意剖視圖。 首先’如圖2A所示，提供一鋁層21，此鋁層21係具有 一第一表面21a及一相對之第二表面21b。接著，如圖2B所 15 示，形成一第一阻層22於鋁層21之第一表面21a上，以保護 該第一表面21a。形成此第一阻層22之方式，可透過壓合乾 膜或塗佈液態光阻所形成。 如圖2C所示利用陽極處理，將未受第一阻層22保護 的銘層21之第·一表面21b氧化’以形成·一氧化紹層23於第二 20 表面21b。而後’如圖2D所示，形成一圖案化之第二阻層24 於氧化銘層23表面。形成此圖案化之第二阻層24之方式， 可透過壓合乾膜或塗佈液態光阻形成阻層，再以曝光顯影 形成圖案化之第二阻層24。接著，如圖2E所示，透過敍刻 以圖案化氧化鋁層23，便使氧化鋁層23具有複數第一開口 25 區231顯露部分鋁層21。本實施例蝕刻方式可為電漿蝕刻 10 1361483 (plasma etching )、化學蝕刻、或電溶解（eiectr〇dissolution ) 等’以使氧化鋁層23圖案化。 然後’如圖2F所示，移除第一阻層22及第二阻層24。 制除之方式係可取決於第一阻層22及第二阻層24之材質， 5 而選擇使用物理性移除或化學性溶除之方式。再參考圖2G 所示，形成一第三阻層26於鋁層21之第一表面21a，並且第 三阻層26係顯露部分鋁層21作為導電用。形成此第三阻層 26之方式，可透過壓合乾膜或塗佈液態光阻形成阻層，並 顯露紹層21之周緣的部分第一表面21 a(圖中未示）。接著， 10 如圖2H所示，利用該鋁層21顯露之部分導通電流，進行電 鑛’形成一第一線路層27於第一開口區231中。其中，第一 線路層27與氡化鋁層23之表面齊平。另外，第一線路層27 之材質可選自由銅、錫、鎳、鉻、鈦、銅鉻合金、以及錫 鉛合金所組成群組其中之一者。 15 如圖21所示’剝除第三阻層26。剝除第三阻層26之方 式可類似前述移除第一阻層22及第二阻層24之方式。接 著，如圖2J所示，蝕刻移除鋁層21。至此，得到本發明所 提供之氧化鋁基板。此氧化鋁基板包括一氧化鋁層23、以 及一第一線路層27。其中’氧化鋁層23具有複數第一開口 20 區231 ’且第一開口區231貫穿氧化鋁層23，而第一線路層 27配置並嵌入氧化鋁層η之第一開口區23丨中，並且第一線 路層27係齊平於氧化鋁層23相對兩表面。 接續’可選擇性進行以下製程，如圖2K所示，壓合一 介電層29於氧化鋁層23及第一線路層27表面。此介電層29 11 1361483 之材質可為感光或非感光有機材料，例如ABF ( Aj inomoto Build-up Film)、聯二苯環 丁二稀（benzocylobutene，BCB)、 液晶聚合物（liquid crystal polymer，LCP )、聚亞酿胺 (polyimide ’ PI)、聚乙稀謎（poly ( phenylene ether )， 5 PPE )、聚四 乙烯（poly ( tetra-fluoroethylene )，PTFE )、 FR4、FR5、雙順丁酿二酸酿亞胺/三氮牌（bismaleimide triazine，BT)、芳香尼龍（aramide)、或環氧樹脂與玻璃 纖維之混合物。再參考圖2L ’於介電層29中開設複數第二 開口區291，而後於此介電層29表面及其第二開口區291内 10 形成一導電層28。開設第二開口區291之方式’依據介電層 29之材料而定，可利用圖案化微影技術即曝光顯影之方 式，或使用雷射蝕孔或鑽孔之方式開設°惟當利用雷射鑽 孔的技術時，復需進行除膠渣（De_smear)作業以移除因鑽孔 所殘留於該介電層開口内的膠〉查。 15 而後，如圖2M所示，利用導電層28導通電流’電鍵形 成一第二線路層30，之後利用研磨’去除介電層29表面之 金屬及其覆蓋之部分導電層28 ’使第二線路層30僅設置於 第二開口區291中’且其表面齊平於介電層29表面，並電性 連接於第一線路層27。此第二線路層30之材質可類似於第 20 —線路層27。若需要更高密度之線路配置’可進行習知的 線路增層製程’壓合介電層’再形成導電盲孔及增廣線路 層，以增加線路的層數。 接著，如圖2N所示’形成一防焊層31於介電層29表面。 此防焊層31具有複數開孔312顯露做為電性連接墊303之部 12 1361483 分第二線路層30。其中，可見圖2N所示之防焊層31覆蓋部 分電性連接墊303，此電性連接墊303為防焊層定義型電性 連接塾（solder mask defined pads，SMD pads)。 另外，若如圖2N’所示’其防焊層31未覆蓋電性連接 5 墊303，此電性連接墊303則為非防焊層定義型電性連接墊 (non-solder mask defined pads J NSMD pads) ° 實施例2 ® 本實施例氧化鋁基板之製法同上述實施例1，唯一不同 10 在於本實施例沒有接續形成介電層29及第二線路層30於氧 化紹層23及第一線路層27表面，而是直接形成防焊層31於 氧化铭層23及第一線路層27表面。此防焊層31同樣具有具 有複數開孔312顯露做為電性連接墊273之部分第一線路層 27。如圖3所示之防焊層31覆蓋部分電性連接塾273，此電 15 性連接墊273為防焊層定義型電性連接墊（solder mask defined pads，SMD pads )。另外，若如圖3,所示，其防焊 • 層31未覆蓋電性連接墊273，此電性連接墊273則為非防焊 層定義型電性連接墊（non-solder mask defined pads，NSMD pads) ° 20 综上所述，本發明使用具優良熱與機械特性之氧化鋁 做為基板，因此若需進行習知機械鑽孔加工製作時，其通 孔可由一般之ΙΟΟμηι等級到1 Ομιη等級，有利於細微化佈 線，從而提高覆晶基板之佈線密度，不會如同習知ΒΤ樹脂 為材質之核心板’因材質限制而造成製作之孔洞直徑無法 25 低於50 μπι以下’而難以形成更小的孔徑，無法達到更高佈 13 1361483 線被度之缺失。另一方面，本發明製作氧化鋁基板之過程 中’亦利用鋁層、氧化鋁層及非鋁金屬層三者不同之蝕刻 選擇性’而於姓刻過程中僅會使上述其中之一受到姓刻， 而可進行線路製程，並製得細線路結構，亦可視所需製作 5 增層結構於氡化銘基板表面以增加線路佈局。 由於將第一線路配置於氧化铭層中，第二線路層亦可 電性連接至該第一線路層，故可以充分利用氧化鋁基板線 路佈局空間，並取代習知的電鍍導通孔，以及減少整體封 裝基板之厚度，提高封裝基板之應用性。 1〇 另外’由於習知以BT樹脂為材質之核心板常因硬度不 足，而無法承受增層結構或熱膨脹係數差所產生之不對稱 應力，所會發生基板彎曲情形。然而本發明所使用之材質 為硬度較尚之氧化紹做為基板’因此可減少上樹基板彎曲 情形，進而使成品良率及可靠度提高，亦具細微化佈線容 15 易、尺寸穩定性高等優點。 上述實施例僅係為了方便說明而舉例而已，本發明所 主張之權利範圍自應以申請專利範圍所述為準，而非僅限 於上述實施例。 【圖式簡單說明】 圖1係習知封裝基板結構之剖視示意圖。 圖2 A〜2 N係本發明實施例1製作氧化鋁基板之流程剖視示 意圖。 圖2N’係本發明實施例1氧化鋁基板之剖視示意圖。 14 1361483 圖3及3’係本發明實施例2氧化鋁基板之剖視示意圖。 【主要元件符號說明】 10 封裝基板 11 核心板 12 線路 13 增層結構 121 電鍍導通孔 131 導電盲孔 132 增層線路層 21 紹層 21a 第一表面 21b 第二表面 22 第一阻層 23 氧化鋁層 24 第二阻層 231 第一開口區 26 第三阻層 27 第一線路層 28 導電層 273, 303 電性連接墊 29, 134 介電層 291 第二開口區 30 第二線路層 31，14 防焊層 312 開孔 1520 circuit layers. In addition, the removal of the layer may be further included to form a solder mask on the surface of the oxygen mask layer. The solder resist layer has a plurality of openings to expose the first wiring layer. In the above method, when the second surface of the aluminum layer is oxidized, the first resist layer is formed on the first surface of the aluminum layer to protect the surface. And patterning the aluminum oxide layer by forming a pattern of a second resist layer on the surface of the oxygen (four) layer and patterning the oxide layer to form the plurality of exposed portions of the first opening region Ming layer. Typically, the oxidized inscription layer exposed in the first plurality of open regions is removed by plasma etching, chemical etching, or electrodissolution, and the ----------- In front of the open area, and a second resist layer, and then a third resist layer is formed on the layer. In addition, the third resist layer exposes a portion of the layer as a conductive layer. In addition, the first resist layer, the liquid photoresist or the dry film. The resistive layer may be respectively 8 in the above-mentioned alumina substrate and the method for preparing the same, and the material of the dielectric layer is selected from the group consisting of ABF (Ajinomoto Build-up Film), benzocylobutene (BCB), and liquid crystal. Liquid crystal polymer (LCP), polyimide (PI), poly(phenylene ether), PPE, poly(tetra-fluoroethylene, PTFE), FR4 One of the group consisting of FR5, bismaleimide triazine (BT), aramide, and a mixture of epoxy resin and glass fiber. The material of the first circuit layer or the second circuit layer is selected from the group consisting of copper, tin, magnetic, titanium, copper alloy, and tin-alloy. According to the aluminum oxide substrate and the method for producing the same, the first circuit is disposed in the aluminum oxide layer, and the second circuit layer is electrically connected to the first circuit layer, so that the layout space of the aluminum oxide substrate can be fully utilized, and It replaces the conventional plating vias and reduces the thickness of the entire package substrate to improve the applicability of the package substrate. On the other hand, it is known that the core plate made of BT resin is often unable to withstand the asymmetry stress caused by the buildup structure or the difference in thermal expansion coefficient due to insufficient hardness, and the substrate is bent; however, the material used in the present invention is Since the alumina having a high hardness is used as the substrate, the bending of the substrate can be reduced, and the yield and reliability of the finished product can be improved. [Embodiment] The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can easily understand other advantages and effects of the present invention from the disclosure of the present disclosure. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes may be made without departing from the spirit and scope of the invention. 5 In the embodiments of the present invention, the drawings are simplified schematic views. However, the drawings only show the components related to the present invention, and the components shown therein are not in actual implementation, and the actual number of components in the actual implementation is a selective design and the component layout. The pattern may be more complicated. 10 Embodiment 1 Referring to Figures 2A to 2N, there are shown schematic cross-sectional views of a process for producing an alumina substrate of the present invention. First, as shown in Fig. 2A, an aluminum layer 21 having a first surface 21a and an opposite second surface 21b is provided. Next, as shown in Fig. 2B, a first resist layer 22 is formed on the first surface 21a of the aluminum layer 21 to protect the first surface 21a. The manner in which the first resist layer 22 is formed can be formed by laminating a dry film or applying a liquid photoresist. As shown in Fig. 2C, the first surface 21b of the inscription layer 21 which is not protected by the first resist layer 22 is oxidized by anodization to form a layer 23 on the second surface 21b. Then, as shown in Fig. 2D, a patterned second resist layer 24 is formed on the surface of the oxidized layer 23. The patterned second resist layer 24 is formed by forming a resist layer by laminating a dry film or coating a liquid photoresist, and then forming a patterned second resist layer 24 by exposure and development. Next, as shown in Fig. 2E, by patterning the aluminum oxide layer 23, the aluminum oxide layer 23 has a plurality of first openings 25, 231 exposing a portion of the aluminum layer 21. The etching method of this embodiment may be plasma etching 10 1361483 (plasma etching), chemical etching, or electrolysis (eiectr〇dissolution) or the like to pattern the aluminum oxide layer 23. Then, as shown in Fig. 2F, the first resist layer 22 and the second resist layer 24 are removed. The manner of elimination may depend on the material of the first resist layer 22 and the second resist layer 24, and the physical removal or chemical dissolution may be selected. Referring again to Fig. 2G, a third resist layer 26 is formed on the first surface 21a of the aluminum layer 21, and the third resist layer 26 exposes a portion of the aluminum layer 21 for electrical conduction. The third resist layer 26 is formed by forming a resist layer by laminating a dry film or coating a liquid photoresist, and revealing a portion of the first surface 21a (not shown) of the periphery of the layer 21. Next, as shown in FIG. 2H, a portion of the conduction current exposed by the aluminum layer 21 is used to form a first wiring layer 27 in the first opening region 231. The first wiring layer 27 is flush with the surface of the aluminum telluride layer 23. In addition, the material of the first circuit layer 27 may be selected from the group consisting of copper, tin, nickel, chromium, titanium, copper-chromium alloy, and tin-lead alloy. 15 The third resist layer 26 is stripped as shown in FIG. The manner of stripping the third resist layer 26 may be similar to the manner of removing the first resist layer 22 and the second resist layer 24 as described above. Next, as shown in Fig. 2J, the aluminum layer 21 is removed by etching. Thus far, the alumina substrate provided by the present invention was obtained. The alumina substrate includes an aluminum oxide layer 23 and a first wiring layer 27. Wherein the 'alumina layer 23 has a plurality of first openings 20 regions 231 ' and the first opening regions 231 penetrate the aluminum oxide layer 23, and the first wiring layer 27 is disposed and embedded in the first opening region 23A of the aluminum oxide layer n, and The first wiring layer 27 is flush with the opposite surfaces of the aluminum oxide layer 23. The following process can be selectively performed. As shown in Fig. 2K, a dielectric layer 29 is laminated on the surface of the aluminum oxide layer 23 and the first wiring layer 27. The material of the dielectric layer 29 11 1361483 may be a photosensitive or non-photosensitive organic material, such as ABF (Aj inomoto Build-up Film), benzocylobutene (BCB), liquid crystal polymer (liquid crystal polymer, LCP), polyimide 'PI, poly (phenylene ether), 5 PPE), poly (tetra-fluoroethylene), PTFE, FR4, FR5, double-buten Bismaleimide triazine (BT), aramide, or a mixture of epoxy resin and glass fiber. Referring to FIG. 2L', a plurality of second opening regions 291 are formed in the dielectric layer 29, and then a conductive layer 28 is formed on the surface of the dielectric layer 29 and the second opening region 291. The manner in which the second opening region 291 is opened is determined according to the material of the dielectric layer 29, and may be formed by using a patterned lithography technique, that is, by exposure or development, or by using a laser etch hole or a drill hole. In the drilling technique, a de-smear operation is required to remove the glue remaining in the opening of the dielectric layer due to the drilling. 15 then, as shown in FIG. 2M, a conductive layer 28 is used to conduct a current 'key to form a second wiring layer 30, and then the metal is removed by polishing 'the metal of the surface of the dielectric layer 29 and a portion of the conductive layer 28' The layer 30 is disposed only in the second opening region 291 and has a surface flush with the surface of the dielectric layer 29 and is electrically connected to the first wiring layer 27. The material of the second circuit layer 30 can be similar to the 20th-circuit layer 27. If a higher density line configuration is required, a conventional line build-up process can be performed to "press the dielectric layer" to form a conductive blind via and a thickened wiring layer to increase the number of layers. Next, a solder resist layer 31 is formed on the surface of the dielectric layer 29 as shown in Fig. 2N. The solder resist layer 31 has a plurality of openings 312 exposed as portions 12 1361483 of the second connection layer 30. It can be seen that the solder resist layer 31 shown in FIG. 2N covers a portion of the electrical connection pad 303. The electrical connection pad 303 is a solder mask defining type (SMD pads). In addition, if the solder resist layer 31 does not cover the electrical connection 5 pad 303 as shown in FIG. 2N′, the electrical connection pad 303 is a non-solder layer defined type electrical connection pad (non-solder mask defined NSMD pads) ° Example 2 ® The alumina substrate of the present embodiment is produced in the same manner as the above embodiment 1, except that the dielectric layer 29 and the second wiring layer 30 are not formed in the oxide layer 23 and the first layer. The surface of the wiring layer 27 is formed directly on the surface of the oxidized layer 23 and the first wiring layer 27. The solder resist layer 31 also has a portion of the first wiring layer 27 having a plurality of openings 312 exposed as electrical pads 273. The solder resist layer 31 shown in Fig. 3 covers a portion of the electrical connection pads 273 which are solder mask defining pads (SMD pads). In addition, as shown in FIG. 3, the solder resist layer 31 does not cover the electrical connection pad 273, and the electrical connection pad 273 is a non-solder layer defined type of electrical connection pad (non-solder mask defined, NSMD pads) ° 20 In summary, the present invention uses alumina having excellent thermal and mechanical properties as a substrate, so that if a conventional mechanical drilling process is required, the through hole can be from the general ΙΟΟμηι level to 1 Ομιη. The grade is advantageous for miniaturizing the wiring, thereby increasing the wiring density of the flip-chip substrate, and is not difficult to form as the core plate of the conventional enamel resin is made of a material whose diameter cannot be 25 or less below 50 μπι due to material limitation. A smaller aperture does not allow for the loss of the higher cloth 13 1361483 line. On the other hand, in the process of fabricating an alumina substrate of the present invention, the etching selectivity of the aluminum layer, the aluminum oxide layer and the non-aluminum metal layer is also used, and only one of the above is subjected to the surname in the process of surname. Inscribed, the line process can be carried out, and the fine circuit structure can be obtained. It is also possible to make 5 build-up structures on the surface of the Suihuaming substrate to increase the layout of the circuit. Since the first circuit is disposed in the oxidized inscription layer, the second circuit layer can also be electrically connected to the first circuit layer, so that the layout space of the aluminum oxide substrate can be fully utilized, and the conventional plating vias can be replaced and reduced. The thickness of the overall package substrate improves the applicability of the package substrate. 1〇 In addition, the core plate made of BT resin is often incapable of withstanding the asymmetry stress generated by the build-up structure or the difference in thermal expansion coefficient, and the substrate is bent. However, the material used in the present invention is a substrate having a relatively good hardness as a substrate. Therefore, the bending of the upper substrate can be reduced, thereby improving the yield and reliability of the finished product, and also having the advantages of fine wiring capacity, high dimensional stability, and the like. . The above-described embodiments are merely examples for the convenience of the description, and the scope of the claims is intended to be limited by the scope of the claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view showing a conventional package substrate structure. Fig. 2 A to 2 N are schematic cross-sectional views showing the process of producing an alumina substrate in the first embodiment of the present invention. Fig. 2N is a schematic cross-sectional view showing an alumina substrate of Example 1 of the present invention. 14 1361483 Figures 3 and 3' are schematic cross-sectional views showing an alumina substrate of Example 2 of the present invention. [Main component symbol description] 10 Package substrate 11 Core board 12 Line 13 Adding layer structure 121 Plating via hole 131 Conducting blind hole 132 Adding wiring layer 21 Layer 21a First surface 21b Second surface 22 First resist layer 23 Alumina Layer 24 second resist layer 231 first open region 26 third resist layer 27 first circuit layer 28 conductive layer 273, 303 electrical connection pad 29, 134 dielectric layer 291 second open region 30 second circuit layer 31, 14 Solder mask layer 312 opening 15