TWI231552B - Method for forming circuits patterns of interlayer for semiconductor package substrate - Google Patents

Abstract

A packaging substrate having conductive structure of interlayer and method for fabricating the substrate are proposed, which includes: providing an inner substrate including patterned conductive metal layers formed thereon and a plurality of first openings formed through the inner substrate; applying an insulated material layer onto the conductive metal layers and the first opening and then forming one or more second openings corresponding to each first opening, wherein the bottom of the second opening is lower than a top edge of the inner substrate, allowing to expose the metal wall of the first openings; and, forming an electroplating metal layer on the insulated material layer and the second openings to obtain build-up circuit layers after patterning. Accordingly, making vertical electrical connection between top and lower circuit layers via plating through holes (PTH, e.g. the first opening) instead of conductive vias can significantly reduce conductive pathway of signals. More particularly, adding conductive vias (e.g. the second opening) into the PTH (called ""via on hole"") of the present invention to decrease the amount of blind vias can further extend area of circuits layout of the packaging substrate to enhance reliability of circuits routing.

Description

1231552

FIELD OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor, and more particularly to a semiconductor (BGA) multi-layer semiconductor package substrate, which is connected to upper and lower circuit layers to improve activity. Packaging grid interlayer conductive structure and array type (Ball grid array, special interlayer conductive structure to conductive high-semiconductor packaging substrate layout smart [previous technology]: With the vigorous development of the electronics industry, electronic products have gradually entered multi-functional, High-performance research and development trends. In order to meet the packaging requirements of semiconductor packages with high integration and Miniaturization, for more active and passive components and circuit loading, semiconductor packaging substrates also Gradually evolved from a double-layer board to a multi-layer board (Uti-layer board). Uses inter-layer connection technology (I nter 1 ayerc 〇 n necti ο η) to expand the available circuit layout area on the semiconductor package substrate under limited workshops. In order to meet the needs of South Electronics ’density integrated circuit, the thickness of the package substrate is reduced to accommodate a larger number of circuits and components under the same unit area of the substrate. In response to microprocessors, chip sets, and graphics chips For high-energy chips such as AS semiconductors, the semiconductor package substrates with wires also need to be transferred. Chip signal, improving bandwidth, controlling impedance and other functions to achieve the development of the South I / 0 several packages. However, in order to comply with the development direction of semiconductor packages thin, short, versatile, high speed and high frequency, package substrate Has been developed towards fine lines and small apertures. The existing semiconductor package substrate manufacturing process has changed from the traditional 100 micron line size: including line width, line

17449 Quan 懋 .ptd Page 8 1231552 V. Description of the invention (2) The road space (Space) and aspect ratio (Aspect rat io), etc., have been reduced to less than 30 micrometers, and continue to research and develop towards smaller line accuracy. For the precision of wiring of semiconductor packaging substrates, the industry has developed _ Bui Id-up technology, that is, a core circuit board (core circuit board) surface using circuit build-up technology to stack multiple insulation layers and A conductive layer, and a conductive via is opened in the insulating layer for the electrical connection between the upper and lower layers. Among them, the circuit build-up process is the key to affecting the semiconductor package substrate circuit density. According to the current technology, the manufacturers mostly use the semi-additive method (Sap) to produce the circuit plating method (Pattern plating method). The circuit is detailed. Please refer to Figs. ^ To ^ 'The so-called semi-additive method provides a core circuit board 10' and forms an insulating layer n on the surface thereof. Laser drilling is used to form openings in the insulating layer n. The inner circuit layer 12 of the core circuit board 10 (as shown in FIG. 1A). Then ^^ a conductive seed layer is formed on the insulating layer 11 by electroless copper plating ... on the ^ seed layer 13-a patterned resist layer is applied! After 4 hours, electric ore is formed to form a patterned circuit layer 15 on the surface of the layer 13 (as shown in FIG. 1β). The resist layer 14 is separated and etched to remove the ^ seed layer 1 3 previously covered by the resist layer ^ (as shown in FIG. 1 c); so, using this 箄 = edge layer and layer layer, ie It is made into a substrate with a lot of lumens = step t. | Semiconductor encapsulation with circuit layers in addition In addition, as shown in Figures 2A to 2C, the circuit plating method also first provides a core circuit board 20, and the surface of the core circuit board 20 ^ ^ r pe * " φ forms a metal compression insulation layer such as resin-resin coated copper (RCC)

17449 Quan 懋 .ptd Page 9 12351552 V. Description of the invention (3) 2 1 'Using laser drilling and other methods to form openings 2 1 0 in the insulating layer 2 1, to connect the core circuit board 2 0 The inner circuit layer 2 2 (as shown in FIG. 2A) °, and then a conductive seed layer 23 is electrolessly plated on the insulating layer 21 having a thin metal layer, and a pattern is applied on the seed layer 2 3 The resist layer 24 is electroplated to form a patterned circuit layer 25 on the conductive seed layer 23 (as shown in FIG. 2B). After that, the resist layer 24 is peeled off for 14 more times to remove the seed layer 23 (as shown in FIG. 2C) under the resist layer 24, which was previously covered. Then, the above steps can be repeated to form the insulating layer and the build-up circuit layer to complete a semiconductor package substrate having a multilayer circuit layer. However, if a multi-layer semiconductor mounting substrate manufactured according to the aforementioned semi-additive method or circuit plating method is used, if the chip signal is to be transmitted from the uppermost layer to the lowermost layer of the semiconductor package substrate, the signal must be added from the uppermost layer to the circuit and the upper layer The conductive blind holes between the circuit layer and the upper circuit layers reach the core circuit board, and then pass through the plated through holes (PTT) inside the core circuit board, the conductive blind holes between the lower build-up circuit layers, and the lower build-up layer. The circuit layer 'reaches the bottom layer of the substrate. The signal transmission path is too long, which will easily increase the inductance and cause cross-talk or noise, which will damage the electrical transmission quality. θ Secondly, the traditional core circuit board manufacturing process is as shown in Figures 3 to 3D. First, β, such as a resin pressed copper box (Resinc 〇pper, RCC), is a pressed insulation layer 3 〇 〇, and drilled with a plurality of through holes 3 〇 2 (as shown in Figure 3 A and then copper plating and patterning process to form the inner layer circuit layer 3 0 3 on the surface of the insulating layer 3 0 0 and A metal layer is deposited on the wall of the through hole 3 02 (as shown in FIG. 3B), and is filled with a conductive or non-conductive layer.

17449 Quan 懋 .Ptd Page 10 1235552 V. Description of the invention (4) Filling material 31 (such as insulating ink or copper-containing conductive paste) to fill the remaining space of 30 2 to form a plated through hole (15 (1 { 1) 302 is similar to the inner circuit layer 30 of the upper and lower surfaces of the insulating layer 300, and then the redundant filling material 31 is removed to maintain the core circuit board circuit surface (as shown in Figure 3C). However, the core circuit board In the manufacturing process, there are more plug holes and brushing to raise the manufacturing cost of the substrate. It is particularly important a. The core circuit board has most plated through holes, which often leads to the formation of patterned circuit layers on the core circuit board and the increased circuit layer formed. At the same time, the through hole must extend out of the pad space to form a conductive via. This not only wastes the substrate wiring area and miniaturizes the packaging trend, but also affects the substrate because of the need to avoid the electrical location during the circuit layout. Flexibility in the use of space.

[Summary of the invention]: X # The disadvantages of the conventional technology described above. The main purpose of the present invention is to provide an interlayer conductive structure of a semiconductor package substrate and to increase the circuit layout area of the package substrate and increase the interlayer circuits. Layout flexibility Another object of the present invention is to provide a conductive structure between semiconductor packages and a manufacturing method thereof, which directly plug holes through an insulating layer; an ink plug hole and a brushing process in a core circuit board manufacturing process; Wire $ μ ® t μ 5 gold degrees to avoid interfacial peeling Another object of the present invention is to provide a semi-enclosed conductive structure and its manufacturing method '# to shorten the conductive blind hole wiring space' The electrical conduction brush grinding process of the through hole The flatness process surface forms the self-plating guide on the lower surface, which is not conducive to the plating of the vias. The purpose is to make the method by using the circuit (the substrate layer instead of the conventional south insulating layer.

17449 全懋 .ptd Interlayer of substrate

1231552 V. Description of the invention (5) The conductive blind hole plating layer and the plated through hole form a better electrical connection relationship. Another object of the present invention is to provide an interlayer conductive structure of a semiconductor package substrate and a manufacturing method thereof, thereby shortening a signal transmission path to avoid crosstalk and noise, and further improve the electrical quality of the semiconductor package substrate. To achieve the above and other Purpose, the present invention discloses an interlayer conductive structure of a semiconductor package substrate, including: an inner layer substrate on which an inner layer circuit layer and a plurality of plated vias penetrating through the inner layer substrate are formed; and an insulating layer formed on the inner layer circuit layer. On the surface and in the plated through hole, the insulating layer corresponding to at least a part of the plated through hole is formed with an opening having a hole bottom lower than the top edge of the inner substrate, and the hole wall metal layer of the plated through hole is exposed outside; and The patterned metal layer is formed on the surface of the insulating layer and in the opening. The invention also discloses a method for manufacturing an interlayer conductive structure of a semiconductor package substrate, which includes: providing an inner layer substrate, and a plurality of inner layer substrates are formed through the inner layer substrate. An electroplated via hole on the surface, and an inner layer circuit layer is formed on the inner substrate surface; An insulating layer is formed on the inner layer substrate and in the plated via hole, and the insulating layer corresponds to at least a part of the plated via hole, and a hole wall metal layer is formed to expose the plated via hole outside the opening; and the insulating layer is formed on the insulating layer; A patterned metal layer is formed on and in the opening. The patterned metal layer on the insulating layer and in the opening can be formed by forming a conductive film on the surface of the insulating layer and the opening, and then forming a patterned electrical clock resistance layer on the conductive film. Formed by electric key. Subsequently, the insulating layer and the patterned metal layer can be repeatedly stacked to form a multilayer semiconductor package.

17449 懋 .ptd Page 12 1231552 V. Description of the invention (6) Mount the base plate. In the present invention, a plated through hole is formed in the inner substrate to replace the conductive vias to conduct vertical conductive connections between different circuit layers, which can shorten the signal conduction path and make the upper circuit layer The signal can be directly transmitted to the underlying circuit layer through the patterned metal layer and the plated through hole formed in the insulating layer. Helmet = external wiring of the electrical blind hole and reducing the amount of conductive blind hole setting, thereby expanding the circuit layout of the substrate. The area makes the circuit layout more flexible. ^ Using plated vias for signal transmission between layers, in addition to shortening and reducing inductance, crosstalk, and noise generation, it is also necessary to implement the ink plugging and brushing process at & 2 to reduce costs; and =: The use of the same insulating layer can further improve the bonding strength between the interfaces of the insulating material ^^ and the vias of the base hole, and avoid the reliability of the interface ^ = ore guide plate. The k-liter packaging base [Embodiment]: The following is explained through specific embodiments. A person skilled in the art can be disclosed by this description: the embodiment of the clear solution to other advantages and effects of the present invention. The present invention also easily implements or applies the J-system embodiment. In the description of this article, it is based on different viewpoints and applications, and can be modified and changed without departing from the details. Under the spirit of Beiyue, all kinds of the following are shown in Figures 4A to 4m, the interlayer conductive structure of the substrate and the semiconductor package of the present invention. The drawings are all good examples. • In the need to note the unintended intention, only a schematic illustration

17449 Quan 懋 .ptd Page 13 1231552 V. Description of the invention (7) The substrate structure of the present invention. However, these drawings only show the elements related to the present invention. The elements shown are not the actual implementation. The number, shape and size ratio of the actual implementation are an optional design. The layout pattern may be more complicated. As shown in FIG. 4A and FIG. 4B, first, at least one inner layer board 40 having a thin metal layer formed on its surface is provided. The inner layer board 40 may be a single-layer or multi-layer circuit board with pre-processing completed. In the diagram of this embodiment, the inner layer board 40 is composed of an insulating layer 400 and a thin metal layer 4 01 formed on the surface of the insulating layer 400, and the inner layer is mechanically drilled. A plurality of first openings 4 2 (see FIG. 4B) penetrating the substrate are drilled on the plate 40. Wherein, the insulating layer 400 may be epoxy resin, polyimide, cyanate ester, glass fiber, bismaleimide / triazine (Bismaleimide Triazine, BT) or FR5 material mixed with epoxy resin and glass fiber; the thin metal layer 401 is generally based on copper (Cu), which has better conductivity, as a wire material for signal transmission, and The thin metal layer 401 can be first laminated or deposited on the insulating core layer, or made of resin-coated copper (RCC), because it effectively provides the adhesion of the subsequent electroplated metal layer. A good specific embodiment is that before the thin metal layer 401 is deposited, the surface of the insulating layer 401 must be roughened in advance. At the same time, this embodiment uses a resin pressed copper foil (RCC) as an example for illustration. . As shown in Figure 4C, next, physical vapor deposition (PVD), chemical vapor deposition (CVD), electroless plating, or chemical deposition are used, such as sputtering, evaporation, and arc vapor deposition. (Arc

17449 Quan 懋 .ptd Page 14 1235552 V. Description of the invention (8) vapor deposition), ion beam sputtering, laser ablation deposition, plasma-assisted chemical vapor deposition or No electroplating or the like, so that a conductive layer (not shown) is formed on the surface of the inner layer plate 40 and the first opening 4 02, and the conductive layer is used as a current conduction path to form a surface on the inner layer plate 40 And a conductive metal layer 403 with sufficient thickness is formed on the wall of the first opening 40 2 by electroplating. As shown in FIG. 4D, a photoresist layer (not shown) is formed, and processes such as Exposure, Development, and Etching are performed to make the conductive metal layer 40. 3 patterning, and an inner layer circuit layer 4 0 3 a is formed on the upper and lower surfaces of the inner layer plate 40, and a keyed through hole (PTH) 40 2 a is formed in the first opening 402, An inner substrate 40a is formed. As shown in FIG. 4E, an insulating layer 41 is formed on the inner substrate 40a, so that the upper and lower surfaces of the inner substrate 40a and the inner circuit layer 403a are covered by the insulating layer 41, respectively. The insulating layer 41 is filled into the remaining space in the plated through hole 40 2 a. The insulating layer 41 may be, for example, ABF (Ajinomoto Build-up Film, trade name, manufactured by Ajinomoto Co., Ltd.). As shown in FIG. 4F, then, a laser process, such as a C0 2 laser or an ultraviolet laser, is used to open a first portion of the insulating layer 41 corresponding to at least a part of the plated through-hole 4 0 2 a. Two open holes 4 1 0, the conductive metal layer of the plated through hole 4 2 a hole wall is exposed outside, wherein the bottom edge of the bottom of the second open hole 4 1 0 is lower than the top of the inner substrate 4 0 a And the bottom of the second opening 4 1 0 is set below the top edge of the inner substrate 40 a and does not pass through the inner layer base

17449 全懋 .ptd Page 15 1231552 V. Description of the invention (9) Board 40 # is limited. As shown in FIG. 4G, next, a patterned circuit build-up process is performed, which can first form a conductive film 4 and a patterned plating resist layer 412 on the insulating layer 41. The conductive film 411 is mainly described later. The current conducting path 'required for the electroplated metal layer can be composed of metal, alloy, or stacked metal layers, and can be formed remotely from a group of metals consisting of copper tin, copper, copper, copper, copper, and copper alloys. The conductive film 411 can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), electroless plating, or chemical deposition, such as sputtering, evaporation, and arc vapor deposition (Arc It is formed by methods such as vapor deposition, ion beam sputtering, laser ablation deposition, plasma-assisted chemical vapor deposition, or non-electric bonding. However, according to practical experience, the conductive film 4 1 1 is preferably composed of electroless copper-plated particles. As shown in FIG. 4, the electroplating method is used to form an electro-mineral metal layer 4 2 a in the opening of the patterned plating resist layer 4 1 2, and then the electrical clock resist layer 4 1 2 is removed and covered thereunder. The conductive film 41 is formed in the insulating layer 41 of the inner substrate 40a and the second opening 410 to form a patterned metal layer. The patterned metal layer includes a first build-up layer on the surface of the insulating layer 41. First build-up circuits layer 4 2 and an electroplated metal layer 4 2a filled in the second opening 410. As shown in FIG. 4I and FIG. 4J, a dielectric insulating layer 43 can be formed on the first build-up circuit layer 42, and at least one blind can be formed in the dielectric insulating layer 43. The exposed part of the hole 430 (Via) is an additional layer of the circuit layer 42,

17449 Quan 懋 .ptd Page 16 1235552 V. Description of the invention (ίο) The dielectric insulating layer 43 may be, for example, ABF (A ji η 〇m 〇t ο B ui 1 d-upfi 1 π〇, epoxy resin ( Epoxy Resin), Cyanate Ester, Glass Fiber, Bismaleimide / Bismaleimide Triazine (BT), or a mixture of epoxy resin and glass fiber It can be formed by laser or mechanical drilling and other blind holes 430. Of course, it is also possible to form an insulating layer with a thin layer of metal (such as resin laminated copper) on the first layer layer. Foil), and blind holes are formed by laser or mechanical holes. 'The stomach is shown in Figure 4K, and then patterned circuit layering is performed again' for the dielectric insulating layer 43 and the blind holes. A second build-up circuit exhibition king 4 4 and a conductive blind hole 4 3 0 a are formed on 4 3 0, so that the conductive blind hole 4 3 0a can electrically conduct the first build-up circuit layer 42 and the second build-up layer. Line layer 4 4 and the completion of the build-up line = of course. Of course, the build-up process can also be continued to form a two 'multi-line structure. ^ The above-mentioned patterned circuit layer-adding process is only for illustration, and is not intended to limit the application scope of the present invention, which will be described first. Finally, as shown in FIG. 4L, the second layer-added circuit can be used. As a protective layer, a solder mask 45 is used as a protective layer. The solder resist 45 has a plurality of openings, and the second build-up circuit layer 44 is exposed to form a multilayer semiconductor package substrate (this The embodiment is a six-layer board of 2 + 2 + 2). The interlayer conductive structure of the semiconductor package substrate of the present invention, as shown in the figure, includes: an inner substrate 40a on which an inner circuit layer 4 0 3 a is formed. And most of the recording vias 4 〇 2 a penetrating the inner substrate 4 0 a;-an insulating layer filled on the inner circuit layer 403 a and the plating vias 4 02 a

1231552 V. Description of the invention (Η) 4 1 (such as ABF), the insulating layer 41 corresponds to at least a part of the plated-through hole 4 () 2a, and a hole bottom is formed at a second lower than the top edge of the inner substrate 40a. The opening 4 1 0 can expose the metal layer of the plated through hole 4 2 a through the opening of the second opening 4 1 0; and a patterned layer formed on the surface of the insulating layer 4 1 The circuit layer 4 2 and the plated metal layer 4 2 a in the second opening 4 10. In addition, FIGS. 5A to 5D show another preferred embodiment of the interlayer conductive structure and manufacturing method of the semiconductor package substrate of the present invention. However, the structure and manufacturing method of this embodiment are substantially the same as those of the previous embodiment, and the difference lies in the formation of the first opening, not only on one side of the substrate, but also on both the front and back sides of the package substrate. As shown in FIG. 5A 'First, an inner layer substrate 5 0 a buried in an insulating layer 5 丨 is prepared, and a plurality of key vias 5 0 2 a are formed in the inner layer substrate 5 0 a and within the holes. Fill the insulation layer 51. The upper and lower sides of the insulating layer $ 1 correspond to the plated through holes 5 0 2a, and techniques such as c02 laser or ultraviolet laser are used, and the insulating layer 51 corresponds to at least a part of the electrical conduction A first opening 5 1 0 is opened at the hole 5 0 2 a. The electric ore via 5 is exposed to the outside. The conductive metal layer of the hole wall is where the bottom edge of the second opening 51 is 0. The lower edge of the inner layer substrate 50 a is nearer, and the bottom of the second opening 5o0 is set below the edge of the inner layer substrate 50a without passing through the inner layer substrate 50a. As shown in FIG. 5B, the patterned circuit layer-adding process is performed next, which can use an additive method to first form a conductive film and a patterned electrical keying resistance layer on the insulating layer & 1. (Not shown), and then use the electroplating method to form a key metal layer '俾 to form a first build-up circuit layer on the inner substrate 50a

17449 Quan. Ptd Page 18 1231552 V. Description of the Invention (12) 52 (First build-up circuits layer) ’At the same time, the second opening 51 0 is filled with a plated metal layer 52a. As shown in FIG. 5C, a dielectric insulating layer 53 is formed on the first build-up circuit layer 52, and the dielectric insulating layer 5 is provided with a blind hole 530. Layer 52, and a blind hole 5 3 0 can be formed by a technique such as laser drilling. Of course, an insulating layer with a thin metal layer can also be formed on the first build-up circuit layer 52, and a blind hole can be formed by laser drilling technology. As shown in FIG. 5D, after that, the step of adding layers is repeatedly performed to form one or more build-up structures on the inner substrate 50a and the lower side, respectively. The conductive blind hole 53a is electrically connected to the wiring structure between adjacent layers, and then is covered with a solder resist layer 55 to obtain a multilayer semiconductor package substrate. In the present invention, the first hole 'such as a plated through hole (Plating thruugh) is formed in the hole wall of the inner substrate with a conductive metal layer, instead of the conductive blind hole ^ (: 〇! 1 (111 (: 1: ^ 6 乂 丨 3) to carry out vertical guide connection between different circuit layers. The signal on the upper layer of the package substrate can directly pass through the inner substrate = the second opening, the inner circuit and the second opening on the lower part of the inner substrate; connect to the opposite side (That is, compared with the inner semiconductor fi σ ^ 叩 r opening the semiconductor layer on the other side of the conductive layer substrate and the dream semiconductor substrate), compared with the aforementioned sinus 竑 $ 丄 to 可 攻 + # β A 4 + example, it can shorten the signal conduction more effectively. The path, the electrical quality of the substrate, is wrong to enlarge the package substrate circuit lining and achieve it again, through the purpose of the inner layer. (ConductlVe via) to enter the gate electricity mine through hole ^^ Instead of conductive blind holes (can shorten the signal conduction path, the vertical conductive connection between the circuit layer, i 'enables the signal of the upper circuit layer to be directly selected

1231552 V. Description of the invention (13) The second opening in the upper part of the inner substrate, the inner circuit layer and the second opening in the lower part of the inner substrate quickly lead to the bottom of the package substrate. Holes to expand the circuit layout area of the package substrate and make the circuit layout more flexible. In addition, the use of plated vias for signal transmission between layers not only shortens the conductive path, reduces inductance, crosstalk, and noise generation, but also eliminates the need to implement ink plugging and brushing processes to reduce costs when making the inner substrate; and circuits The surface and the plug hole are covered with the same insulation layer or the hole wall circuit layer is fully plated with metal, which can improve the bonding strength between the insulation material and the interface between the circuit layer and the plated through hole, avoiding interface peeling, and improving the reliability of the package substrate. Sexual purpose. The previous disclosure steps of the present invention are not limited to the methods described in the embodiments. Equivalent replacement steps of other substrate manufacturing processes, equipment, or materials, such as replacing layers by hot pressing or changing the number of layers of multilayer packaging substrates, are also included in this document. The scope of the invention. The above-mentioned embodiments are merely illustrative for explaining the principle of the present invention and its effects, and are not intended to limit the present invention. Anyone skilled in the art can modify and change the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application mentioned later.

17449 Quan 懋 .ptd Page 20 12351552 Simple illustration of the drawings [Simplified illustration of the drawings]: Figures 1A to 1C are schematic diagrams of the conventional semi-additive semiconductor package substrate manufacturing process; Figures 2A to 2C FIG. 3A is a schematic diagram of a conventional manufacturing process of a semiconductor package substrate by a circuit plating method; FIGS. 3A to 3D are schematic diagrams of a manufacturing process for forming an inner-layer substrate plating via hole by a conventional ink plugging method; FIGS. 4A to 4L are the present invention A cross-sectional view of a first embodiment of a method for manufacturing an interlayer conductive structure of a semiconductor package substrate; and FIGS. 5A to 5D are cross-sectional views of a second embodiment of a method for manufacturing an interlayer conductive structure of a semiconductor package substrate of the present invention. 10.20 Core circuit board 11.21 Insulation layer 110,210 Opening hole 12.22 Inner circuit layer 13, 23 Seed layer 14.24 Resistive layer 15.25 Patterned circuit layer 3 0 0, 4 0 0 Insulation layer 3 0 2 Through hole 3 0 2a Plating through hole 3 0 3 Inner circuit layer 31 Filling material

17449 懋 .ptd page 21 1231552

Brief description of the drawing 40 Inner plate 40a, 50a Inner substrate 401 Thin metal layer 402 First opening 402a, 502a Plating via 403 Conductive metal layer 40 3a Inner circuit layer 41, 51 Insulating layer 410, 510 Second opening 411 Conductive Film 412 Plating resist layer 42, 52 First layer circuit layer 42a, 52a Plating metal layer 43, 53 Insulating layer 43 0, 5 3 0 Blind hole 430a, 530a Conductive blind hole 44 Second layer layer 45, 55 Flux layer 17449 Full 懋 .ptd Page 22

Claims (1)

1231552 VI. Application Patent Scope 1. A method for manufacturing an interlayer conductive structure of a semiconductor package substrate, which includes providing an inner layer substrate. The inner layer substrate has a plurality of plated vias 5 formed therein and an inner layer circuit layer is formed on the inner substrate surface; Forming an insulating layer on the inner layer substrate and in the plated through hole, and the insulating layer corresponding to at least a part of the plated through hole is formed with a hole wall metal layer outside the opening to expose the plated through hole; and the insulating layer A patterned metal layer is formed on and in the opening. 2. For example, the method for manufacturing an interlayer conductive structure in item 1 of the patent scope, wherein the patterned metal layer on the insulating layer and in the opening can be formed by sequentially forming an insulating layer and a surface of the opening. The conductive layer and a patterned plating resist layer are formed by electroforging. 3. Please refer to the patent for the manufacturing method of the interlayer conductive structure in item 1, wherein the inner substrate comprises a multilayer board structure composed of an insulating core layer and at least one layer of circuit patterns formed on the surface of the insulating core layer. 4. The method for manufacturing interlayer conductive structure in item 1 of the patent scope, where the insulating layer is ABCCA. Ji η 〇m 〇t 〇Build-up Film) 0 5. The layer in the scope of patent application 1 A method for manufacturing a conductive structure, wherein the opening is provided on one side of the inner substrate: the board. 6. If so, please patent the manufacturing method of the interlayer conductive structure in the first range, wherein the opening 5 is placed on both sides of the inner substrate: the board. 7. Please refer to the patent for the method for manufacturing the interlayer conductive structure in item 1, where the bottom of the opening is lower than the near edge of the inner β-layer substrate, and the limit is not passed through the inner substrate. 17449 Quan 懋 .ptd Page 23 12351552 6. Application for Patent Scope 8. For the method of manufacturing the interlayer conductive structure in the scope of patent application item 1, wherein the opening is formed by laser drilling technology (Laserdri 1 1 ing) . 9. For the method for manufacturing an interlayer conductive structure according to item 8 of the patent application, wherein the laser is a C02 laser. 10. The method for manufacturing an interlayer conductive structure according to item 8 of the scope of patent application, wherein the laser is an ultraviolet laser. 11. The method for manufacturing an interlayer conductive structure according to item 1 of the application, wherein the patterned metal layer can be repeatedly stacked with an insulating layer and a patterned metal layer to obtain a semiconductor package substrate with a multilayer circuit. 1 2. An interlayer conductive structure of a semiconductor package substrate, comprising: an inner layer substrate on which an inner circuit layer and a plurality of plated vias penetrating through the inner substrate are formed; an insulating layer formed on the surface of the inner circuit layer And the electrical vias, the insulating layer corresponding to at least a part of the plated through holes is formed with an opening having a hole bottom lower than the top edge of the inner layer substrate, and the hole wall metal layer of the plated through holes is exposed outside; and The patterned metal layer is formed on the surface of the insulating layer and in the opening. 13. The interlayer conductive structure according to item 12 of the scope of patent application, wherein the inner layer substrate comprises a multilayer board structure composed of an insulating core layer and at least one circuit pattern formed on the surface of the insulating core layer. 14. The interlayer conductive structure according to item 12 of the patent application scope, wherein the insulating layer is an ABF (Ajinomoto Build-up Film). 15. The interlayer conductive structure according to item 12 of the patent application scope, wherein the opening 17449 全懋 .ptd Page 24 1231552 6. Scope of patent application The hole is set on one side of the inner substrate. 16. The interlayer conductive structure according to item 12 of the patent application scope, wherein the openings are provided on both sides of the inner layer substrate. 1 7. The interlayer conductive structure according to item 12 of the patent application scope, wherein the hole bottom of the opening is lower than the nearer edge of the inner layer substrate, and the one that does not pass through the inner layer substrate is limited. 18. The interlayer conductive structure according to item 12 of the scope of patent application, wherein the openings are formed by laser drilling technology (Las er d r i 1 1 i n g). 19. The interlayer conductive structure according to item 18 of the scope of patent application, wherein the laser is a C02 laser. 20. The interlayer conductive structure according to item 18 of the patent application scope, wherein the laser is an ultraviolet laser. 2 1. The interlayer conductive structure according to item 12 of the scope of the patent application, wherein the patterned metal layer can be repeatedly stacked with an insulating layer and a patterned metal layer to obtain a semiconductor package substrate with a multilayer circuit. 17449 懋 .ptd Page 25