TW200539772A - Circuit board with multi circuit layers and method for fabricating the same - Google Patents

Abstract

A circuit board with multi circuit layers and a method for fabricating the same are proposed, wherein a plurality of core substrates formed with metal layers on the surfaces thereof are provided. A plurality of vias are formed on one surface of the core substrate to expose the metal layer on the other surface of the core substrate. A first circuit layer and a plurality of conductive vias are formed on the surface of the core substrate with vias formed thereon by a pattern process. A multi-layer circuit board is formed by integrating the core substrates with an insulating layer formed between the core substrates on their surfaces having conductive vias. After a plurality of holes are formed in the multi-layer circuit board, a second circuit layer and a plurality of conductive holes are formed on the multi-layer circuit board by a pattern process, wherein a plurality of pads are defined in the second circuit layer and at least a pad is formed on the bottom end of the conductive via, so as to improve the layout flexibility and area.

Description

200539772 V. Description of the invention (1)-[Technical field to which the invention belongs]: The present invention relates to a circuit board with multi-layer circuit layers and a method for manufacturing the same, especially a multi-layer circuit with improved wiring space and flexibility. Layered circuit board and its manufacturing method. [Previous technology]: With the vigorous development of the electronics industry, electronic products have gradually been selected for multi-function, high-performance research and development trends. To meet the high accumulation of semiconductor packages (

Integration and Miniaturization packaging requirements for more active and passive components and circuit connections, the circuit board has also gradually changed from single-layer board, double-layer board > 臾 to multi-layer board, 俾In a limited space, the use of interlayer connection technology (I nter 1 ayerc ο η necti ο η) to expand the available circuit layout area on the circuit board, so as to meet the needs of integrated circuits , Reduce the thickness of the circuit board 'to accommodate a larger number of circuits and components under the same circuit board unit area. In addition, in response to the calculation of high-performance chips such as microprocessors, chip sets, and graphics chips, circuit boards with wires also need to improve their functions of transmitting chip signals, improving bandwidth, and controlling impedance to achieve high 丨 / 〇number packages. Development. However, in order to meet the development trend of thin and short, versatile, high-speed and high-frequency semiconductor packages, circuit boards have been developed towards fine lines and small apertures. Therefore, in order to improve the wiring precision of the circuit board, the industry has developed a build-up technology (B ui 1 d-up), that is, a multi-layer insulation layer is alternately stacked on the surface of a core circuit board using the build-up circuit technology. And line

200539772 V. Description of the invention (2) Road layer 'and a conductive via (Conductive via) is provided in the insulation layer to provide electrical connection between upper and lower lines. Among them, the circuit overlay process is the key to affecting the circuit density of the circuit board. According to the current technology, the industry mostly uses the semi-additive process (SAP) and the pattern plating method to make the circuit overlay. Please refer to Figures 1A to 1C. The so-called semi-additive method provides a core circuit ^ gr plate 10 and forms an insulating layer Π on the surface. The laser drilling (Lab dr i 1 1 i ng) is used. An opening is formed in the insulating layer 11 to connect the inner circuit layer 12 of the core circuit board 10 as an electrical conductive pad 16 for electrical conduction (as shown in FIG. 1A). . Next, an electrical layer 13 is formed on the insulating layer 11, and a patterned resistive layer 14 is applied on the conductive layer 13 and then plated to form a patterned circuit layer on the conductive layer 13. 1 5 (as shown in number 1). After that, the resist layer 14 is peeled off and the previously covered resist layer 1 4 is removed. The conductive layer 1 3 (as shown in Fig. 1 C) is used. In this way, these steps are used to re-form the insulating layer and increase the thickness. Layer circuit layer, that is to make an electric board with multiple circuit layers

In addition, as shown in FIGS. 2A to 2C, the circuit plating method also first provides a 〆γ core circuit board 20, and forms a coating such as tree chest copper (RCC) on the surface of the core circuit board 20. The insulating layer 2 1 with a metal layer 21 is pressed, and then an opening 2 1 0 is formed in the insulating layer 2 H by using laser drilling or the like, so as to communicate with the inner circuit layer 2 2 of the core circuit board 20 Electrically connected electrical connection pads 2 6 (as shown in Figure 2A). A conductive layer 2 3 is formed on the insulating layer 2 1 covered with the metal layer 2 1 1, and a patterned resistive layer 24 is applied to the conductive layer 2 3 to perform electric power for the tooth.

17661 Full 懋 .ptd

200539772 (3) patterned 2 4 and removed). The connection layer, the aforementioned conventional insulation layer, forms a layered connection pad in a plurality of boards, and the connection pad and the conductive structure. 'Experienced technology of external circuit layer mounting Zhao Shizhi and the circuit with conductive plate V. Invention description layer 2 3 The distance from the resistive layer shown in Figure 2C and the build-up line are formed, but the way is to form an I-hole and the conductive circuit is more laid These electrical layers are connected to each other. Therefore, the miniaturization of the circuit board occupies space and affects the circuit. Line layer 2 5 (as shown in Figure 2B). After that, the part of the metal layer previously covered under the resistive layer 24 is peeled off (as described above, the above steps can be repeated to form an insulating layer element to form a circuit board with multiple circuit layers. The processes are all used on the core circuit board such as compression bonding After that, on the same side of the insulating layers, through the laser eye holes, a plurality of conductive blind holes are formed afterwards to electrically connect the circuit structure. However, this requires an additional 16 or 2 6 to support the The conductive blind hole, through the connection of the electrical blind hole, to call the circuit board internally not only increases the amount of electrical connection pads, waste, and other wiring surface wiring area, in addition to being unfavorable, it will also be in the circuit layout When it is affected by the electrical connection pads corresponding to the blind holes of the conductive blind holes, the wiring density is also not conducive to the flexible wiring of the circuit board. After the + ice is formed on the conductive blind holes on the outer layer of the circuit board, an electrical connection is formed. Pad, and then wiring to connect the electrical connection pad to another electrical connection inner layer circuit. The electrical connection pad of Shishi accepts a conductive blind hole to electrically connect to connection i to undertake :: making = complicated, J • Required Provided electrically connected to multi-line help enhance the spirit ^ ^ ^ to the process steps and cost, some not te-based conductive vias generally increase the electrical circuit layer towards the core

200539772 V. Description of the invention (4) The circuit board is opened, and the conductive blind hole needs to be filled with a copper-like material in order to provide the electrical connection of the subsequent wiring of the circuit board. This will use more materials to improve Manufacturing cost and process steps of circuit boards. [Summary]: In view of the shortcomings of the conventional technology described above, the main object of the present invention is to provide a circuit board with multiple circuit layers and a method for manufacturing the same, thereby increasing the layout area of the circuit board circuit, thereby improving the flexibility of circuit layout. . Another object of the present invention is to provide a circuit board with multiple circuit layers and a manufacturing method thereof, thereby reducing costs. In order to achieve the above and other objectives, the present invention discloses a circuit board having a plurality of circuit layers. The circuit board includes a plurality of core layer boards, and a first patterned circuit layer and a plurality of conductive blind holes are formed on one surface of the layer board. A second patterned circuit layer is formed on the other surface of the core layer board; at least one insulating layer is sandwiched between the first patterned circuit layer and the conductive blind hole of the core layer boards; and most are formed The conductive vias in the core boards are electrically connected to the core boards. Wherein, the second patterned circuit layer of the core board has a plurality of electrical connection pads, and at least one of the electrical connection pads can selectively correspond to a conductive blind hole on the same side of the first patterned circuit layer of the core board. At the bottom, in addition, the conductive vias may be plated through-hole structures that penetrate through most of the core boards, or a conductive blind hole structure that partially penetrates through most of the core boards. In addition, an insulation layer and another circuit board may be spaced between each of the core layer boards to be connected to each other. The manufacturing method of the circuit board with multi-layer circuit layers of the present invention includes: providing a plurality of core board, a metal layer is formed on the surface of the core board; and the core board

17661 Quan 懋 .ptd Page 12 200539772 V. One of the descriptions of the invention There are electrical blind holes in the exposed metal layer of the surface layer; the layers are mutual holes; the on-going circuit is formed and there are insulation holes in this interval. The line of the board is therefore formed with the bottom diameter of the other side of the electric blind hole in the complex thinking, to avoid the connection to the undertaking step and complex. The area of the electrically conductive blind hole layout of the road layer (5) is formed in the blind hole. The bonding-shaped circuit_two pattern layers have a core layer, a plate edge layer and a conductive circuit layer. 'The conductive blind plate of this hair board has multiple terminals, which can be used to remove conductive holes, and the connection of the present invention.' Also, a plurality of blind holes are formed at the bottom end of the hole to form a core board. Multi-layer circuit board manufacturing process, circuit layer and multiple electrically conductive conductive blind holes. Another circuit board blind hole or electroplating has multiple holes formed on one side. One side is clamped electrically. At the same time, the blind hole opening avoids the direct installation space of the multi-layer wire pads and the opening of the south circuit board so that the line is first conductive: the plural leads are connected to the bottom. The core layers are patterned with patterned blind holes. The multilayer boards are multi-layer board electrical vias and, at least in addition, are connected to the board by another table process, with the circuit layer and one side spaced apart on the surface, where the An electrical connection is made with the core layer board, and the gold of the electrical conductive surface has a plurality of insulating conductors and through-holes in the core. The second figure of the pad system can electrically conduct the cores and the circuit of the circuit layer. The board and its manufacturing method can be provided with electrical blind holes, then an insulating layer is placed on the circuit boards, and then the patterned circuit layer of the pad of the circuit board is used to make the direct electrical conduction path of the conductive connection pad steeply connected. Extra wiring throughout to connect it to f = to reduce the wiring layout space for the process. = ^ 'S circuit board and its manufacturing method system line :: 电!孔 底 #, and no need to consider, in order to increase the flexibility of circuit layout of the circuit board,

17661 Quan 懋 .ptd Page 13 200539772 V. Description of Invention (6) All kinds of missing technologies. Furthermore, the circuit board with multi-layer circuit layers and the manufacturing method of the present invention can perform vertical electrical connection of each circuit layer of the circuit board without additional electrical connection pads for receiving with the conductive blind holes ^. The amount of electrical connection pads is reduced to reduce the cost of the process. ^ The present invention is not limited by the space occupied by the conductive blind hole openings, thereby expanding the layout area of the outer layer of the circuit board and making the layout more flexible. In addition, when patterned circuit layers and electrical connections are formed on the bottom surfaces of the conductive blind holes of the two circuit boards, there is no need to fill the conductive blind holes with a filler material such as copper, which further reduces the cost of the process and reduces the number of process steps. . '[Embodiment]: The following familiarity with the specific implementation of the present invention can also be based on various electric circuits such as the road reference layer. By point and function or should point and should be changed. The best schematic diagram of Figure 3J is only implemented in a mixed scale. The other advantages of the person skilled in the 3B map are applied to different perspectives. Modifications and changes can be made from the 3A to the board method. However, these parts are not actual and the dimensions can be further reproduced. Figure 3 A and the first embodiment illustrate the embodiments of the present invention. The contents disclosed in this specification are easily effective. The present invention can also be used to illustrate the embodiments of the present invention by using other different uses, that is, the various uses in this specification, without departing from the spirit of the present invention. Among them, it is necessary to pay attention to the "layer;" only to schematically illustrate the elements of the present invention that are related to the present invention, their current state, and the actual implementation of the & a selective design, and the component layout As shown, first, a plurality of core boards 3 are provided,

200539772 V. Description of the invention (7) 3 1, the core board 3 0, 3 1 is formed with a metal layer 3 0 1, 3 11 'on the surface and is laser-drilled to the core board 3 0, 3 A plurality of blind holes 3 0 2 and 3 1 2 are drilled in 1 (as shown in FIG. 3B), so that the bottom end of the blind hole 3 0 2, 3 1 2 exposes the other surface of the laminate 30, 31. Of metal layers 301, 311. Wherein, the insulating part of the core board 30, 31 may be epoxy resin, Polyimide, Cyanate Ester, glass fiber, and bismaleic acid. It is made of imine / triazine (Bismaleimide Triazine, BT) or FR 5 material mixed with epoxy resin and glass fiber. The metal layer 301 is generally copper (Cu) with better conductivity, and the metal layer 3 0 1, 3 1 1 can be laminated or deposited on the insulating core layer, or a resin or laminated copper is used. Resin coated copper (RCC) is formed. As shown in Figure 3C, physical vapor deposition (PVD), chemical vapor deposition (CVD), electroless plating, or chemical deposition technologies are selected, such as sputtering, evaporation, and arc vapor deposition ( Arc vapor deposition), Ion beam sputter i ng, Laser ablation deposition, plasma-assisted chemical vapor deposition or electroless plating, etc. A conductive layer (not shown) is formed on the surface of the blind holes 302, 31 2 and the blind holes 302, 31 2 as a current conduction path, and the core plate 30, 31 is formed by an electroplating process. An electroplated metal layer 3 0 3, 3 1 3 with a sufficient thickness is formed in the surface metal layer 301 and the blind holes 3 0 2, 3 1 2. Then, a patterning process of the electroplated metal layer 3 0 3, 3 1 3 is performed on one side of the core layer plate 3 0, 31 by forming a blind hole 3 0 2, 3 1 2, and the like. A first patterned circuit layer 303a, 313a and conductive blind holes 302a, 312a are formed on one surface of the core board 30, 31.

17661 Quan 懋 .ptd Page 15 200539772 V. Description of Invention (8) As shown in Figure 3D. Of course, the aforementioned circuit patterning process can also be formed by electroplating. After forming the conductive layer, a patterned plating resist layer (not shown) can be covered and electroplated to form the first patterned circuit layer 303a, 313a and conductive The blind holes 3 0 2 a, 3 1 2 a, and then the plating resist layer and the conductive layer covering it are removed. As shown in FIG. 3E, an insulating layer 3 is sandwiched between the core layer boards 30, 31 on which the first patterned circuit layers 3 0 3a, 31 3a and the conductive blind holes 30 2a, 31 2a are formed on the surface. 5. The insulating layer 35 may be relatively bonded to the core layer boards 30, 31 by hot pressing, coating, or other appropriate methods, and a first patterning may be formed in the layer boards 30, 31. The surfaces of the circuit layers 3 0 3a and 313a are covered by the insulating layer 35. At the same time, the insulating layer 35 is filled into the conductive blind holes 302a and 312a to form a multilayer board, as shown in FIG. 3F. Show. Ganzhong 'the insulating layer 3 5 may be, for example, an ABF (A ji η 〇m 〇t ο B ui 1 d ~ up F i 1 m, trade name' produced by Shang Wei Zhi Su Co.) layer, of course, the insulating layer 35 It is also possible to use other insulating materials with different characteristics instead of the ones described in this embodiment. * As shown in FIG. 3G, a plurality of through holes of the multilayer board are drilled in the completed multilayer board by, for example, mechanical drilling. The hole wall of L 32 forms a metal layer 3 2 0 '. A conductive or non-conductive filling material M1 is filled in the through holes 32, as shown in FIG. As shown in FIG. 3I, next, a circuit patterning process is performed to form a second patterned circuit layer on the surface of the core board 3 0, 3 1 constituting the multilayer board and in the through hole 32. 3 0 3b, 3 13b, and plated-through holes 33. The second patterned circuit layer 3 0 3b, 31 3b has a plurality of electrical connection pads 3 03c, 3 13c.

200539772 V. Description of the invention (9) 'And at least one electrical connection pad 3 0 3 c, 3 1 3 c is formed at the bottom of the conductive blind holes 302 a, 312 a of the core board 3 0, 3 1. Among them, since the patterning process belongs to a known person ', it will not be described in detail here. Therefore, the present invention can define a plurality of electrical connection pads 303c, 313c 'in the second patterned circuit layer 3 0 3b, 31 3b, and make at least one electrical connection 303c, 313c be formed in the above 3 Hai core. The bottoms of the conductive blind holes 302a, 312a of the laminates 30, 31 are used to form a direct conductive path for electrical connection, without the need for additional wiring on the back of an electrical connection as is known in the art to connect it to the conductive Electrical connection of blind hole 塾. Therefore, the present invention can use a blind hole formed by laser in advance as a part of a conductive line such as an electrical connection, thereby reducing the amount of electrical connection pads. Moreover, the present invention is not affected by the arrangement of conductive blind holes. The limitation of space can expand the layout space and flexibility of the circuit board. ^ As shown in FIG. 3J, a patterned solder resist layer (S〇1 der ma sk) 3 4 is formed on the second patterned circuit layers 303b, 31 3b, and a portion of the second patterned circuit is exposed outside Layers 3 0 3b, 313b are electrically connected to pads 303c, 313c, and a metal protective layer 36, such as a nickel / gold metal layer or other, is formed on the electrical connection pads 3 303c, 3 1 3c. Appropriate metal protective layer to protect the electrical connection pads 303c, 313c, and provide the electrical connection 303c, 313c with good electrical connection with other conductive elements. It can then be planted on the electrical connection pad, with solder wires, solder balls, metal bumps, or other appropriate conductive elements, for subsequent use as a circuit board carrying a semiconductor wafer. In May, I read Figure 3I. Through the aforementioned process, the present invention also revealed a circuit board with multiple circuit layers, including: a plurality of core boards 3 0, 3 丨 on one surface of the core boards 30, 31. A first patterned circuit layer 30a is formed thereon,

17661 Full 懋 .ptd

Page 17 200539772 V. Description of the invention (10) 3 1 3 8 and plural conductive blind holes 3 0 2 a, 3 1 2 a, and a second surface is formed on the other surface of the core board 3 0, 31 Patterning the circuit layers 303b, 313b, so that at least one of the electrical connection pads 30c, 313c in the second patterned circuit layer 3 03b, 313b corresponds to the bottom of the conductive blind holes 3 2a, 31 2a; at least An insulation layer 35 is sandwiched between the core boards 30, 31, and a plurality of plated through holes 33 formed in the core boards 30, 31 to electrically connect the core boards 30. , 31 line layer. In addition, please refer to Figs. 4A to 4E, which show another preferred embodiment of the circuit board with multi-layer wiring layers and the manufacturing method thereof according to the present invention. However, the structure and manufacturing method of this implementation example are substantially the same as those of the previous embodiment, except that this embodiment is to form a conductive blind hole in the multilayer board, and to supplement the foregoing embodiment is to form a penetration through the multilayer Plated vias for the board. Therefore, the following descriptions are for illustrative purposes only, and are not intended to limit the present invention. The same component symbols are used to represent the same components, so the same functions and structures will not be described again, only the differences Description. As shown in FIG. 4A, a completed multilayer board is provided. The multilayer board is formed according to the system shown in FIGS. 3A to 3F in the foregoing embodiment. / f π As shown in FIG. 4B, it is tied to the top and bottom sides of the multilayer board 3 (), such as laser drilling technology to drill a plurality of blind holes 4 丨, and the core board & 31 A patterned line 3 0 3a, 313a. Next, a metal layer 42 is formed on the surface of the selective hole 41 of the multilayer board. As shown in FIG. 4C, it is < ^ Physical vapor deposition (PVD), chemical vapor deposition (CVD), (Or chemical deposition technology, such as low bond (Sp u 11 ering), Cai Tie

200539772 V. Description of Invention (11)

Evaporation, Arc vapor deposition, Ion beam sputtering, Laser ablation deposition, plasma-assisted chemical vapor deposition or electroless plating, etc. A conductive layer (not shown) is formed on the surface of the core board 3 0, 3 1 and the blind hole 41 as a current conduction path. The plating process is used to form the core board 30, 3 1 and the blind hole 4 1 A plating metal layer 42 having a sufficient thickness is formed on the surface.

As shown in FIG. 4D, a circuit patterning process is performed to form second patterned circuit layers 303b, 313b and conductive blinds on the surface of the core board 3 0, 3 1 constituting the multilayer board and in the blind holes 41. Hole 41a. As shown in the figure, the second patterned circuit layers 3 0 3b, 3 13b have a plurality of electrical connection pads 3 3c, 313c, and at least one electrical connection pad 3 3c, 31 3c is formed on the core board. The bottoms of the conductive blind holes 30, 31 are 30 2 a, 3 1 2 a. Therefore, the present invention defines a plurality of electrical connection pads 303c and 313c in the second patterned circuit layers 303b and 313b, and at least one electrical connection pad 3o 3c, 31 3 is formed on the core board 30 The bottom of the conductive blind holes 3, 3, 2a, 31, 2 need no additional wiring to connect the electrical connection 塾 3 0c, 3 1 3c to another electrical connection pad, let alone the latter The electrical connection pad receives a conductive blind hole to be electrically connected to the inner layer circuit. This will simplify the wiring and form a direct conduction path. Therefore, the present invention can solve the lack of conventional technology without being limited by the space for the conductive blind holes. In addition to expanding the circuit layout area of the circuit board, it also makes the circuit board's circuit layout flexible as shown in Figure 4E. Then, a patterned zinc repellent layer 3 4 is formed on the surface of the multilayer board, and a part of the second patterned circuit layer 3 0 3 b is exposed.

200539772 V. Description of the invention (12) ~ 3 1 3 b Electrical connection pad 3 0 3 c, 3 1 3 c, and a metal protective layer 3 is formed on the electrical connection pad 3 〇 03 〇 3 1 3 c 6. The electrical connection is provided by the metal protective layer 3 6 3 0 3 c, 3 13 c make good electrical connection with other conductive components Y, and then, solder wires, solder balls can be planted on the electrical connection pad , Metal bumps, or other appropriate conductive elements' for subsequent use to carry electricity for semiconductor wafers ^ Although the foregoing embodiment is exemplified by a circuit board having four circuit layers as an example, it should be understood that the present invention Can also be applied to other layers of circuit boards. As shown in FIG. 5, it shows a preferred embodiment of the circuit 〇0 and 丄 Λ of the present invention having a multilayer circuit layer. It is mainly sandwiched between a plurality of station layers 30,31 between the insulation layer 35 and a core circuit board 50 to join, Ϊ: i ί Ϊ more ί circuit layer circuit board (the embodiment shown in the figure is Circuit board with eight circuit layers). Among them, according to the number of circuit layers completed or other processes, following 6 Shikou 〆 ^ ^ φ ^ 夂 衮 In the private test, the multi-layer circuit layer is electrically connected vertically. Hole, or partially through: m :::? L, or the combination of plated vias and conductive blind holes: not limited by the ones just described in the examples, but can be different according to different. Therefore, in the plural core The bottom end diameter of the electric blind hole is formed on the other side between the layers, so as to avoid one of the side-shaped electric blind holes on the board of the present invention. Most of the electrical selectable forming techniques require conductive blinds to be formed on the multilayer circuit layer. The side clamped insulation connection pads are formed into circuit boards and holes that are electrically connected to an electrical connection, and then on the layer, and then directly at the place where the circuit layer is connected, and the manufacturing method can be used for these circuit boards. The circuit board so that the conductive conducting path connects it

17661 Full 懋 .ptd

200539772

V. Description of the invention (13) The connection to the steps and the complexity. In addition, the layout area of the electrically conductive blind holes of this road layer, the know-how of the seed board and its manufacturing method, can reduce the electrical conductivity and not be conductive. When the outer layer wiring board is conductive, there is no need to further reduce the manufacturing process of the circuit board of the present invention. The embodiment of the present invention is only to limit the spirit of the present invention and to set the electrical layer at the right hole of the model to avoid occupying the wiring layer. Conductive opening position, circuit board layout of the board 'The present invention sets the length of the electrically connected circuit layer to reduce the occupied space. The circuit layout is further formed to form a pattern filling material, and the process steps are not limited to the equivalent replacement of materials. The embodiments described in the original art of the present invention should be used to open the conductive blind holes as described later, while avoiding the invention's direct installation space with multiple connection pads and the lack of circuit types. No additional multi-row circuit board pads are required to set the blind hole opening area, so that the bottom end of the blind hole table will include the cost of the steel process, and the steps, equipment or material layers will be illustrated. . Under any familiarity, use the protective pad gj to connect the pads to borrow layout space. The bottom of the circuit board and its blind holes, in order to increase the flexibility of the electrical system, has the cost limit of the multi-layer wire connection supply and conductive electrical connection process, thereby expanding flexibility. Layer and fill in the conductive blind step. The generation steps described in the examples can be implemented without any modifications and changes. The patents can be applied without modification and changes to reduce the number of lines in the manufacturing process. It is not necessary to consider the circuit of the circuit board to solve the electrical blind holes in the circuit layer. In this way, in addition to the large circuit board of the present invention, in the electrical connection pad hole, there are also methods, such as changing the multilayer range. The above is not intended to violate the invention. Therefore, the range is listed.

17661 Quan 懋 .ptd Page 21 200539772 Simple illustration of the drawings [Simplified illustration of the drawings]: Figures 1A to 1C are the conventional semi-additive process schematic diagrams; Figures 2A to 2C are the conventional circuits Schematic diagram of the electroplating process; Figures 3A to 3J are schematic cross-sectional views of the first embodiment of the circuit board with multilayer circuit layers of the present invention; Figures 4A to 4E are circuit boards of the present invention with multilayer circuit layers A schematic cross-sectional view of the second embodiment; and FIG. 5 is a schematic cross-sectional view of the third embodiment of a circuit board with a multilayer circuit layer according to the present invention. (Explanation of component symbols) 10 Core circuit board 11 Insulating layer 110 Opening hole 12 Inner circuit layer 13 Conductive layer 14 Resistive layer 15 Patterned circuit layer 16, 26 Electrical connection pad 20 Core circuit board 21 Insulating layer 211 Metal layer 210 Opening hole 22 Inner circuit layer 23 Conductive layer 111 11! 17661 Full 懋 .ptd Page 22 200539772 Brief description of the diagram 24 Resistive layer 25 Patterned circuit layer 3 0, 31 Core board 301, 311 Metal layer 302, 312 Blind hole 302a, 312a conductive Blind holes 3 0 3, 3 1 3 Electroplated metal layers 303a, 313a First patterned circuit layer 303b, 313b Second patterned circuit layer 3 0 3c, 31 3c Electrical connection pad 35 Insulation layer 32 Through hole 320 Metal layer 321 Filling material 33 Plating via 34 Antireflective layer 36 Metal protective layer 41 Blind hole 41a Conductive blind hole 42 Metal layer 50 Circuit board

17661 懋 .ptd Page 23

Claims (1)

200539772 VI. Scope of patent application 1. A method for manufacturing a circuit board with multiple circuit layers includes: providing a core board with a plurality of metal layers formed on its surface; forming a plurality of blind holes on one surface of the core board to expose the core A metal layer on the other surface of the laminate; a circuit patterning process is performed to form a first patterned circuit layer and a plurality of conductive blind holes on the surface of the core laminate with the blind holes; and the core laminates are formed with conductive blind One side of the hole is separated by an insulating layer to form a multilayer board; a plurality of through holes are formed in the multilayer board; and a circuit patterning process is performed to form a second pattern on the surface of the multilayer board and the corresponding through hole. And a plurality of conductive vias. 2. For example, the method for manufacturing a circuit board with multiple circuit layers in the scope of patent application, wherein the blind hole is formed by laser drilling. 3. If the method of manufacturing a circuit board with a multilayer circuit layer according to item 1 of the patent application scope, a filling material may be filled in the through hole. 4. For the method for manufacturing a circuit board with a multi-layer circuit layer according to item 1 of the patent application scope, wherein the conductive via is one of a plated via and a conductive blind via. 5. For the method of manufacturing a circuit board with a multi-layer circuit layer according to item 1 of the scope of patent application, wherein the conductive vias penetrate the multi-layer board for subsequent formation of electroplated vias. 6. For the method of manufacturing a circuit board with a multi-layer circuit layer according to item 1 of the scope of patent application, wherein the conductive vias do not penetrate the multi-layer board for subsequent formation of conductive blind vias. 17661 Quan 懋 .ptd Page 24 200539772 --- 6 7. > The scope of the patent application is as the first in the scope of patent application. Among them, the circuit board of the second layer of the security layer: //, and the layer of the circuit layer is too H + one The 0 woody circuit layer has a plurality of electrical properties, and at least one electrical connection pad is an electrical connection pad, and 1 is formed on the core board. Fatal blind hole bottom 8. As in the method of Shenjing Patent No. 丨 or 7 with a multilayer circuit layer method, where 'the second patterned circuit layer is formed with a fresh plate layer ^ and the exposed part of the first Two patterned circuit layer pattern rejection 9 · For a circuit board with a multilayer circuit layer in the scope of patent application item 7, where 'the electrical connection pad is formed with a metal protective layer, t = the electrical connection pad and provides effective electrical properties Connect the conductive element. '、 Protect the I. Such as the circuit board system with multi-layered circuit layers in item 9 of the scope of patent application, wherein the conductive element is one of the group consisting of bonding wires, solder balls and metal bumps. .乂 II · For the method for manufacturing a circuit board with multiple circuit layers according to item 9 of the patent application, wherein the metal protective layer is a nickel / gold metal layer. 12. A method for manufacturing a circuit board with a multilayer circuit layer as described in item 1 of the scope of the patent application, wherein the core layer board may be separated by an insulating layer to be bonded to the multilayer circuit board. 1 3. —A kind of circuit board with multilayer circuit layers' includes a plurality of core layer boards, f 4 of the core layer board is formed with a first patterned circuit layer and conductive blind holes, and the other surface of the core 3 is opposite A second patterned circuit layer is formed; p at least one insulating layer is sandwiched between the first patterned circuit layer and the conductive blind hole of the core layer board; and 17661 All thoughts. Ptd 200539772 6. Scope of patent application A plurality of conductive vias are formed in the core board to electrically connect the core boards with power supply. 14. A circuit board with multiple layers of layers as described in item 13 of the scope of patent application, wherein these blind holes are drilled by laser drilling. 1 5. If a circuit board with multiple layers is applied for item 13 in the scope of patent application, wherein the conductive via is one of a plated through hole and a conductive blind hole. 0 6. If item 13 is in the scope of patent application A circuit board with a multilayer circuit layer, wherein the conductive vias penetrate the multilayer board for subsequent formation of a plated through hole L. 17. For a circuit board with a multilayer circuit layer as described in item 13 of the patent application scope, wherein the conductive vias do not penetrate the multilayer board for subsequent formation of conductive blind holes. 18. The circuit board with a multilayer circuit layer according to item 13 of the scope of patent application, wherein the second patterned circuit layer has a plurality of electrical connection pads, and at least one electrical connection pad is formed on the core layer The bottom of the conductive blind hole of the board is 109. For example, a circuit board with a multi-layered circuit layer in item 13 or 18 of the scope of patent application, wherein a patterned solder resist layer is formed on the second patterned circuit layer, and The second patterned circuit layer is partially exposed. 20. A circuit board with a multilayer circuit layer as described in claim 18 of the scope of patent application, wherein a metal protective layer is formed on the electrical connection pad to protect the electrical connection pad and provide effective electrical connection to conductive elements. 2 1. If a circuit board with a multi-layered circuit layer is in the scope of patent application No. 20, the 17661 Quan 懋 .ptd Page 26 200539772 6. In the scope of patent application, the conductive element is one of the group consisting of wire, solder ball and metal bump. 2 2. A circuit board with a multi-layer circuit layer, such as the scope of application for patent No. 20, wherein the metal protective layer is a nickel / gold metal layer. 2 3. The circuit board with multi-layer circuit layers according to item 13 of the scope of patent application, wherein an insulation layer is spaced between the core and board to be bonded to the multi-layer circuit board. 17661 懋 .ptd Page 27