200847363 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種封势其& +彡本说 一 裡钌衮基板之結構，尤指一種適用於 提高封裝基板之導電能力i & At 电靶刀一政熱性旎，並且同時降低製作 5 成本之封裝基板結構。 【先前技術】 隨著電子產業的蓬勃發展，電子產品亦逐漸進入多功 能、高性能的研發方向。為滿足半導體封裝件高積集度 1〇 (Ι*_ί〇η)以及微型化⑼‘㈣灿⑽）的封裝要求，提供 多數主被動元件及線路連接之電路板，亦逐漸由單層板演 變成多層板，以使在有限的空間下，藉由層間連接技術 (Interlayer connection)擴大電路板上可利用的佈線面積而 配合高電子密度之積體電路（Integrated circuit)需求。 15 目刚，半導體封裝結構大多是將半導體晶片背面黏貼 於基板頂面後進行打線接合（wire b〇nding),或是將半導體 晶片主動面以覆晶接合（Flip chip)方式與基板頂面電性連 接，爾後再於基板之背面植以錫球，以電性連接至如印刷 電路板之外部電子裝置。 -0 圖1A至1E為習知覆晶封裝基板之製作方法。首先，請 參閱圖1A，提供一核心板11，此核心板丨丨須由不導電之材 料構成。目刖’業界常用BT樹脂（Bismaleimide Triazine200847363 IX. Description of the Invention: [Technical Field] The present invention relates to a structure of a substrate, in particular, a substrate suitable for improving the conductivity of a package substrate, i & At The electric target knife is hot and entangled, and at the same time reduces the cost of the package substrate structure. [Prior Art] With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional and high-performance research and development. In order to meet the packaging requirements of semiconductor package high integration 1〇(Ι*_ί〇η) and miniaturized (9)'(4)can(10)), most active and passive components and circuit-connected circuit boards are provided, which are gradually evolved from single-layer boards. The multi-layer board is used to expand the wiring area available on the board by an interlayer connection in a limited space to meet the requirements of a high electron density integrated circuit. 15, the semiconductor package structure is mostly after the back side of the semiconductor wafer is adhered to the top surface of the substrate for wire bonding, or the semiconductor wafer active surface is flip-chip bonded (Flip chip) and the top surface of the substrate The connection is followed by solder balls on the back side of the substrate to electrically connect to external electronic devices such as printed circuit boards. -0 Figures 1A to 1E show a method of fabricating a conventional flip chip package substrate. First, referring to Fig. 1A, a core board 11 is provided, which is not made of a non-conductive material.目' Industry commonly used BT resin (Bismaleimide Triazine
Resin)作為核心板u的材料。接著，如圖1B所示，於核心 5 200847363 板η中形成複數個貫通核心板u之通孔lla。此通孔lla一 般是以機械鑽孔方式形成。 隨之，如圖1C所示，透過無電電鍍的方式，全面性形 成一晶種層（圖未示）覆蓋於核心板i丨之兩侧表面、以及該些 5通孔11 a之内壁，再利用晶種層（圖未示）導電，電鍍形成一 金屬層12於核心板11之兩側表面、以及該些通孔丨之内 壁；之後以樹脂13將通孔Ua填滿。 / 凡成上述步驟之後，如圖1D所示，以微影及蝕刻技術 ' 使金屬層12圖案化。位於核心板u兩側表面之金屬層以被 Θ木化後成為覆晶基板之線路層丨，至於通孔11及其内壁 之金屬層12b則成為導電通孔，係電性連接核心板u兩側表 面之線路層12a。 15Resin) is the material of the core board u. Next, as shown in FIG. 1B, a plurality of through holes 11a penetrating through the core plate u are formed in the core n 200847363. This through hole 11a is generally formed by mechanical drilling. Then, as shown in FIG. 1C, a seed layer (not shown) is formed on both sides of the core plate i and the inner walls of the five through holes 11 a by means of electroless plating. The seed layer (not shown) is electrically conductive, and a metal layer 12 is formed on both sides of the core plate 11 and the inner walls of the through holes, and then the through holes Ua are filled with the resin 13. / After the above steps, as shown in FIG. 1D, the metal layer 12 is patterned by the lithography and etching technique. The metal layer on the surface of both sides of the core board u is turned into a circuit layer of the flip-chip substrate, and the metal layer 12b of the through hole 11 and the inner wall thereof becomes a conductive via hole, and is electrically connected to the core board u. The wiring layer 12a of the side surface. 15
20 然後，如圖1E所示，利用習知增層方式分別於核心板 11兩側形成線路增層結構15，15，，至此完成—多層結構之封 2基板。此線路增層結構15，15，主要是由介電層150,150，與 金屬線路層151，151’依序增層所構成，由於其製法已為業界 所熟知，故不贅述。 最後於線路增層結構丨5,15，表面形成具有複數個開口 160之防焊層16’再於開口⑽中形成焊料凸塊1脑焊料球 nr完成本實施例之覆晶封裝基板。該覆晶基板下側之 =㈣係供與-㈣電路板電性連接之用，覆晶基板上 W之知料凸塊17()係、供與__晶片電性連接之用。 f上述之封裝基板製作方法中，封裝基板的主要製作 :、、製作核心板11之通孔lia的機械鑽孔製程。核心板n 6 200847363 在進行機械鑽孔時，會先將複數個核心板丨丨堆疊在一起， 再一起對這些核心板u進行機械鑽孔。因此，在固定高度 下核心板11的厚度愈薄，則可疊板數量越多，每次機械鑽 孔可加工之核心板U數量就越多，隨之加工成本就越少。 而核u板1 1厚度怨溥’則該核心板} i於後續製程所面臨 之板彎（warpage)及漲縮等風險將隨著愈大。 f 10 另方面由於封裝基板的電性與散熱性能主要是由 核心板11之導電通孔的導電與導熱特性而定，導電通孔若 為實心金屬柱一般可獲致最佳導電與導熱特性，而核心板 η之厚度太厚則不易於製作實。金屬柱之導電通孔，這也 是所以業界習用的技術，核心板此導電通孔僅為配置於 通孔m内壁表面之金屬層12b而非實心金屬柱。然而隨著 業界對封裝基板之電性及散熱要求越來越高，習知封裝基 板之導電通孔結構，將無法滿足需求。 土 15 發明内容 20 有鐘於此，本發明提供一種封裝基板之 1 一電性導通板嵌埋於一核心板之鬥”山 /…、巧 柏·$ 开中，俾能提高每次機 械鑽孔可加工之疊板數，以降低加工成本。 實心金屬之導電通 及導熱效果。 並且，由於該電性導通板易於製作 孔’俾能提高封裝基板之電性傳導能力 7 200847363 埋於核心板内，後續之 面臨之板彎及漲縮等風 再者，由於該電性導通板係嵌 製程能夠避免以較薄核心板加工所 險0 ❹=明所提供封裝基板之結構m核心板， 口、？一：對之兩表面，並具有至少-貫穿該兩表面之開 ’，也性導通板，係被嵌埋於該外核心板之開口中；二 ^〜層l構’係對應配置於該外核心板與電性導通板之 _ ’該外核增層結構包括至少—第—介電層、至少—第 介==及複數第—_導電盲孔’第_線路層係、疊置於第一 /曰Ί且第—導電f孔係電性連接該些第一線路 二、1其中部份第—導電f孔係、電性連接第—線路層與該電 通板’又最外面之p線路層具有複數連接塾；以及 了防焊層，係覆蓋於外核增層結構表面，且具有複數開孔， 以顯露該些連接墊。 15Then, as shown in Fig. 1E, the line build-up structures 15, 15 are formed on both sides of the core board 11 by conventional build-up methods, respectively, and the two-layer structure of the multi-layer structure is completed. The line build-up structures 15, 15 are mainly composed of dielectric layers 150, 150, and metal circuit layers 151, 151' sequentially added. Since the manufacturing method is well known in the industry, it will not be described. Finally, on the surface build-up structure 丨5,15, a solder resist layer 16' having a plurality of openings 160 is formed on the surface, and a solder bump 1 brain solder ball nr is formed in the opening (10) to complete the flip chip package substrate of the present embodiment. The lower side of the flip chip substrate is used for electrical connection with the -(4) circuit board, and the material bump 17 () of the flip chip substrate is electrically connected to the __ chip. f In the above method for fabricating a package substrate, the package substrate is mainly produced: a mechanical drilling process for forming a through hole lia of the core plate 11. Core board n 6 200847363 When mechanical drilling is performed, a plurality of core boards are stacked first, and then these core boards u are mechanically drilled together. Therefore, the thinner the thickness of the core plate 11 at a fixed height, the larger the number of stackable plates, and the more the number of core plates U that can be machined per mechanical drill hole, and the less the processing cost. However, the risk of warpage and shrinkage of the core board will be greater as the core board will be reluctant. f 10 In addition, since the electrical and thermal performance of the package substrate is mainly determined by the conductive and thermal conductivity of the conductive via of the core board 11, the conductive via is generally a solid metal pillar to obtain the best electrical and thermal conductivity characteristics. If the thickness of the core plate η is too thick, it is not easy to make it. The conductive via of the metal post is also a technique used in the industry. The conductive via of the core board is only the metal layer 12b disposed on the inner wall surface of the through hole m instead of the solid metal pillar. However, as the industry's requirements for electrical and thermal dissipation of package substrates are increasing, the conductive via structure of conventional package substrates will not meet the demand. Soil 15 SUMMARY OF THE INVENTION In the present invention, the present invention provides a package substrate 1 in which an electrical conduction plate is embedded in a core plate "mountain"..., Qiaobai·Open, which can improve each mechanical drill The number of stacked plates can be processed to reduce the processing cost. The conductive conduction and thermal conduction effect of the solid metal. Moreover, since the electrical conduction plate is easy to make the hole '俾 can improve the electrical conductivity of the package substrate 7 200847363 buried in the core board In addition, the subsequent plate bending and shrinkage, etc., due to the electrical conduction plate system can avoid the processing of the thin core plate. And a pair of surfaces having at least - opening through the two surfaces, and a conductive via plate embedded in the opening of the outer core plate; the second layer is configured correspondingly to The outer core plate and the electrical conductive plate _ 'the outer core build-up structure includes at least - the first dielectric layer, at least - the first dielectric == and the plurality of - - conductive blind holes' _ circuit layer system, stacked Electrically connecting the first/曰Ί and the first conductive f holes A line 2, a portion of the first conductive f-hole system, the electrical connection first-circuit layer and the outermost p-circuit layer of the telecommunications plate have a plurality of connection ports; and a solder resist layer covering the outer core The surface of the structure is layered and has a plurality of openings to reveal the connection pads.
20 上述結構中，該電性導通板之一較佳實施方式為，該 1生導通板具有一内核心板，其相對兩表面各具有一金屬 線路層，且該内核心板具有複數導電通孔，係貫通該内核 心板之兩表面且電性連接該些金屬線路層，其中，該金屬 線路層下方復配置有一金屬線路底層，且該導電通孔係為 填滿該通孔之金屬柱。該金屬線路底層之材料不限定，較 佳為一晶種層及一銅箔層其中之一者，且該導電通孔之該 金屬柱與於該通孔内壁之間復可包括有一晶種層。 上述結構中，復可包括二内核增層結構，係對應配置 於该内核心板之兩側，其中，該内核增層結構包括至少一 8 200847363 第了介電層、至少一第二線路層及複數第二導電盲孔，第 二線路層係疊置於第二介電層表面一：電盲'第 性連接該些第二線路 =電盲孔係電 心;本；a α 电「連接第一線路層與該内核 增層結構之部η…取外面之弟-線路層係與外核 再刀弟一導電盲孔電性連接。 構另：·，本她提供一種嵌埋有晶片之封裝基板之結 少二：：核心板，係具有相對之兩表面，並具有至 r ι〇 15 2〇 外核開”;二外核增層G構二:被編該 導體構裝之兩側，該外核增層結⑽ 第-:::二第 電性連接該些第一線踗厗，、，η ν電盲孔係 係電坌/ θ亚一側之部份第一導電盲孔 &連接弟一線路層與該半導體構裝，又最外面之第一 線路層具有複數連接塾；以及弟 層姓Μ # A π θ 知層係覆盍於外核增 構表面’且具有複數開孔，以顯露該些連接塾。 上=構中’該半導體構裝之一較佳實施方式，係包 ΐ内：板’其相對兩表面各具有-金屬線路層，且 :内核心板具有複數導電通孔’係貫通該内 ::電性連接該些金屬線路層，且該導電通孔係為填= :了柱;一晶片’係以覆晶方式接置於該内：:板 之一側，該晶片且右旛赵雷饩勒 數導電元俥…且該些電極塾係藉由複 導電讀與§亥内核心板之該金屬線路層電性連接 -内核增層結構，係、配置於該内核心板之另—側，其中 9 200847363 該内核增層結構包括至少一第二介電層、至少 層及複數第二導電盲孔，第二線路層係疊置於第二：電層 表面’且第二導電盲孔係電性連接該些第二線路層，及電 性連接=二線路層與該内核心板表面之金屬線路層，又最 外面之第二線路層係與外核增層結構之部份第一 電性連接。 上述結構中，復包括一底膠層充填於該晶片與該内核 心板之間。 上述結構中，該些導電元件不限定’較佳為複數焊料 凸塊及複數焊料球其中之一者。 為複數烊枓 上述結構中’該外核心板另埋歲有至少一内核心板及 二=其兩側之内核增層結構，以電性連接該外核心板兩 側之外核增層結構。 15 20 =明所提供之嵌埋有晶片之封裝基板之結構，係且 有體構裝被嵌埋於外核心板之開 構裝之内核心板之厚产小时導體 趣禮,丨w 核心板厚度，俾能提高每 機械鑽孔可加工之疊板數，隨之降低加工成本。 核、由於料導體構裝之内核心板之厚度小於該外 通：板=故該半導體構裝易於製作實心金屬柱之導電 封裝基板之電性傳導能力及導熱效果。 製η避Γ於該内核心板係嵌埋於外核心板内，後續之 表矛壬月b夠避免以較薄外访 風險。 X板加工所面臨之板彎及漲縮等 10 200847363 L貫呃万式】 等圖示僅!圖式:為簡化之示意圖。惟該 實際實施時之態樣……：斤‘"具不支凡件非為 八貝除κ施時之元件數目、 例為一選擇性之今呼，0甘 形狀寺比 … 又6十且其元件佈局型態可能更複雜。 ，θ2Α121為本實施例封裝基板的製作方法剖面示 思圖。 百先參閱圖2A，提供一内核心板21。 的種類不受限制，主要是依 板21 10 15 戈'疋I屋口口而要選擇。本貫施例採用 之内核心板2 1為銅落基板（c〇pper dad ^叫，故該内核 心板21之兩侧表面分別具有一銅箔層22。 接著’參閱圖2B，利用機械鑽孔方式，於該内核心板 21中幵y成複數通孔2 1 a。進行機械鑽孔時，會先將複數内核 心板21堆豎在一起’再一起對這些内核心板。進行機械鑽 孑L。 广 然後，利用無電電鍍的方式，於該内核心板21之兩側 、 表面以及該些通孔21a之内壁全面性的形成一晶種層（圖中 未示）。該晶種層之材質可使用銅、錫、鈀、鉑、鎳、絡、 鈦、銅/鉻合金、或錫/鉛合金。在本實施例中，該晶種層為 20 銅。 接著，參閱圖2C，藉由該晶種層（圖中未示）作為導電 路徑’以電鍍方式在内核心板21之兩側表面以及該些通孔 2la之内壁全面性的形成一金屬層23直到該金屬層23填滿 該些通孔21 a為止。該金屬層23通常可使用金、銅、鎳、把、 200847363 銀、錫、鎳/把、絡/鈦、鎳/金、纪/金、或鎳/把/金等作為 材質。在本實施例中，該金屬層為銅材質。 然後，參閱圖2D，於該金屬層23表面形成一圖案化阻 層24。再如圖2E所示，移除未被該圖案化阻層24覆蓋之金 5屬層23、晶種層（圖中未示）、以及銅箔層22。此時，位於該 内核心板21兩側表面之金屬層23被圖案化而形成金屬線路 層23a，至於通孔21a内之金屬層23則形成電性連接該内核 心板21兩側該些金屬線路層23a之導電通孔23b。 然後，如圖2F所示，利用增層方式分別於該内核心板 10 21兩側形成一内核增層結構25,2 5，，係包括至少一第二介電 層250,250、至少一第二線路層251a，251a，及複數第二導電 盲孔251b，251b，，第二線路層251a，251a，係疊置於第二介電 層25/，25(V表面，且第二導電盲孔251b，25ib，係電性連接該 些第二線路層251a，251a，，及電性連接第二線路層 15 25 1a，251a’與該内核心板21表面之金屬線路層23a，至此完 成-電性導通板20。由於增層結構之形成方式已為業界所 熟知，故不贅述。 前述圖2A至2F僅以完成一電性導通板汕單元之製作 為代表以作為其製程示意圖，實際上該製程係應用於一整 20版面（Panel)之内核心板21，經前述製程以完成一整版面 (panel)之電性導通板2〇，言亥整版面電性導通板2〇具有複數 呈陣列排版之電性導通板20單元，復經過切割以得到複數 電性導通板20單元。 12 200847363 復次，參閱_，提供—外核心板31，並切割該外核 心板”中形成一開口 31a，該外核心板”之兩側表面可分別 具有-線路層32,32，，且該外核心板31之厚度與該電性導通 板20之厚度大致相同。 接著，參目圖2H，將該電性導通板2〇埋入該外核心板 31之開口 31钟，並以樹脂33固定該電性導通板2()於該開口 3 1 a 中。 Γ ΙΟ 15 20 然後，如圖21所示，利用增層方式分別於外核心板3ι 與電性導通板20兩側形成-外核增層結構35,351， 層結構35,35,包括至少-第—介電層风35Q，、至少一第^ 線路層351a，351a’及複數第一導電盲孔351b，351b，，第一線 路層351a，351a’係疊置於第一介電層35〇,35〇，表面，且第一 導電盲孔351Μ51ΐν係電性連接該些第一線路層35u, 351a，，其中部份第一導電盲孔351b，351b，係電性連接第一線 路層351a，351a，與該電性導通板2〇最外面之第二線路層 25 1 a,25 1 a又最外面之第一線路層351 a，35 1 a'具有複數連 接塾 35 1 c，35 1 c，。 最後，於該外核增層結構35,35,表面形成一防焊層 36,36’，該防焊層36,36,具有複數開孔36〇,36〇，以顯露該些連 接墊35 lc，35 lc’，以供後續配置焊料凸塊或焊料球（圖未 示）’即完成本實施例之封裝基板之製作。 本發明復提供一封裝基板結構，如圖21所示，該封裝 基板結構主要包括：一外核心板31 ; 一電性導通板2〇(見圖 2F)肷埋於該外核心板3 1之開口 3 1 a中；二外核增層結構 13 200847363 35,35f，係對應配置於 側；以及一且古★*、以 之31與電性導通板20兩 構35,35,表面。 曰6,36復|於外核增層結 其中，該電性導通板2〇具有一心 表面各具有一金屬線 = ，，'相對兩 9 且垓内核心板2 1具有福數莫 =b，係貫通該内核心板21之兩表面且電性連接= 路層23a。該金屬線路層23a下方配置有一金屬線路 f 10 底層（本實施例中為_ 4 μ ”、、銅、泊層，見圖邛之22)，且該導電通孔 係為填滿該通孔21 a之金屬柱。 實施例 本實施例請參考圖从至3£，係嵌埋有晶片之封裝基板 的製作方法剖面示意圖。 _首先，芩閱圖3 A，其結構與實施例一之圖2F大致相 15同，係一已完成之電性導通板20，，其製法可參考實施例一 ，圖2A至2F相關說明而得知，故不贅述。在本實施例中， 忒内核增層結構25,25，包括一第二介電層25〇,25〇，、一第二 線路層251a，251a’及複數第二導電盲孔251b，251b，，第二線 路層251a，251a’係疊置於第二介電層25〇,25〇，表面，且第二 2〇導電目孔251 b，251b’係電性連接該内核心板21兩側該些金 屬線路層23a與該些第二線路層251a，251a，。 然後，如圖3B所示，將一晶片28以覆晶方式接置於該 私性導通板20’之一側，使該晶片28之該些電極墊28〇藉由複 數導電元件27與該内核增層結構25之第二線路層25 la電性 25 連接；再將一底膠層29充填於該晶片28與該電性導通板20, 14 200847363 之間，至此完成一半導體構裝2。上述該些導電元件27係為 複數焊料凸塊及複數焊料球其中之一者。 此外，本實施例之内核增層結構25，亦可只形成於該内 核心板21未接置該晶片28之一側，則該晶片28之電極塾· 5可錯由複數導電元件27直接與該内核心板21之該金屬線路 層23a電性連接（圖未示）。 另方面，參閱圖3C，提供一外核心板3丨，並切割該 外核心板以形成一開口 31a，該外核心、板31之兩側表面^ 分別具有一線路層32,32'，且該外核心板31之厚度與該半導 10 體構裝2之厚度大致相同。 接著，參閱圖3D，將該半導體構裝2埋入該外核心板 31之開口 31a中，並以樹脂33固定該半導體構裝二。 然後:如圖3E所示，利用習知增m分別於外核心 板31與半導體構裝2兩側形成-外核增層結構35,35、由於 15增層結構之形成方式已為業界所熟知，故不贅述。在本實 施例中，該外核增層、结構35,35,包括至少—第一介電^ 350,3 5 G、至少—第_線路層35u，35ia，及複數第—導電盲 孔351b，351b，，第-線路層351a，351a，係疊置於第一介電層 35〇,35〇表面，且第一導電盲孔351b，351b，係電性連接該些 20第、、線路層351a，351a，，其中部份第一導電盲孔3训，係電 性連接第-線路層35 la，與該半導體構裝2之第二線路層 251a’。 s 最後，於該外核增層結構35,35,表面形成一防焊層 %，36，該防焊層36,3 6,具有複數開孔360,360,以顯露該些 15 200847363 連接塾351c,351c’ ’以供後續配置焊料凸塊或焊料球（圖未 示）’即完成本實施例之嵌埋有晶片之封裝基板之製作。 本實施例復提供一嵌埋有晶片之封裝基板之結構，如 圖3E所示，該嵌埋有晶片之封裝基板結構主要包括：一外 5核心板31 ; 一半導體構裝2嵌埋於該外核心板31之開口 31a 中；二外核增層結構35,3 5，，係對應配置於該外核心板與半& 導體構裝2之31兩侧；以及一具有複數開孔之防焊層3/,'36, 覆蓋於外核增層結構35,3 5’表面。 其中，該半導體構裝2包括：一内核心板21，其相對兩 10表面各具有一金屬線路層23a，且該内核心板21具有複數導 電通孔23b ’係貫通該内核^板21之兩表面且電性連接該些 金屬線路層23a，且該導電通孔23b係為填滿該通孔之金 屬柱，a曰片28，係以覆晶方式藉由複數導電元件27接置 於該内核心板之一側；以及一内核增層結構25,25t，係配置 15於该内核心板21之一側或兩側。上述該些導電元件27係為 複數焊料凸塊及複數焊料球其中之一者。 、上述之結構中，該外核心板復可另埋嵌有至少一電性 導通板，以電性連接言亥外核心板兩側之外核增層結構，請 參閱實施例一之圖21。 20 _於習知封裝基板結構，本發明所提供之封裝基板 結構與嵌埋有晶片之封裝基板結構，均使封裝基板具有實 至屬柱之導电通孔，因此該封裝基板結構能有較佳之電 性傳導功能與傳熱效果。 並且本發明之導電通孔係於内核心板中製作，由於 16 200847363 其厚度小於一般外核心板，故每次機械鑽孔可加工之板數 可增加。製作外核心板之通孔的機械鑽孔製程為封裝基板 的主要製作成本，因此本發明可降低封裝基板的製作成本。 再者，由於該内核心板係嵌埋於外核心板内，後續之 製程能夠避免以較薄外核心板加工所面臨之板彎及漲縮等 風險。 上述實施例僅係為了方便說明而舉例而已，本發明所 張之權利範圍自應以申凊專利範圍所述為準，而非僅限 於上述實施例。 【圖式簡單說明】 圖1A至1E為習知覆晶封|基板之製作方法剖面示意圖。 圖2A至21為本實施例封裳基板的製作方法剖面示意圖。 圖3A至3E為本實施例封裝基板的製作方法剖面示意圖。 【主要元件符號說明】 核心板 外核心板 金屬層 導電通孔 線路增層結構 防焊層 焊料凸塊 電性導通板 金屬線路底層 圖案化阻層 1 la，21a 通孔 12a，151，151’，32,32, 線路層 13, 33 樹脂 150,150' 介電層 160,360,360， 防焊層開孔 171 焊料球 21 内核心板 23a 金屬線路層 25,25， 内核增層結構 11 r 31 12, 23 12b，23b 15，15’ 16,36,36丨 170 20,201 22 24 17 200847363 250,2501 第二介電層 251a，251a， 第二線路層 251b925 1bf 第二導電盲孔 2 半導體構裝 27 導電元件 28 晶片 280 電極墊 29 底膠層 31a 開口 35,351 外核增層結構 350,350， 第一介電層 351a?351af 第一線路層 351b9351bf 第一導電盲孔 351c，351c! 連接墊 18In a preferred embodiment of the electrical conduction plate, the one-way conductive plate has an inner core plate, and each of the two surfaces has a metal circuit layer, and the inner core plate has a plurality of conductive through holes. And connecting the two surfaces of the inner core board and electrically connecting the metal circuit layers, wherein a metal circuit bottom layer is disposed under the metal circuit layer, and the conductive via is a metal pillar filling the through hole. The material of the bottom layer of the metal circuit is not limited, and is preferably one of a seed layer and a copper foil layer, and the metal pillar of the conductive via and the inner wall of the through hole may further comprise a seed layer. . In the above structure, the complex may include a two-core build-up structure correspondingly disposed on two sides of the inner core board, wherein the core build-up structure includes at least one of 200847363 dielectric layers, at least one second circuit layer, and a plurality of second conductive blind holes, the second circuit layer is stacked on the surface of the second dielectric layer: an electric blind 'the first connection to the second lines = an electric blind hole system core; the present; a α electric "connection A circuit layer and the portion of the core build-up structure η... take the outer brother-line layer system and the outer core and the knives a conductive blind hole electrically connected. Another: ·, she provides a package embedded with a wafer The second layer of the substrate is: the core plate has two opposite surfaces, and has a core opening to r ι〇15 2〇; the second outer nuclear layer G structure 2: is programmed on both sides of the conductor assembly, The outer core buildup layer (10) is electrically connected to the first line 踗厗, ,, η ν electric blind hole system 坌 / θ sub-side part of the first conductive blind hole & Connecting a line layer with the semiconductor package, and the outermost first circuit layer has a plurality of connections; and the younger layer Μ# A π θ Overlying strata configuration by the outer surface of the core "and having a plurality of openings to expose the plurality of connection Sook. In a preferred embodiment of the semiconductor package, the inside of the package: the board has a -metal circuit layer on each of its opposite surfaces, and the inner core plate has a plurality of conductive vias extending through the inside: Electrically connecting the metal circuit layers, and the conductive vias are filled with: a column; a wafer is attached to the inside by a flip chip: one side of the board, the wafer and the right side Zhao Lei a plurality of conductive elements 俥, and the electrodes are electrically connected to the metal circuit layer of the core board by a complex conductive read-core layer structure, and are disposed on the other side of the inner core board Wherein the core buildup structure comprises at least a second dielectric layer, at least one layer and a plurality of second conductive blind vias, the second circuit layer being stacked on the second: electrical layer surface 'and the second conductive blind via Electrically connecting the second circuit layers, and the electrical connection=the second circuit layer and the metal circuit layer on the inner core plate surface, and the outermost second circuit layer and the outer nuclear layered structure part of the first electricity Sexual connection. In the above structure, a primer layer is filled between the wafer and the core plate. In the above structure, the conductive elements are not limited to one of the plurality of solder bumps and the plurality of solder balls. In the above structure, the outer core plate has at least one inner core plate and two inner core build-up structures on both sides thereof to electrically connect the nuclear build-up structure on both sides of the outer core plate. 15 20 = The structure of the package substrate embedded with the wafer provided by Ming, and the body structure is embedded in the core plate of the open core of the outer core board. The 导体w core board Thickness, 俾 can increase the number of stacks that can be machined per mechanical drill, which in turn reduces processing costs. The core, because the thickness of the core plate within the conductor structure is smaller than the external: plate = the semiconductor structure is easy to fabricate the electrical conductivity and thermal conductivity of the conductive package substrate of the solid metal column. The η Γ Γ 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该Plate bending and shrinkage faced by X-board processing 10 200847363 L 呃 呃 】 】 等 等 等 ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! However, the actual implementation of the situation ...: Jin '" has nothing to do with the number of components of the eight-baked κ Shi Shi, the example of a selective call, 0 Gan shape temple than ... and sixty and The component layout type may be more complicated. θ2Α121 is a cross-sectional view showing a method of fabricating the package substrate of the present embodiment. Referring to Figure 2A, an inner core panel 21 is provided. The type is not limited, mainly depending on the mouth of the board 21 10 15 Ge'疋I. In the present embodiment, the core board 21 is a copper drop substrate (c〇pper dad, so that both sides of the inner core board 21 have a copper foil layer 22 respectively. Next, see FIG. 2B, using a mechanical drill In the inner core plate 21, a plurality of through holes 2 1 a are formed in the inner core plate 21. When mechanical drilling is performed, the plurality of inner core plates 21 are first stacked together to perform mechanical drilling on the inner core plates together. Then, a seed layer (not shown) is integrally formed on both sides of the inner core plate 21, the surface, and the inner walls of the through holes 21a by means of electroless plating. The material may be copper, tin, palladium, platinum, nickel, cobalt, titanium, copper/chromium alloy, or tin/lead alloy. In this embodiment, the seed layer is 20 copper. Next, referring to FIG. 2C, A seed layer (not shown) is used as a conductive path to form a metal layer 23 on both sides of the inner core plate 21 and the inner walls of the through holes 21a in a plating manner until the metal layer 23 is filled. The through holes 21 a. The metal layer 23 can generally be used with gold, copper, nickel, and, 200847363 , tin, nickel / handle, titanium / nickel, gold, gold / gold, nickel / handle / gold, etc. In this embodiment, the metal layer is made of copper. Then, refer to Figure 2D, A patterned resist layer 24 is formed on the surface of the metal layer 23. Further, as shown in FIG. 2E, the gold 5 layer 23, the seed layer (not shown), and the copper foil not covered by the patterned resist layer 24 are removed. Layer 22. At this time, the metal layer 23 on both sides of the inner core plate 21 is patterned to form the metal wiring layer 23a, and the metal layer 23 in the through hole 21a is electrically connected to both sides of the inner core plate 21. The conductive vias 23b of the metal circuit layers 23a. Then, as shown in FIG. 2F, a core buildup structure 25, 25 is formed on both sides of the inner core plate 10 21 by means of build-up, respectively, and includes at least one The second dielectric layer 250, 250, the at least one second wiring layer 251a, 251a, and the plurality of second conductive blind vias 251b, 251b, and the second wiring layers 251a, 251a are stacked on the second dielectric layer 25/, 25 (V surface, and the second conductive blind holes 251b, 25ib are electrically connected to the second circuit layers 251a, 251a, and electrically connected to the second line 15 25 1a, 251a' and the metal wiring layer 23a on the surface of the inner core board 21, thus completing the electrical conducting board 20. Since the manner of forming the build-up structure is well known in the industry, it will not be described. The foregoing Figs. 2A to 2F It is only represented by the fabrication of an electrical conduction plate unit as a schematic diagram of the process. In fact, the process is applied to a core board 21 within a 20-layer panel, and the entire process is completed by the aforementioned process. The electrical conduction plate 2〇, the full-face electrical conduction plate 2〇 has a plurality of electrical conduction plate 20 units arranged in an array, and is repeatedly cut to obtain a plurality of electrical conduction plate 20 units. 12 200847363 Repeat, refer to _, provide - outer core plate 31, and cut the outer core plate" to form an opening 31a, the two sides of the outer core plate may have - circuit layers 32, 32, and The thickness of the outer core plate 31 is substantially the same as the thickness of the electrical conduction plate 20. Next, in Fig. 2H, the electrical via 2 is buried in the opening 31 of the outer core plate 31, and the electrical via 2 () is fixed in the opening 3 1 a with a resin 33. Γ ΙΟ 15 20 Then, as shown in FIG. 21, the outer core plate 3 and the electrically conductive plate 20 are respectively formed on both sides of the outer core plate 3ι and the electrically conductive plate 20 by an additive layer, and the outer core buildup structure 35, 351, the layer structure 35, 35, including at least - the first The dielectric layer wind 35Q, at least one of the first circuit layers 351a, 351a' and the plurality of first conductive blind holes 351b, 351b, and the first circuit layers 351a, 351a' are stacked on the first dielectric layer 35, 35 The first conductive layer is electrically connected to the first circuit layers 35u, 351a, and the first conductive vias 351b, 351b are electrically connected to the first circuit layers 351a, 351a. The outermost first circuit layer 25 1 a, 25 1 a and the outermost first circuit layer 351 a, 35 1 a' have a plurality of connections 塾 35 1 c, 35 1 c, with the outermost second circuit layer 25 1 a, 25 1 a of the electrical conduction plate 2 . Finally, a solder resist layer 36, 36' is formed on the surface of the outer core buildup structure 35, 35. The solder resist layers 36, 36 have a plurality of openings 36, 36 〇 to expose the connection pads 35 lc , 35 lc', for subsequent configuration of solder bumps or solder balls (not shown) to complete the fabrication of the package substrate of the present embodiment. The present invention provides a package substrate structure. As shown in FIG. 21, the package substrate structure mainly includes: an outer core plate 31; an electrical conduction plate 2 (see FIG. 2F) is buried in the outer core plate 31. The opening 3 1 a; the second outer nuclear build-up structure 13 200847363 35, 35f, correspondingly disposed on the side; and one and the ancient ★ *, 31 and the electrical conduction plate 20 two structures 35, 35, the surface.曰6,36 complex|in the outer nuclear buildup layer, the electrical conduction plate 2〇 has a metal surface each having a metal line =, 'relative to two 9 and the inner core plate 2 1 has a blessing number = b, The two inner surfaces of the inner core plate 21 are penetrated and electrically connected to the road layer 23a. A metal line f 10 underlayer (in the present embodiment, _ 4 μ ′, copper, a berth layer, see FIG. 22) is disposed under the metal circuit layer 23a, and the conductive via is filled with the through hole 21 A metal column of a. Embodiments Referring to the drawings from Fig. 3 to Fig. 3, a schematic cross-sectional view showing a method of fabricating a package substrate in which a wafer is embedded. First, referring to Fig. 3A, the structure and Fig. 2F of the first embodiment A substantially completed electrical conduction plate 20, which can be referred to the first embodiment and the related description of FIGS. 2A to 2F, and therefore will not be described. In this embodiment, the 忒 core enhancement structure 25, 25, comprising a second dielectric layer 25A, 25A, a second circuit layer 251a, 251a' and a plurality of second conductive blind holes 251b, 251b, and the second circuit layers 251a, 251a' are stacked The second dielectric layer 25 〇, 25 〇, the surface, and the second 2 〇 conductive mesh holes 251 b, 251 b ′ are electrically connected to the metal circuit layer 23 a on both sides of the inner core board 21 and the second lines Layers 251a, 251a. Then, as shown in FIG. 3B, a wafer 28 is flip-chip bonded to one side of the private via 20'. The electrode pads 28 of the wafer 28 are electrically connected to the second circuit layer 25 la of the core build-up structure 25 by a plurality of conductive elements 27; a primer layer 29 is further filled on the wafer 28 and the Between the electrical conduction plates 20, 14 200847363, a semiconductor package 2 is completed. The conductive elements 27 are one of a plurality of solder bumps and a plurality of solder balls. Further, the core buildup structure of the embodiment 25, which may be formed only on the side of the inner core board 21 not connected to the wafer 28, and the electrode 塾5 of the wafer 28 may be directly connected to the metal circuit layer of the inner core board 21 by the plurality of conductive elements 27. 23a is electrically connected (not shown). In another aspect, referring to FIG. 3C, an outer core plate 3 is provided, and the outer core plate is cut to form an opening 31a, and the outer core and the side surfaces of the plate 31 have respectively a circuit layer 32, 32', and the thickness of the outer core plate 31 is substantially the same as the thickness of the semiconductor body assembly 2. Next, referring to FIG. 3D, the semiconductor package 2 is buried in the outer core plate 31. In the opening 31a, the semiconductor package 2 is fixed by a resin 33. Then: as shown in Fig. 3E As shown in the figure, the external core layer 31 and the semiconductor core structure 2 are respectively formed on both sides of the outer core plate 31 and the outer surface of the semiconductor structure 2, 35, and the formation of the 15 layer buildup structure is well known in the industry, and therefore will not be described herein. In an embodiment, the outer core buildup layer, the structure 35, 35, includes at least a first dielectric ^ 350, 35 G, at least - a first circuit layer 35u, 35ia, and a plurality of first conductive vias 351b, 351b, The first circuit layer 351a, 351a is stacked on the surface of the first dielectric layer 35, 35, and the first conductive blind holes 351b, 351b are electrically connected to the 20th, circuit layers 351a, 351a. And a part of the first conductive blind via 3 is electrically connected to the first wiring layer 35 la and the second wiring layer 251 a ′ of the semiconductor package 2 . s Finally, on the surface of the outer nuclear buildup structure 35, 35, a solder resist layer %, 36 is formed, and the solder resist layers 36, 36 have a plurality of openings 360, 360 to reveal the 15 200847363 connection 塾 351c, 351c The fabrication of the package substrate in which the wafer is embedded in this embodiment is completed by the subsequent arrangement of solder bumps or solder balls (not shown). In this embodiment, a structure of a package substrate embedded with a chip is provided. As shown in FIG. 3E, the package substrate structure embedded with the chip mainly includes: an outer 5 core plate 31; a semiconductor package 2 is embedded in the structure The outer core plate 31 has an opening 31a; the two outer core buildup structures 35, 35 are disposed on opposite sides of the outer core plate and the semi- & conductor assembly 2; and a plurality of openings The solder layer 3/, '36, covers the surface of the outer nuclear buildup structure 35, 35'. The semiconductor package 2 includes an inner core plate 21 having a metal circuit layer 23a opposite to each other on the surface of the two surfaces 10, and the inner core plate 21 has a plurality of conductive through holes 23b' extending through the core plate 21 The metal circuit layer 23a is electrically connected to the surface, and the conductive via 23b is a metal pillar filling the via hole, and the germanium chip 28 is connected to the inner surface by a plurality of conductive elements 27 in a flip chip manner. One side of the core board; and a core buildup structure 25, 25t, the arrangement 15 being on one or both sides of the inner core board 21. The conductive elements 27 are one of a plurality of solder bumps and a plurality of solder balls. In the above structure, the outer core plate may be embedded with at least one electrical conductive plate to electrically connect the nuclear build-up structure on both sides of the outer core plate, please refer to FIG. 21 of the first embodiment. 20 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Good electrical conductivity and heat transfer. Moreover, the conductive via of the present invention is fabricated in the inner core plate. Since the thickness of the thin core plate is less than that of the general outer core plate, the number of plates that can be processed by each mechanical drilling can be increased. The mechanical drilling process for fabricating the through holes of the outer core plate is the main manufacturing cost of the package substrate, and therefore the present invention can reduce the manufacturing cost of the package substrate. Moreover, since the inner core plate is embedded in the outer core plate, the subsequent process can avoid the risk of plate bending and shrinkage faced by the thin outer core plate processing. The above-described embodiments are merely examples for the convenience of the description, and the scope of the invention is intended to be limited by the scope of the claims. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1E are schematic cross-sectional views showing a method of fabricating a conventional flip chip package. 2A to 21 are schematic cross-sectional views showing a method of fabricating a cover substrate according to the embodiment. 3A to 3E are schematic cross-sectional views showing a method of fabricating a package substrate of the embodiment. [Main component symbol description] Core board outer core board metal layer conductive via line build-up structure solder mask solder bump electrical conduction board metal line bottom layer patterned resist layer 1 la, 21a through hole 12a, 151, 151', 32,32, circuit layer 13, 33 resin 150, 150' dielectric layer 160, 360, 360, solder mask opening 171 solder ball 21 inner core plate 23a metal wiring layer 25, 25, core buildup structure 11 r 31 12, 23 12b, 23b 15,15' 16,36,36丨170 20,201 22 24 17 200847363 250,2501 second dielectric layer 251a,251a, second circuit layer 251b925 1bf second conductive blind hole 2 semiconductor package 27 conductive element 28 wafer 280 electrode Pad 29 Primer 31a Opening 35, 351 Outer core buildup structure 350, 350, First dielectric layer 351a? 351af First trace layer 351b9351bf First conductive blind via 351c, 351c! Connection pad 18