JP5183045B2 - Circuit equipment - Google Patents

Description

  The present invention relates to a circuit device and a manufacturing method thereof, and more particularly, to a circuit device including a wiring board in which a core layer made of a thick metal is built, and a manufacturing method thereof. Furthermore, the present invention relates to a wiring board having a core layer made of a thick metal and a method for manufacturing the same.

  As electronic devices such as mobile phones become smaller and more functional, circuit devices housed therein are mainly provided with a multilayer wiring layer. A circuit device having a multilayer substrate 107 will be described with reference to FIG.

  Here, a circuit device is configured by mounting circuit elements such as a package 105 on the first wiring layer 102 </ b> A formed on the upper surface of the multilayer substrate 107.

  In the multilayer substrate 107, wiring layers are formed on the front surface and the back surface of the base material 101 made of a resin such as glass epoxy. Here, the first wiring layer 102 </ b> A and the second wiring layer 102 </ b> B are formed on the upper surface of the substrate 101. The first wiring layer 102A and the second wiring layer 102B are stacked with an insulating layer 103 interposed therebetween. A third wiring layer 102 </ b> C and a fourth wiring layer 102 </ b> D are stacked on the lower surface of the substrate 101 with an insulating layer 103 interposed therebetween. Each wiring layer is connected at a predetermined location by a connecting portion 104 provided through the insulating layer 103.

  A package 105 is fixed to the uppermost first wiring layer 102A. Here, the package 105 in which the semiconductor element 105A is resin-sealed is surface-mounted via a connection electrode 106 made of solder or the like. In addition to the package 105, passive elements such as chip capacitors and chip resistors, bare semiconductor elements, and the like may be mounted on the surface of the multilayer substrate 107. Here, the thickness of the multilayer substrate 107 is, for example, about 1 mm.

A method for manufacturing the multilayer substrate 107 having the above-described configuration is as follows. First, the second wiring layer 102B and the third wiring layer 102C are formed on the upper and lower surfaces of the base material 101 made of a resin-based material such as an epoxy resin. These wiring layers are formed by etching or selectively plating the attached conductive film. Next, the second wiring layer 102B and the third wiring layer 102C are covered with an insulating layer 103 made of resin. Further, a first wiring layer 102A and a fourth wiring layer 102D are formed on the surface of the insulating layer 103. The method of forming these wiring layers is the same as that of the second wiring layer 102B and the like described above. Further, a connection portion 104 that penetrates the insulating layer 103 and connects the first wiring layer 102A and the second wiring layer 102B is formed.
JP 2003-324263 A

  However, in the circuit device having the multilayer substrate (wiring substrate) having the above-described configuration, since the base material 101 which is the core layer of the multilayer substrate 107 is made of a resin material such as glass epoxy resin, the thermal conductivity is low. There was a problem that heat dissipation via the substrate could not be performed satisfactorily.

  In addition, there is a structure in which metal is used as the material of the base material 101. However, since a core base material in a state like a single metal plate is usually used, when the potential of the core base material is fixed to, for example, a ground potential. There is a problem that it is difficult to locally change the potential of the core substrate. Furthermore, when the material of the base material 101 is a metal, the outer peripheral end portion of the base material 101 which is a conductive material is exposed to the outside from the side surface of the multilayer substrate 107. Accordingly, there is a problem that it is difficult to insulate the base material 101 made of metal from the outside.

  Further, since the base material 101 made of resin is used in the manufacturing method, there is a problem that a crack occurs in the base material 101 in the middle of the manufacturing process and the multilayer substrate 107 becomes defective. . Specifically, in order to improve the mechanical strength of the multilayer substrate 101, and further to improve the heat dissipation of the entire substrate, the base material 101 is made of a resin highly filled with a filler such as alumina. For this reason, the base material 101 becomes fragile, and cracks frequently occur in the base material 101 in the transporting process, the process of inserting and mounting elements on the multilayer substrate 107, and the like.

  There is also a method of using metal as the material of the base material 101. In this case, the wiring layer laminated on the upper surface of the base material and the wiring layer laminated on the lower surface of the base material are efficiently conducted. The manufacturing method has not been established.

  The present invention has been made in view of the above-mentioned problems, and a main object thereof is to provide a circuit device and a wiring board with improved insulation from the outside of the inner metal core layer. It is another object of the present invention to provide an efficient manufacturing method of a circuit board and a circuit board having a core layer made of metal.

  The circuit device of the present invention comprises a wiring board and a circuit element mounted on the wiring board, and the wiring board includes a metal core layer, an insulating layer covering the upper surface and the lower surface of the metal core layer, A first wiring layer and a second wiring layer formed on an upper surface and a lower surface of the insulating layer, wherein the metal core layer is formed of a conductive pattern separated from each other by a separation groove; The conductive patterns are electrically insulated from each other by being filled.

  Furthermore, the circuit device of the present invention includes a wiring board and a circuit element mounted on the wiring board, and the wiring board includes a metal core layer and an insulating layer that covers an upper surface and a lower surface of the metal core layer. And a first wiring layer and a second wiring layer formed on an upper surface and a lower surface of the insulating layer, and an outer peripheral end portion of the metal core layer is an outer peripheral end portion of the wiring substrate made of the insulating layer. It is characterized by being located inside the space.

  The method for manufacturing a circuit device of the present invention includes a first step of partially removing one main surface of a conductive foil to form a separation groove shallower than the conductive foil, and the conductive foil so that the separation groove is filled. A second step of covering the one main surface with a first insulating layer; removing the conductive foil from the other main surface until the first insulating layer filled in the separation groove is exposed; A third step of separating the conductive foil at the provided location to form a conductive pattern; a fourth step of forming a second insulating layer so as to cover the conductive pattern; the first insulating layer; A fifth step of forming a first wiring layer and a second wiring layer on the main surface of the second insulating layer, and a sixth step of electrically connecting a circuit element to the first wiring layer are provided. And

  Furthermore, the method for manufacturing a circuit device according to the present invention includes a first step of partially removing one main surface of the conductive foil to form a connection hole shallower than the conductive foil, and the connection hole filled with the connection hole. A second step of covering the one main surface of the conductive foil with a first insulating layer; a third step of removing the conductive foil from the other main surface until the first insulating layer filled in the connection hole is exposed; A fourth step of forming a second insulating layer so as to cover the other main surface of the conductive foil and the first insulating layer exposed from the connection hole, and the first insulation at a position corresponding to the connection hole. A fifth step of forming a through hole penetrating the layer and the second insulating layer, and forming a first wiring layer and a second wiring layer on a main surface of the first insulating layer and the second insulating layer, A sixth step of forming a through connection portion for connecting the first wiring layer and the second wiring layer inside the through hole. , Characterized by comprising a seventh step of electrically connecting circuit elements to said first wiring layer.

  The wiring board of the present invention includes a metal core layer, an insulating layer covering the upper surface and the lower surface of the metal core layer, and a first wiring layer and a second wiring layer formed on the upper surface and the lower surface of the insulating layer. The metal core layer includes conductive patterns separated from each other by a separation groove, and the conductive patterns are electrically insulated from each other by filling the separation groove with the insulating layer.

  Furthermore, the wiring board of the present invention includes a metal core layer, an insulating layer covering the upper surface and the lower surface of the metal core layer, a first wiring layer and a second wiring layer formed on the upper surface and the lower surface of the insulating layer, The outer peripheral end of the metal core layer is located inside the outer peripheral end made of the insulating layer.

  The method for manufacturing a wiring board of the present invention includes a first step of partially removing one main surface of a conductive foil to form a separation groove shallower than the conductive foil, and the conductive foil so that the separation groove is filled. A second step of covering the one main surface with a first insulating layer; removing the conductive foil from the other main surface until the first insulating layer filled in the separation groove is exposed; A third step of separating the conductive foil at the provided location to form a conductive pattern; a fourth step of forming a second insulating layer so as to cover the conductive pattern; the first insulating layer; And a fifth step of forming a first wiring layer and a second wiring layer on the main surface of the second insulating layer.

  Furthermore, the method for manufacturing a wiring board according to the present invention includes a first step of partially removing one main surface of the conductive foil to form a connection hole shallower than the conductive foil, and the connection hole being filled with the connection hole. A second step of covering the one main surface of the conductive foil with a first insulating layer; a third step of removing the conductive foil from the other main surface until the first insulating layer filled in the connection hole is exposed; A fourth step of forming a second insulating layer so as to cover the other main surface of the conductive foil and the first insulating layer exposed from the connection hole, and the first insulation at a position corresponding to the connection hole. A fifth step of forming a through hole penetrating the layer and the second insulating layer, and forming a first wiring layer and a second wiring layer on a main surface of the first insulating layer and the second insulating layer, A sixth step of forming a through connection portion for connecting the first wiring layer and the second wiring layer inside the through hole. Comprising a.

  According to the circuit device and the wiring board of the present invention, the plurality of conductive patterns that are electrically insulated from each other by the separation groove are built in the wiring board as the metal core layer. Accordingly, the potentials of the metal cores can be made different, and further, a conductive pattern can be used as the wiring. Therefore, functions other than the heat dissipation function can be provided to the metal core layer, and the multi-function and miniaturization of the circuit device can be realized.

  Furthermore, according to the circuit device and the wiring board of the present invention, the metal core layer is positioned inside the outer peripheral end of the insulating layer covering the metal core layer. That is, the outer peripheral end of the metal core layer is covered with the insulating layer and is not exposed to the outside. Therefore, the metal core layer can be well insulated from the outside.

  According to the circuit device and the method for manufacturing a wiring board of the present invention, a conductive pattern functioning as a core layer can be easily formed. Specifically, in the present invention, a separation groove is provided on one main surface of the conductive foil, and the main surface of the conductive foil is covered with the first insulating layer so that the first insulating layer is filled in the separation groove. Thereafter, the conductive foil is separated at the location where the separation groove is provided, thereby forming a conductive pattern. Therefore, a conductive pattern having a desired shape that functions as a core layer can be easily formed inside the circuit device.

  Furthermore, according to the circuit device and the method for manufacturing a wiring board of the present invention, the wiring layers can be easily connected to each other by the through connection portion that penetrates the conductive foil functioning as the core layer in the thickness direction. Specifically, the conductive foil is partially recessed to provide a connection hole, one main surface of the conductive foil is covered with the first insulating layer so that the connection hole is filled, and the connection hole is filled. The conductive foil is removed from the other main surface until one insulating layer is exposed, and a through connection portion for connecting the wiring layers is formed inside the connection hole. From this, the penetration connection part which penetrates the electrically conductive foil used as a core and penetrates wiring layers can be easily formed in arbitrary places.

<First Embodiment>
In the present embodiment, the configuration of the circuit device of the present embodiment will be described with reference to FIGS.

  The configuration of the circuit device 10A will be described with reference to FIG. 1A is a cross-sectional view of the circuit device 10A, and FIG. 1B is a plan view showing a conductive pattern 11 built in the circuit device 10A.

  Referring to FIG. 1A, circuit device 10A is configured by mounting circuit elements such as semiconductor element 21 on the upper surface of wiring board 50 having a metal core layer. Further, the wiring substrate 50 includes a conductive pattern 11 functioning as a metal core layer, a first wiring layer 14 stacked on the upper surface of the conductive pattern 11 via the first insulating layer 12, and a second insulating layer 13. The second wiring layer 15 is mainly provided on the lower surface of the conductive pattern 11. A circuit element such as the semiconductor element 21 is mounted on the first wiring layer 14 of the wiring board 50.

  The conductive pattern 11 functions as a metal core layer that bears the mechanical strength of the entire wiring board 50 and improves heat dissipation. Therefore, the conductive pattern 11 is formed thicker than the other wiring layers, and the thickness is, for example, about 100 μm to 200 μm. As the material of the conductive pattern 11, a metal mainly made of copper, a metal mainly made of aluminum, an alloy, or the like can be adopted. Further, when a rolled metal such as a rolled copper foil is employed as the material of the conductive pattern 11, the mechanical strength and heat dissipation of the conductive pattern 11 can be further improved. The rolled metal has an excellent thermal conductivity of several percent compared to the plated film.

  The conductive patterns 11 are separated from each other at a predetermined interval by a separation groove 16 including a first separation groove 17 and a second separation groove 18. The width of the separation groove 16 is, for example, about 100 μm to 150 μm. Here, the first separation groove 17 is provided by selectively half-etching the conductive foil as the material of the conductive pattern 11 from the upper surface, and the second separation groove 18 is formed by selectively etching the back surface of the conductive foil. Is provided. The first separation groove 17 is filled with the first insulating layer 12 covering the upper surface of the conductive pattern 11, and the second separation groove 18 is filled with the second insulating layer 13 covering the lower surface of the conductive pattern 11. The

  Here, the side surfaces of the first separation groove 17 and the second separation groove 18 are curved, and the adhesion strength with the insulating layer filled therein is improved. In addition, the first separation groove 17 and the second separation groove 18 formed by isotropically proceeding wet etching constitute the separation groove 16 so that the vicinity of the central portion of the separation groove 16 is constricted (conductivity). The side surface of the pattern 11 protrudes outward). Also by this, the adhesion strength between the first insulating layer 12 and the second insulating layer 13 and the conductive pattern 11 is improved.

  The first insulating layer 12 and the second insulating layer 13 cover the upper and lower surfaces of the conductive pattern 11. The first insulating layer 12 is filled in the first separation groove 17, and the second insulation layer 13 is filled in the second separation groove 18. The thickness with which the first insulating layer 12 and the second insulating layer 13 cover the conductive pattern 11 is, for example, about 50 μm to 100 μm. Furthermore, as a material for the first insulating layer 12 and the second insulating layer 13, a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyethylene resin can be employed.

  Furthermore, when a resin material filled with fibrous or particulate filler is adopted as the material of the first insulating layer 12 and the second insulating layer 13, the thermal resistance of these resin layers is reduced, and the heat dissipation of the wiring board 50 is achieved. Can be improved. Silicon oxide or silicon nitride can be used as the filler material. In addition, when these fillers are mixed into the first insulating layer 12 and the second insulating layer 13, the thermal expansion coefficient of the insulating layer approaches the conductive material such as the conductive pattern 11, and a temperature change occurs. Warpage of the wiring board 50 is suppressed.

  The first wiring layer 14 is a wiring layer formed on the upper surface of the first insulating layer 12 and is formed by selectively etching a conductive film or a plating film attached to the first insulating layer 12. Since the thin conductive film or the like is patterned by etching, the first wiring layer 14 can be miniaturized, and the wiring width can be reduced to about 20 μm to 50 μm. Further, the first wiring layer 14 is electrically connected to the conductive pattern 11 via an interlayer connection portion 19 provided through the first insulating layer 12.

  In addition, circuit elements such as the chip element 22 and the semiconductor element 21 are electrically connected to the first wiring layer 14. The chip element 22 has electrodes at both ends fixed by a conductive bonding material such as solder. The semiconductor element 21 such as an LSI or a transistor is fixed to the land-like first wiring layer 14 via a conductive or insulating bonding agent, and the electrode provided on the upper surface is connected to the first via a fine metal wire. Connected to one wiring layer 14.

  The second wiring layer 15 is a wiring layer formed on the lower surface of the second insulating layer 13, and the wiring width can be reduced to about 20 μm to 50 μm similarly to the first wiring layer 14 described above. In addition, the second wiring layer 15 is electrically connected to the lower surface of the conductive pattern 11 through an interlayer connection portion 20 provided through the second insulating layer 13. An external electrode made of a conductive adhesive such as solder may be welded to the second wiring layer 15.

  The interlayer connection portion 19 and the interlayer connection portion 20 are made of a conductive material such as a plating film formed in a through hole provided by removing the insulating layer, and have a function of connecting each wiring layer and the conductive pattern. Here, the first wiring layer 14 and the conductive pattern 11 are connected by an interlayer connection portion 19 provided through the first insulating layer 12. Further, the second wiring layer 15 and the conductive pattern 11 are connected by the interlayer connection portion 20 provided through the second insulating layer 13. Here, each interlayer connection portion may function as a path through which an electric signal passes, or may be a so-called dummy member through which an electric signal does not pass. Even if the interlayer connection portion 19 does not allow electric signals to pass therethrough, it can be used as a thermal via hole through which heat passes through the interlayer connection portion 19.

  The first wiring layer 14 and the second wiring layer 15 described above can be conducted through the interlayer connection portion 19 and the like. In this case, both wiring layers are electrically connected through a route of the first wiring layer 14 → the interlayer connection portion 19 → the conductive pattern 11 → the interlayer connection portion 20 → the second wiring layer 15.

  Here, the first wiring layer 14 and the second wiring layer 15 described above may be covered with a solder resist (resin film) except for a portion connected to the outside and a portion where a circuit element is mounted. Here, referring to FIG. 1A, the lowermost second wiring layer 15 is almost entirely covered with a solder resist 53, and the resist 53 is partially removed, so that the second wiring layer 15 is removed. Is partially exposed. Further, an external electrode 54 made of solder or the like is welded to the lower surface of the second wiring layer 15 exposed from the resist 53. Furthermore, the first wiring layer 14 and the second wiring layer 15 exposed from the resist may be covered with a gold plating film in order to improve bonding properties.

  Further, a three-layered multilayer wiring composed of the first wiring layer 14, the conductive pattern 11 and the second wiring layer 15 is configured. By stacking a multilayer wiring layer through an insulating layer, four or more layers are formed. The wiring layer may be constructed.

  FIG. 1B shows an example of a planar shape of the conductive pattern 11 embedded in the wiring board 50. Here, a large number of conductive patterns 11 are separated by substantially uniform separation grooves 16. In other words, the conductive patterns 11 are electrically separated (insulated) by the first insulating layer 12 and the second insulating layer 13 filled in the separation groove 16. Therefore, by connecting each conductive pattern 11 to the first wiring layer 14 or the second wiring layer 15 via the interlayer connection portions 19 and 20, the potential of each conductive pattern 11 can be made different. For example, these conductive patterns 11 may be used as a signal pattern through which an electric signal input / output to / from the first wiring layer 14 and the second wiring layer 15 passes, or a fixed potential (for example, a power source) at a predetermined location. (Potential or ground potential) may be used as a pattern for extracting.

  The circuit device 10A of this embodiment is of the SIP type in which a large number of circuit elements such as the semiconductor element 21 and the chip element 22 are incorporated. Therefore, the circuit device 10A of this embodiment has a much larger amount of heat generation than the discrete type in which one semiconductor element is incorporated, and a larger and more complicated electric circuit is incorporated. From this, by separating the conductive patterns 11 that are the metal core layers from each other and making the potentials different, it is possible to give the metal core layer functions other than the improvement in heat dissipation, and to improve the functionality of the entire device and Miniaturization can be realized.

  Furthermore, the conductive pattern 11 is thermally coupled to each wiring layer via the interlayer connection portion 19 and the interlayer connection portion 20 whose upper and lower surfaces function as thermal vias, and is used as a pattern for improving heat dissipation. Also good. Here, a plurality of thermal via holes 46 are provided below the semiconductor element 21, and the semiconductor element 21 is thermally coupled to the conductive pattern 11 directly below via the thermal via hole 46. Thus, even if a power transistor having a large calorific value is adopted as the semiconductor element 21, a large amount of generated heat is favorably released to the outside through the thermal via hole 46 and the conductive pattern 11.

  Still further, referring to FIG. 1B, the outer peripheral end of the conductive pattern 11 that is the metal core layer is located inside the insulating layer 51 (the first insulating layer 12 and the second insulating layer 13). ing. That is, as shown in FIG. 1A, the side surface of the outermost peripheral portion of the conductive pattern 11 is covered with the insulating layer 51 including the first insulating layer 12 and the second insulating layer 13 and is not exposed to the outside. . As a result, a structure in which all the conductive patterns 11 are enclosed by the insulating layer 51 and are not exposed to the outside is realized, and the conductive patterns 11 can be insulated from the outside.

  Further, in the wiring board 50 described above, it is preferable that the remaining ratio of each layer (the ratio of the pattern or the area of the wiring layer to the area of the entire board) is substantially constant. For example, the remaining ratio of the first wiring layer 14, the conductive pattern 11, and the second wiring layer 15 is preferably about 80% ± 10%. Thus, by making the remaining rate of each layer substantially constant, it is possible to prevent the wiring substrate 50 from warping in a process involving heating, such as a wire bonding process. In addition, when the metal core layer is a solid one that is not patterned as shown in FIG. 2, the remaining rates of the first wiring layer 14 and the second wiring layer 15 may be made substantially equal in the above-described range.

  Furthermore, considering the heat dissipation of the entire substrate, the first wiring layer 14 made of a metal material has better thermal conductivity than the first insulating layer 12 made of a resin material, so the first wiring layer 14 etc. The higher the remaining rate of each layer, the better. For example, the remaining ratio of the first wiring layer 14, the conductive pattern 11, and the second wiring layer 15 is preferably 50% or more, more preferably 70% or more, and particularly preferably 80% or more. Thus, by increasing the residual ratio of each layer such as the first wiring layer 14, the steady thermal resistance is reduced, and the heat generated from the circuit elements such as the semiconductor element 21 can be satisfactorily externalized via the wiring substrate 50. Can be released. Here, when the metal core layer is a solid one that is not patterned as shown in FIG. 2, the residual ratio of the first wiring layer 14 and the second wiring layer 15 may be increased within the above-described range.

  Next, with reference to FIG. 2, the configuration of another form of circuit device 10B will be described. 2A is a cross-sectional view of the circuit device 10B, and FIG. 2B is a plan view showing the conductive foil 25 incorporated therein. The basic configuration of the circuit device 10 </ b> B is the same as that of the circuit device 10 </ b> A described above, and the difference is that it has a through connection part 23. The configuration of the circuit device 10B will be described focusing on this difference.

  Referring to FIG. 2A, the circuit device 10B includes a solid conductive foil 25 that is not patterned as a metal core layer. The thickness and material of the conductive foil 25 may be the same as those of the conductive pattern 11 described above. The conductive foil 25 may pass an electric signal input / output to / from a circuit element mounted on the first wiring layer 14, and a fixed potential (a ground potential or a power supply potential) may pass through the interlayer connection portion at a predetermined location. Or may be used only for heat dissipation by being electrically floating. By adopting such a conductive foil 25 as the metal core layer, the mechanical strength of the entire wiring board 50 is improved by the conductive foil 25. Furthermore, since a predetermined potential (ground potential or power supply potential) can be taken out from the conductive foil 25 via the interlayer connection portion 19 and the interlayer connection portion 20 at an arbitrary place, the first wiring layer 14 and the second wiring layer 14 The degree of freedom in designing the wiring layer 15 can be improved.

  A connection hole 42 is provided through the conductive foil 25 partially in the thickness direction. The connection hole 42 includes a first connection hole 27 provided from the upper surface of the conductive foil 25 and a second connection hole 28 provided from the lower surface of the conductive foil 25. The first connection hole 27 is filled with the first insulating layer 12, and the second connection hole 28 is filled with the second insulating layer 13. The diameter of the connection hole 42 having a circular shape in plan is, for example, about 100 μm to 200 μm.

  Referring to FIGS. 2A and 2B, the through-connection portion 23 is provided through the resin material filled in the connection hole 42, and the upper first wiring layer 14 and the lower layer are connected to each other. The second wiring layer 15 is electrically connected. Specifically, the through-connecting portion 23 is provided with a through-hole so that the first insulating layer 12 and the second insulating layer 13 that are located inside the through-hole 24 in plan view are penetrated, and copper or the like is provided in the through-hole. It is formed by embedding a conductive material. The diameter of the through connection portion 23 is, for example, about 50 μm to 100 μm. By providing the through connection portion 23, the first wiring layer 14 and the second wiring layer 15 can be electrically connected without passing through the conductive foil 25.

  Referring to FIG. 2B, the outer peripheral end of conductive foil 25 that is a metal core layer is located inside the outer peripheral end of wiring substrate 50. That is, since the side surface of the conductive foil 25 is covered with the insulating layer 51, the conductive foil 25 is insulated from the outside, and a sufficient withstand voltage is secured.

  A circuit device 10C having still another configuration will be described with reference to FIG. 3A is a cross-sectional view of the circuit device 10C, and FIG. 3B is a plan view of the conductive pattern 11 built in the circuit device 10C.

  The circuit device 10C shown in this figure is a combination of the circuit device 10A and the circuit device 10B described above. That is, the through connection portion 23 is provided inside the connection hole 42 provided in the conductive pattern 11. With this configuration, a more complicated electric circuit can be configured in the circuit device 10C.

  Referring to FIG. 3A, the first wiring layer 14 is electrically or thermally connected to the conductive pattern 11 through an interlayer connection portion 19 that penetrates the first insulating layer 12. Similarly, the second wiring layer 15 is electrically or thermally connected to the conductive pattern 11 via the interlayer connection portion 20 that penetrates the second insulating layer 13.

  In addition, the first wiring layer 14 and the second wiring layer 15 are electrically connected through the through connection portion 23 that penetrates the first insulating layer 12 and the second insulating layer 13 in the region where the connection hole 42 is provided. ing. Specifically, referring to FIG. 3B, a connection hole 42 is provided in the conductive pattern 11 </ b> A provided on the lower right side of the circuit device 10 </ b> C, and the through-connection portion 23 is formed inside the connection hole 42. Yes. Here, the through-connection portion 23 is not necessarily provided in the connection hole 42, and the through-connection portion 23 penetrates the first insulating layer 12 and the second insulating layer 13 located in the separation groove 16. May be provided.

  A circuit device 10D having another configuration will be described with reference to the cross-sectional view of FIG. The basic configuration of the circuit device 10D is the same as that of the circuit device 10A described above, and the difference is that a circuit element is built in the insulating layer.

  Here, a built-in element 26 is built in the second insulating layer 13 covering the lower surface of the conductive pattern 11. Here, the built-in element 26 is a chip-type element that is a chip capacitor or a chip resistor, and electrodes at both ends are connected to the conductive pattern 11 via a bonding material such as solder. Here, as the built-in element 26, in addition to the chip-type element, an active element such as LIS or a passive element can be generally employed. The built-in element 26 may be built into the second insulating layer 13, may be built into the first insulating layer 12, or may be built into both. By adopting the built-in element 26, the mounting density of the circuit device 10D can be improved.

  Next, the structure of the circuit device 10E having another configuration will be described with reference to FIG. 5A is a cross-sectional view of the circuit device 10E, and FIG. 5B is an enlarged cross-sectional view of the separation groove 16A.

  Referring to FIG. 5A, the basic configuration of circuit device 10E is basically the same as that of circuit device 10A shown in FIG. 1, and the difference is the first separation that forms separation groove 16A. The size of the groove 17A and the second separation groove 18A is different.

  That is, in the separation groove 16 shown on the left side of FIG. 5A, the depth and width of the first separation groove 17 and the second separation groove 18 provided in the upper part are substantially the same. With such a configuration, for example, the width of the separation groove 16 can be reduced to about 150 μm. However, with this configuration, when the circuit device 10E is viewed from above, a region where the width of the separation groove 16 is 150 μm is a dead space. That is, the interlayer connection 19 and the interlayer connection 20 cannot be provided in this region, and the degree of freedom in designing these interlayer connections is low.

  Therefore, in the circuit device 10E shown in this figure, the first and second separation grooves 17 and 18 constituting the separation groove 16 are made different in size to improve the wiring density. That is, in the separation groove 16A provided near the center of the circuit device 10E, the upper first separation groove 17A is formed smaller, and the lower second separation groove 18A is formed larger than the first separation groove 17A. As a result, the area occupied by the isolation trench 16A can be reduced, the degree of freedom in designing the interlayer connection portion 19 can be improved, and the degree of freedom in pattern layout of the first wiring layer 14 can be improved.

  With reference to FIG. 5B, the structure of the separation groove 16A will be described in detail. The separation groove 16A provided between the conductive patterns 11 includes an upper first separation groove 17A and a lower second separation groove 18A, and the second separation groove 18A is larger than the first separation groove 17A. Yes. As an example of a specific size, the width L1 of the first separation groove 17A is 100 μm, and the depth L3 is, for example, about 50 μm. On the other hand, the width L2 of the second separation groove 18A is 300 μm, and the depth L4 is about 100 μm.

  By comprising as mentioned above, the width | variety of 17 A of 1st separation grooves located in the upper part can be narrowed. For example, when the first separation groove 17 and the second separation groove 18 have the same width, the separation groove 16 has a width of about 150 μm. On the other hand, here, by making the width of the first separation groove 17A relatively small, the width L1 of the upper end of the separation groove 16A becomes about 100 μm. That is, according to the configuration of the present embodiment, the width of the upper end portion of the separation groove 16A is reduced by 50 μm, and the effective area of the upper surface of the conductive pattern 11 on which the interlayer connection portion 19 can be formed increases accordingly. Referring to FIG. 5B, an interlayer connection 19A is formed on the upper surface of the conductive pattern 11 corresponding to the upper side of the second separation groove 18A.

  As a result, the degree of freedom in designing the interlayer connection portion 19 is increased, and the degree of freedom in designing the first wiring layer 14 connected to the conductive pattern 11 via the interlayer connection portion 19 is also improved. In particular, since the first wiring layer 14 is a wiring layer on which the semiconductor element 21 and the like are mounted, many fine patterns are often required. Therefore, the configuration of the separation groove 16A increases the degree of freedom in designing the first wiring layer 14, and thus a more multifunctional semiconductor element 21 can be mounted.

  Here, the separation groove 16A described above is for electrically separating the conductive patterns 11 as the core layer, but this configuration is also applied to the connection hole 42 shown in FIG. Is possible. In this case, the first connection hole 27 is formed smaller than the second connection hole 28. Even with such a configuration, it is possible to reduce the positional restriction of the interlayer connection portion 19 and further improve the degree of freedom in designing the first wiring layer 14.

  Furthermore, in the above description, the second separation groove 18A is formed larger than the first separation groove 17A. However, even if the size relationship is reversed, the first separation groove 17A may be formed larger than the second separation groove 18A. good. This increases the effective area of the lower surface of the conductive pattern 11 and increases the degree of freedom in designing the interlayer connection portion 20 and the second wiring layer 15 shown in FIG.

  Next, the configuration of another form of circuit device 10F will be described with reference to FIG. 6A is a cross-sectional view of the circuit device 10F, and FIG. 6B is a cross-sectional view of the conductive pattern 11 built in the wiring board 50 of the circuit device 10F. The basic configuration of the circuit device 10F is the same as that of the circuit device 10A described above, and the difference is that wirings 47A and 47B made of a part of the conductive pattern 11 are provided.

  With reference to FIG. 6A, the wirings 47 </ b> A and 47 </ b> B are composed of a part of the conductive pattern 11, and are thinner and narrower than the other conductive patterns 11. Specifically, the wirings 47A and 47B are formed by adjusting the size and position of the separation groove in the etching process for separating the conductive pattern 11.

  First, the wiring 47A located on the left side in the drawing is provided with a wide first separation groove 17B on the upper side, and two second separation grooves 18B and 18C from below so as to be in contact with the first separation groove 17B. And formed. As a result, a wiring 47A is obtained in which the lower surface is located on the same plane as the lower surfaces of the other conductive patterns 11, and the upper surface is located below the upper surfaces of the other conductive patterns. Specifically, for example, when the second separation grooves 18B and 18C having a width of 500 μm and a width of 150 μm are provided at both ends below the first separation groove 17B, a wiring 47A having a width of 200 μm is obtained. Moreover, the thickness of the wiring 47A is about half of the conductive pattern 11, for example, about 50 μm to 100 μm.

  Furthermore, since the wide first separation groove 17B is etched deeper than the other separation grooves, the depth required for the second separation grooves 18B and 18C for pattern separation becomes shallower, and the second separation is accordingly made. The width of the grooves 18B and 18C can be reduced. For example, the depth of the first separation groove 17 </ b> B is at least half the thickness of the conductive pattern 11 (conductive foil as a material). Accordingly, the width of the second separation grooves 18B and 18C can be set to about 100 μm, for example, the wiring 47A and the other conductive pattern 11 can be brought close to each other, and the pattern density can be improved.

  The wiring 47B located on the right side in the drawing is formed by providing a wide second separation groove 18D from below and providing two first separation grooves 17C and 17D in contact with the second separation groove 18D from above. . The size of the wiring 47B may be the same as that of the wiring 47A described above. The upper surface of the wiring 47 </ b> B is located on the same plane as the upper surfaces of the other conductive patterns 11, and the lower surface is located above the other conductive patterns 11.

  Referring to FIG. 6B, the wiring 47 </ b> A extends longer than the other conductive pattern 11 and is connected to another wiring layer via the interlayer connection portion 20. Here, the wiring 47A is connected to the second wiring layer 15 shown in FIG. On the other hand, the wiring 47B is connected to the first wiring layer 14 via the two interlayer connection portions 19. Here, one of the wirings 47 </ b> A and 47 </ b> B may be connected to the first wiring layer 14 via the interlayer connection portion 19, and the other may be connected to the second wiring layer 15 via the interlayer connection portion 20.

  Further, similarly to the wiring 47B described above, the wide second separation groove 18D is deeply etched, so that the widths of the first separation grooves 17C and 17D can be reduced. As a result, the wiring 47B and other conductive materials can be reduced. The pattern 11 can be made to approach.

  As described above, by providing the wiring 47A and the like, the conductive pattern 11 functioning as the metal core layer can have a function of routing the wiring, and a more multifunctional electric circuit can be built in the circuit device 10F. Can do.

  Next, the configuration of another type of circuit device 10G will be described with reference to FIG. The circuit device 10G is different from the circuit device 10A described above in that the wiring substrate 50 is provided with the digging portions 52A and 52B.

  The dug portion 52A is provided by partially removing the first wiring layer 14 and the first insulating layer 12, and the upper surface of the conductive pattern 11 is exposed on the lower surface of the dug portion 52A. The semiconductor element 21 is mounted on the upper surface of the dug portion 52A using a bonding material such as solder. Furthermore, the electrode on the upper surface of the semiconductor element 21 is electrically connected to a pad made of the first wiring layer 14 and provided around the engraved portion 52A using a fine metal wire. In this way, by providing the digging portion 52A and mounting the semiconductor element 21 directly on the upper surface of the conductive pattern 11, the heat generated from the semiconductor element 21 is released to the outside through the conductive pattern 11 well. Can be made.

  The dug portion 52B is provided by partially removing the second insulating layer 13 and the second wiring layer 15, and the back surface of the conductive pattern 11 on which the semiconductor element 21 is mounted is exposed from the top surface. Yes. Further, an external electrode 54 made of solder or the like is welded to the lower surface of the conductive pattern 11 exposed inside the dug portion 52B. By doing in this way, the heat generated from the semiconductor element 21 is released to the outside through the conductive pattern 11 and the external electrode 54 without going through the resin material.

  Next, the configuration of another form of the circuit device 10H will be described with reference to the cross-sectional view of FIG. The configuration of the circuit device 10H is different from the other circuit devices described above in that the sealing resin 49 is provided. Here, the sealing resin 49 is formed so that the upper surfaces of the chip element 22, the semiconductor element 21, and the wiring substrate 50 are covered. The sealing resin 49 is formed by an injection mold using a thermoplastic resin or a transfer mold using a thermosetting resin. The configuration of the sealing resin 49 is applicable to all the circuit devices described above.

  With reference to a cross-sectional view of FIG. 8B, the configuration of another form of circuit device 10I will be described. The configuration of the circuit device 10I is basically the same as that of the circuit device 10F described above, and the difference is in the configuration of the wiring 47A and the like. This difference will be described below.

  The built-in element 26 is fixed to the upper surface of the wiring 47A formed on the left side on the paper. Here, a chip capacitor, a chip resistor, or the like is employed as the built-in element 26. The upper surface of the wiring 47 </ b> A is formed such that the position of the upper surface is lower than the other conductive patterns 11 in accordance with the depth of the first separation groove 17 </ b> B. Therefore, an increase in the thickness of the wiring board 50 due to the mounting of the built-in element 26 is suppressed.

  Further, two wirings 47B and 47C are formed close to each other on the right side on the paper surface. The wiring 47B located in the upper part is separated by the first separation grooves 17C and 17D, and the first separation groove 17D is formed wider than the first separation groove 17C. Further, the lower wiring 47C is separated by the second separation grooves 18D and 18E, and the second separation groove 18D is formed wider than the second separation groove 18E.

  Here, by arranging the upper first separation groove 17D and the lower second separation groove 18D so as to overlap each other in a plane, the wiring 47B and the wiring 47C can be made extremely close to each other. For example, the distance D1 between the wiring 47B and the wiring 47C can be shortened to about 20 μm. This greatly contributes to pattern miniaturization.

<Second Embodiment>
In the present embodiment, a method for manufacturing the circuit device 10A having the configuration shown in FIG. 1 will be described with reference to the cross-sectional views of FIGS.

  Referring to FIG. 9A, first, the first separation groove 17 is formed by partially etching the surface of the conductive foil 30. The conductive foil 30 is made of a metal or alloy whose main material is copper or aluminum, and has a thickness of about 100 μm to 200 μm, for example. In addition, when a rolled metal subjected to a rolling process is used as the material of the conductive foil 30, the rolled metal is excellent in mechanical strength, so that cracks and deformation of the substrate occur in the middle of the manufacturing process. Can be suppressed.

  Here, after covering the upper surface of the conductive foil 30 excluding the region where the first separation groove 17 is to be formed with a resist (not shown), the conductive foil 30 is etched from the upper surface using this resist as an etching mask. doing. In this step, the conductive foil 30 is wet etched using an etchant containing iron chloride or copper chloride.

  The depth of the first separation groove 17 formed in this step is preferably about half of the thickness of the conductive foil 30. Accordingly, the separation groove 16 can be constituted by the first separation groove 17 and the second separation groove 18 formed by isotropically proceeding wet etching, and the width of the separation groove 16 is narrowed to about half of the thickness of the separation groove. (See FIG. 9C). As a result, the area of the conductive pattern occupying the entire wiring board increases, and the mechanical strength and heat dissipation characteristics of the wiring board are improved.

  For example, if the thickness of the conductive foil 30 is in the range of 100 μm to 200 μm, the depth of the first separation groove 17 may be about 50 μm to 100 μm. Further, considering that the wet etching in this step proceeds isotropic, the width of the first separation groove 17 is 50 μm to 100 μm depending on the thickness of the conductive foil 30.

  After the first separation groove 17 is formed by the above process, a resist (not shown) used as an etching mask is peeled off from the conductive foil 30 and removed.

  Referring to FIG. 9B, next, the upper surface of the conductive foil 30 is covered with the first insulating layer 12 so as to fill the first separation groove 17, and the first insulating layer 12 is covered with the first insulating layer 12. A conductive film 31 is attached. As a manufacturing method of the first insulating layer 12, a semi-solid or liquid resin material may be applied to the upper surface of the conductive foil 30 and then heat-cured, or a film-shaped resin material may be vacuumed on the upper surface of the conductive foil 30. You may make it contact | adhere with a press. In this step, since the first separation groove 17 does not penetrate the conductive foil 30 and terminates in the middle of the thickness direction, even if the liquid or semi-solid first insulating layer 12 is applied to the conductive foil 30, Problems such as leakage of the resin material from the first separation groove 17 do not occur.

  Since the side surface of the first separation groove 17 is a curved surface formed by wet etching, the first insulating layer 12 is fitted to the side surface of the first separation groove 17 and the adhesion strength between the two is strong.

  Further, the upper surface of the first insulating layer 12 is entirely covered with the first conductive film 31. Here, the first insulating layer 12 to which the first conductive film 31 is adhered may be laminated on the conductive foil 30, or after the first insulating layer 12 is in close contact with the conductive foil 30, 31 may be attached to the first insulating layer 12. Moreover, the 1st electrically conductive film 31 may be comprised from a rolled metal, and may be formed by the plating method. The thickness of the first conductive film 31 is, for example, about 20 μm to 50 μm.

  As the resin material constituting the first insulating layer 12, both a thermosetting resin or a thermoplastic resin can be employed. Further, a resin material mixed with a fibrous or particulate filler may be adopted as the first insulating layer 12. The thickness of the first insulating layer 12 covering the upper surface of the conductive foil 30 is, for example, about 50 μm to 100 μm.

  With reference to FIG. 9C, next, the second separation groove 18 is formed by selectively etching from the back surface of the conductive foil 30, and the conductive foil 30 is separated to obtain each conductive pattern 11. Specifically, first, a resist (not shown) is formed so that the back surface of the conductive foil 30 in a region corresponding to the first separation groove 17 is exposed. Next, the second separation groove 18 is formed by wet-etching the back surface of the portion of the conductive foil 30 exposed from the resist (not shown). Here, the second separation groove 18 is formed by wet etching until the first insulating layer 12 filled in the first separation groove 17 is exposed. In other words, the second separation groove 18 is formed until it reaches the first separation groove 17, and the first insulating layer 12 filled in the first separation groove 17 is exposed from the second separation groove 18.

  The depth of the second separation groove 18 needs to be at least greater than the depth at which the first insulating layer 12 filled in the first separation groove 17 is exposed. Therefore, for example, when the thickness of the conductive foil 30 is 100 μm to 200 μm and the depth of the first separation groove 17 is 50 μm to 100 μm, the depth of the second separation groove 18 is about 50 μm to 100 μm. That is, the distance obtained by adding the depth of the first separation groove 17 and the depth of the second separation groove 18 needs to be equal to or greater than the thickness of the conductive foil 30. In order to reliably expose the first insulating layer 12 filled in the first separation groove 17 from the second separation groove 18, a distance obtained by adding the depth of the first separation groove 17 and the depth of the second separation groove 18. Is preferably longer by about several tens of μm than the thickness of the conductive foil 30.

  Through the above steps, a conductive pattern having a shape as shown in FIG.

  Here, the second separation groove 18 is not necessarily provided. For example, the conductive foil 30 may be entirely removed from the back surface without using an etching mask in this step, and the first insulating layer 12 filled in the first separation groove 17 may be exposed downward. In this case, the conductive pattern 11 is separated only by the first separation groove 17.

  Next, referring to FIG. 9D, the back surface of the conductive pattern 11 is covered with the second insulating layer 13, and the second conductive film 32 is attached to the surface of the second insulating layer 13. Here, the second insulating layer 13 is formed so that the lower surface of the conductive pattern 11 is covered and the second separation groove 18 is filled. The thickness, composition, and formation method of the second insulating layer 13 may be the same as those of the first insulating layer 12 described above. Furthermore, the thickness, composition, and formation method of the second conductive film 32 formed on the lower surface of the second insulating layer 13 may be the same as those of the first conductive film 31 described above.

  Referring to FIG. 10A, next, the first conductive film 31 and the second conductive film 32 in a region to be connected to the conductive pattern 11 are partially removed. Specifically, after applying a resist 45 functioning as an etching mask over the entire upper surface of the first conductive film 31, exposure / development processing is performed, and the surface of the first conductive film 31 at a location connected to the conductive pattern 11. To expose. Further, wet etching is performed to remove the first conductive film 31 exposed from the resist 45. A similar process is performed on the second conductive film 32 to partially remove the second conductive film 32. After this step is completed, the resist 45 is peeled off and removed.

  Referring to FIG. 10B, next, laser processing using the first conductive film 31 as a mask is performed, and the first insulating layer 12 exposed from the exposed portion of the first conductive film 31 is removed and exposed. Hole 33 is formed. Here, the first insulating layer 12 exposed from the first conductive film 31 is laser-etched so that the upper surface of the conductive pattern 11 is exposed from the bottom of the exposed hole 33. Further, in this step, the second insulating layer 13 exposed from the second conductive film 32 is removed to form an exposed hole 34 in which the conductive pattern 11 is exposed at the bottom. If a residue such as an evaporated resin material remains on the bottom of the exposure hole 33 or the like by laser irradiation in this step, desmear treatment is performed to remove the residue. Side surfaces such as the exposure holes 33 formed in this step are inclined surfaces whose opening area increases toward the outside. Therefore, in the next process of performing the plating process, the flow of the plating solution in the exposed hole 33 is promoted, and there is an advantage that the plated film can easily adhere to the inner wall of the exposed hole 33.

  Referring to FIG. 10C, next, an interlayer connection portion 19 or the like is formed inside the exposure hole 33, and each wiring layer is electrically connected to the conductive pattern. The interlayer connection portion 19 may be formed of a metal film formed in the exposed hole 33 by a plating method, or a conductive material such as solder or conductive resin paste may be embedded in the exposed hole 33. When the interlayer connection portion 19 is formed by plating, first, a thin metal film (seed layer) by electroless plating is provided on at least the inner wall of the exposure hole 33, and then a voltage is applied to the seed layer to perform electrolysis. A plating film made of copper having a thickness of about several μm is formed by a plating method. By the same method, the interlayer connection portion 20 is provided on the side surface of the exposure hole 34 that penetrates the second insulating layer 13. Here, when filling plating is performed, a plating film can be generated so that the exposed hole 33 and the exposed hole 34 are embedded.

  After the interlayer connection portions 19 and 20 are formed, the first conductive layer 31 and the second conductive layer 32 are selectively etched to pattern the first wiring layer 14 and the second wiring layer 15. Since the thickness of the first conductive film 31 and the second conductive film 32 is about 10 μm, for example, the wiring width can be reduced to about 20 μm to 50 μm.

  Here, the first wiring layer 14 is stacked above the conductive pattern 11 and the second wiring layer 15 is stacked below the conductive pattern 11 to realize a three-layer multilayer wiring. Four or more wiring layers may be realized by stacking layers. By increasing the number of wiring layers to be stacked, a larger-scale electric circuit can be incorporated into the wiring board.

  After the above steps are completed, the first wiring layer 14 and the second wiring layer 15 may be covered with a solder resist made of a resin film, except for a place where circuit elements are mounted or connected to the outside. .

  Referring to FIG. 10D, next, circuit elements are mounted on the first wiring layer 14 to be electrically connected. Here, the chip element 22 is connected to the first wiring layer 14 via a bonding material such as solder. Further, the back surface of the semiconductor element 21 such as LSI is mounted on the land-like first wiring layer 14 via a bonding material, and the electrode on the front surface is connected to the first wiring layer 14 via a fine metal wire.

  Further, after the resist 53 is formed so as to cover the second wiring layer 15, the resist 53 is removed so that the second wiring layer 15 is partially exposed, and the exposed second wiring layer 15 is formed. An external electrode 54 made of solder is welded. Further, the wiring board 50 is separated into each unit at a location where a one-dot chain line is shown. Further, after the sealing resin is formed on the upper surface of the wiring substrate 50 so as to cover the semiconductor element 21 and the like, the separation step may be performed. In this step, each wiring layer exposed from the resist 53 may be covered with a gold plating film.

  In this step, since the wiring board 50 is separated at the position where the separation groove 16 is formed (that is, where the conductive pattern 11 and the first wiring layer 14 are not present), the cutting means such as a dicing saw is used. Abrasion can be suppressed and separation can be performed. Moreover, since the conductive material such as copper is not separated, the generation of burrs associated with the separation is suppressed.

  Through the above process, for example, the circuit device 10A having the configuration shown in FIG. 1 is manufactured.

  Here, in the manufacturing method described above, the wiring layer is formed by etching the film-like conductive film (the first conductive film 31 and the second conductive film 32), but a plating film may be used instead of the conductive film. it can. In this case, the first conductive layer 31 and the second conductive layer 32 are not provided, and after forming the exposed holes 33 and the like shown in FIG. A metal film covering 13 is provided. Thereafter, the metal film is selectively etched to form the first wiring layer 14 and the second wiring layer 15 shown in FIG. According to the manufacturing method in which the wiring layer is provided by this plating film, the wiring layer is formed by etching a thin metal film having a thickness of about 5 μm to 10 μm, and therefore, a fine wiring layer having a width of about 40 μm or less can be formed. it can.

  Further, when the circuit device 10 </ b> D shown in FIG. 4 is manufactured, the built-in element 26 may be mounted on the conductive pattern 11 before the second insulating layer 13 is formed. Furthermore, when manufacturing the circuit device 10 </ b> E shown in FIG. 5, the width of the second separation groove 18 may be made larger than that of the first separation groove 17 in the above process.

<Third Embodiment>
Next, a method for manufacturing the circuit device 10B having the configuration shown in FIG. 2 will be described with reference to the cross-sectional views of FIGS. The method for manufacturing the circuit device 10B is basically the same as the method for manufacturing the circuit device 10A described above. The difference between the two is that a through-connecting portion 23 that penetrates each insulating layer is formed, and that a metal core is constituted by a solid conductive foil 25 that is not patterned. A method for manufacturing the circuit device 10B will be described focusing on this difference.

  Referring to FIG. 11A, first, the conductive foil 25 is partially etched from the upper surface to provide the first connection hole 40. As the material of the conductive foil 25, a metal having a thickness of about 100 μm to 200 μm is adopted. Specifically, a metal mainly made of copper, a metal mainly made of aluminum, an alloy, a rolled metal, or the like is adopted. .

  The first connection hole 40 is formed by wet-etching the conductive foil 25 exposed from the etching mask after selectively covering the upper surface of the conductive foil 25 with an etching mask (not shown). Here, the 1st connection hole 40 is formed corresponding to the location in which the penetration connection part which penetrates the conductive foil 25 and connects wiring layers is provided. The depth of the first connection hole 40 is, for example, about half the thickness of the conductive foil 25 and is about 50 μm to 100 μm. Further, the width (diameter) of the first connection hole 40 formed by wet etching that proceeds isotropically is about 50 μm to 100 μm, similarly to the depth.

  Referring to FIG. 11B, next, the upper surface of the conductive foil 25 is covered with the first insulating layer 12 so as to fill the first connection holes 40, and the first upper surface of the first insulating layer 12 is covered with the first insulating layer 12. A conductive film 31 is attached. Further, the conductive foil 25 is removed from the back surface so that the first insulating layer 12 filled in the first connection hole 40 is exposed. Here, the connection hole 42 is constituted by the first connection hole 40 and the second connection hole 41 which are continuous in the thickness direction. The basic process of this step is the same as that of the second embodiment described above.

  Here, the second connection hole 41 is formed by selectively wet-etching the conductive foil 25 in the region below the first connection hole 40. The first insulating layer 12 filled in the first connection hole 40 is exposed from the second connection hole 41. Also here, in order to expose the first insulating layer 12 filled in the first connection hole 40 to the outside, the length obtained by adding the depth of the first connection hole 40 and the depth of the second connection hole 41 is the conductive length. It needs to be longer than the thickness of the foil 25. Here, the conductive foil 25 is completely removed from the back surface by so-called maskless etching that does not use an etching mask without performing selective etching for forming the second connection hole 41, and the first connection is made. The first insulating layer 12 filled in the holes 40 may be exposed on the back surface of the conductive foil 25.

  Referring to FIG. 11C, next, the back surface of the conductive foil 25 is covered with the second insulating layer 13 so that the second connection holes 41 are filled, and the lower surface of the second insulating layer 13 is further covered. The second conductive film 32 is attached to the substrate. The details of this process are also the same as in the second embodiment described above.

  Referring to FIG. 11D, next, the first conductive film 31 and the second conductive film 32 are partially etched to provide an exposed portion 43 and an exposed portion 44. The exposed portion 43 is provided corresponding to a location where an interlayer connection portion that connects the first conductive film 31 or the second conductive film 32 and the conductive pattern 11 is formed. Further, the exposed portion 44 is provided by removing the first conductive film 31 located above the connection hole 42. Further, the exposed portion 44 is also provided below the connection hole 42 by removing the second conductive film 32. By providing the exposed portion 43 and the exposed portion 44, laser etching is performed using the first conductive film 31 and the second conductive film 32 as a mask, and the first insulating layer 12 and the second insulating layer 13 are partially removed. Can do.

  Referring to FIG. 12A, next, the first insulating layer 12 exposed from the first conductive film 31 is removed by irradiating a laser to form an exposed hole 33 and a through hole 24. The upper surface of the conductive pattern 11 is exposed from the bottom of the exposure hole 33. Further, the second insulating layer 13 exposed from the second conductive film 32 is removed with a laser to form an exposed hole 34, and the lower surface of the conductive pattern 11 is exposed from the bottom of the exposed hole 34. In addition, with respect to the through hole 24, the first insulating layer 12 and the second insulating layer 13 filled in the connection hole 42 can be removed by irradiating laser from one main surface to reach the other main surface. good. Furthermore, the through-hole 24 may be formed partway with a laser irradiated from one main surface, and the remaining through-hole 24 may be formed with a laser irradiated from the other main surface.

  In this step, a through hole 24 penetrating the first insulating layer 12 and the second insulating layer 13 filled in the connection hole 42 is provided. The diameter of the through hole 24 is smaller than that of the connection hole 42 and is, for example, about 50 μm to 100 μm. Further, the through hole 24 is provided apart from the side wall of the connection hole 42 in order to insulate the connection portion formed later in the through hole 24 from the conductive pattern 11.

  Referring to FIG. 12B, next, a metal film is formed by an electroless plating method and an electrolytic plating method, and interlayer connection portions 19 and 20 and through connection portion 23 are formed. An interlayer connection portion 19 made of a plating film is formed in the exposed hole 33 penetrating the first insulating layer 12 to connect the first conductive film 31 and the conductive pattern 11. Further, an interlayer connection portion 20 made of a plating film is provided inside the exposed hole 34 that penetrates the second insulating layer 13 to connect the second conductive film 32 and the conductive pattern 11. Further, the through-connection portion 23 is formed by the metal film generated inside the through-hole 24. The first conductive film 31 and the second conductive film 32 stacked with the conductive pattern 11 interposed therebetween are electrically connected without passing through the conductive foil 25 by the through connection portion 23.

  Referring to FIG. 12C, next, the first conductive layer 31 and the second conductive layer 32 are selectively etched, and the first wiring layer 14 and the second wiring layer 15 are patterned. Here, the first wiring layer 14 and the second wiring layer 15 are electrically connected via the through connection portion 23.

  Next, referring to FIG. 12D, circuit elements are mounted on the first wiring layer 14. Here, the chip element 22 and the semiconductor element 21 are connected to the first wiring layer 14.

  Through the above steps, the circuit device 10B having the structure shown in FIG. 2 is manufactured. Here, when the circuit device 10 </ b> C having the structure shown in FIG. 3 is manufactured, the connection hole 42 is provided at the same time in the process of manufacturing the separation groove 16, and the through-connection part 23 is formed at the same time as the process of forming the interlayer connection 20. Is provided.

<Fourth embodiment>
In this embodiment, a method for manufacturing the circuit device 10F having the configuration shown in FIG. 6 will be described with reference to FIG. This manufacturing method is basically the same as that of the second embodiment described above, and the difference is that the width and position of each separation groove are adjusted in order to form the wiring 47A and the like.

  Referring to FIG. 13A, first, first separation grooves 17 are formed from the upper surface of conductive foil 30 by wet etching. If the purpose is simply to separate the conductive pattern 11 in a later step, the width of the first separation groove 17 may be made uniform, but here, in order to form a wiring, the wide first separation groove 17 is formed. Is provided. Specifically, the width of the first separation groove 17B provided on the left side on the paper surface is, for example, about 500 μm. On the other hand, the width of the first separation grooves 17C and 17D is, for example, about 150 μm. In this step, the first separation groove 17 is formed by selectively covering the upper surface of the conductive foil 30 with an etching mask and performing wet etching.

  Referring to FIG. 13B, next, the upper surface of the conductive foil 30 is covered with the first insulating layer 12 so that the first separation grooves 17B and the like are filled. A film-like first conductive film 31 is attached to the upper surface.

  Referring to FIG. 13C, next, the conductive foil 30 is selectively wet-etched from the back surface to separate the conductive patterns 11 and further form wirings 47A and the like. First, a second separation groove 18 having a width substantially equal to that of the first separation groove 17 is formed at the right end in the drawing, and an electrically isolated conductive pattern 11 is obtained by these separation grooves.

  On the other hand, two second separation grooves 18B and 18C are provided below the wide first separation groove 17B. The conductive foil remaining between the second separation grooves 18B and 18C becomes the wiring 47A. The widths of the second separation grooves 18 </ b> B and 18 </ b> C may be the same as those of the other second separation grooves 18 provided for separating the conductive pattern 11. Specifically, if the width of the first separation groove 17B is 500 μm and the widths of the second separation grooves 18B and 18C located therebelow are 150 μm, the width of the wiring 47A is about 200 μm. Here, the second separation grooves 18B and 18C do not have to be located all below the first separation groove 17B, and a part of the second separation grooves 18B and 18C is located below the first separation groove 17B. However, other parts may protrude outside. That is, the cross-sections of the second separation grooves 18B and 18C and the first separation groove 17B are in contact with each other, and the wiring 47A is separated from the adjacent conductive pattern 11. The lower surface of the wiring 47A formed by the first separation groove 17B and the like having the above configuration is located on the same plane as the lower surface of the other conductive pattern 11, and the upper surface is located below the upper surface of the other conductive pattern 11. ing.

  A second separation groove 18D having a large width is formed below the first separation grooves 17C and 17D. The width of the second separation groove 18D may be the same as that of the first separation groove 17B described above, for example, about 500 μm. A portion surrounded by the first separation grooves 17C and 17D and the second separation groove 18D is the wiring 47B. The size of the cross section of the wiring 47B may be the same as that of the wiring 47A described above. The upper surface of the wiring 47B is positioned on the same plane as the upper surfaces of the other conductive patterns 11, and the lower surface thereof is positioned above the other conductive patterns 11.

  Referring to FIG. 13E, next, after providing interlayer connection portions 19 and 20 to form first wiring layer 14 and second wiring layer 15, circuit elements such as semiconductor element 21 are connected to wiring board 50. The circuit device 10F shown in FIG. 6 is manufactured. The details of this step are the same as in the other embodiments described above. In this step, the interlayer connection portions 19 and 20 are also formed at locations where the wirings 47A and 47B are provided, and these wirings are connected to the first wiring layer 14 or the second wiring layer 15.

<Fifth embodiment>
Next, a method for manufacturing the circuit device 10G having the configuration shown in FIG. 7 will be described with reference to FIG. This manufacturing method is basically the same as that of the second embodiment described above, and the difference is that a dug 52A and the like are provided.

  Referring to FIG. 14A, first, a substrate on which a conductive pattern 11 and the like are formed is prepared. Here, the upper and lower surfaces of the conductive pattern 11 separated by the separation groove are covered with the first insulating layer 12 and the second insulating layer 13, and the upper surface of the first insulating layer 12 is covered with the first conductive film 31, The lower surface of the two insulating layer 13 is covered with the second conductive film 32.

  Referring to FIG. 14B, next, the dug portion 52A removes the first conductive film 31 and the first insulating layer 12 corresponding to the portion where the circuit element is to be mounted and its peripheral portion. Provided. A specific removal method may be performed only by laser irradiation, or may be performed by a combination of etching treatment and laser irradiation. Since the thickness of the first conductive film 31 is about several μm, the first conductive film 31 and the first insulating layer 12 below the first conductive film 31 can be removed by irradiating with a laser having a large output. In the case where the trench 52A is formed by combining etching and laser, first, the first conductive film 31 in the region where the trench 52A is to be formed is removed by selective etching using an etching mask. The first insulating layer 12 is exposed. Next, the first insulating layer 12 exposed from the first conductive film 31 is removed by laser irradiation. In any method, the upper surface of the conductive pattern 11 is exposed on the bottom surface of the engraved portion 52A.

  The formation method of the dug portion 52B is the same as that of the dug portion 52A. In this case, the second conductive film 32 and the second insulating layer 13 above the second conductive film 32 are partially removed to provide a dug 52B where the lower surface of the conductive pattern 11 is exposed. Here, since the digging portion 52B is provided in order to bring the external electrode made of solder or the like into contact with the back surface of the conductive pattern 11, its planar size is smaller than that of the semiconductor element 21 to be mounted later. May be.

  Referring to FIG. 14C, next, after forming the first wiring layer 14 and the like, circuit elements are mounted to complete the circuit device. Specifically, after forming the first wiring layer 14 and the second wiring layer 15, the semiconductor element 21 and the chip element 22 are electrically connected to the first wiring layer 14. In this embodiment, the semiconductor element 21 is accommodated in the digging portion 52A, and the semiconductor element 21 is fixed to the upper surface of the conductive pattern 11 through a bonding material such as solder. Then, the pad formed of the first wiring layer 14 located in the peripheral portion of the dug portion 52A and the electrode formed on the upper surface of the semiconductor element 21 are electrically connected by a thin metal wire.

  Further, an external electrode 54 made of solder or the like is welded to the lower surface of the conductive pattern 11 exposed from the dug portion 52B. By forming in this way, the semiconductor element 21 is directly fixed to the conductive pattern 11. Therefore, the heat generated from the semiconductor element 21 is released to the outside through the conductive pattern 11 and the external electrode 54.

It is a figure which shows the circuit apparatus of this invention, (A) is sectional drawing, (B) is a top view. It is a figure which shows the circuit apparatus of this invention, (A) is sectional drawing, (B) is a top view. It is a figure which shows the circuit apparatus of this invention, (A) is sectional drawing, (B) is a top view. It is sectional drawing which shows the circuit apparatus of this invention. It is a figure which shows the circuit apparatus of this invention, (A) is sectional drawing, (B) is expanded sectional drawing. It is a figure which shows the circuit apparatus of this invention, (A) is sectional drawing, (B) is a top view. It is sectional drawing which shows the circuit apparatus of this invention. It is a figure which shows the circuit apparatus of this invention, (A) is sectional drawing, (B) is sectional drawing. It is a figure which shows the manufacturing method of the circuit apparatus of this invention, (A)-(D) is sectional drawing. It is a figure which shows the manufacturing method of the circuit apparatus of this invention, (A)-(D) is sectional drawing. It is a figure which shows the manufacturing method of the circuit apparatus of this invention, (A)-(D) is sectional drawing. It is a figure which shows the manufacturing method of the circuit apparatus of this invention, (A)-(D) is sectional drawing. It is a figure which shows the manufacturing method of the circuit apparatus of this invention, (A)-(E) is sectional drawing. It is a figure which shows the manufacturing method of the circuit apparatus of this invention, (A)-(C) is sectional drawing. It is sectional drawing which shows the structure and manufacturing method of the multilayer substrate of background art.

Explanation of symbols

10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H, 10I Circuit device 11, 11A Conductive pattern 12 First insulating layer 13 Second insulating layer 14 First wiring layer 15 Second wiring layer 16, 16A Separation groove 17 , 17A, 17B, 17C, 17D First separation groove 18, 18A, 18B, 18C, 18D, 18E Second separation groove 19, 19A, 20 Interlayer connection part 21 Semiconductor element 22 Chip element 23 Through-connection part 24 Through hole 25 Conduction Foil 26 Built-in element 27 First connection hole 28 Second connection hole 30 Conductive foil 31 First conductive film 32 Second conductive film 33, 34 Exposed hole 40 First connection hole 41 Second connection hole 42 Connection hole 43, 44 Exposed portion 45 Resist 46 Thermal via hole 47A, 47B, 47C Wiring 48 Metal fine wire 49 Sealing resin 50 Wiring board 51 Insulating layer 5 A, 52B engraved part 53 resist 54 external electrodes

Claims (2)

Comprising a wiring board and a plurality of circuit elements mounted on the wiring board;
The wiring board includes a metal core layer mainly composed of copper, a first insulating layer made of an epoxy resin covering an upper surface and a lower surface of the metal core layer, a second insulating layer made of the epoxy resin , and the first A first wiring layer and a second wiring layer formed on the upper surface of the insulating layer and the lower surface of the second insulating layer;
The metal core layer includes a plurality of conductive patterns separated from each other by a separation groove, and the plurality of conductive patterns are electrically insulated from each other by filling the separation groove with the insulating layer.
The first insulating layer positioned in the first conductive pattern of the plurality of conductive patterns is provided with a semiconductor element in the plurality of circuit elements, and the first insulating layer positioned below the semiconductor element Are provided with a plurality of first thermal via holes,
A second thermal via hole is provided in the second insulating layer located below the semiconductor element, and the area of the first wiring layer, the area of the conductive pattern, and the area of the second wiring layer with respect to the area of the wiring substrate A circuit device characterized in that the ratio is equal to or greater than 70% . A first wiring layer provided on the first insulating layer and a second wiring layer provided on a lower surface of the second insulating layer;
The first insulating layer and the second insulating layer corresponding to the first thermal via hole and the second thermal via hole are removed to form a first through hole and a second through hole, and the first wiring layer and the first thermal via hole are formed. The conductive pattern is thermally coupled by a conductive material provided in the first through hole, and the second wiring layer and the first conductive pattern are thermally coupled by a conductive material provided in the second through hole. The circuit device according to claim 1, which is coupled.

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