JP2008060372A - Circuit apparatus, method of manufacturing the same, wiring substrate, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the flexibility of design when designing a wiring layer by reducing the planar size of an interlayer connection which penetrates through an insulating layer and makes the wiring layers conducted to each other. <P>SOLUTION: In a circuit apparatus, a projection 60 projecting in a thickness direction is provided on the upper surface of and the lower surface of a conductive pattern 11 of a metal core layer, and an interlayer connection for making wiring layers conduct to each other is provided on a region in which the projection 60 is provided. Specifically, the projection 60 is provided on the upper surface of the conductive pattern 11, and the interlayer connection 19 for electrically connecting the conductive pattern 11 with a first wiring layer 14 is provided in such a manner that the interlayer connection penetrates through a first insulating layer 12. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a circuit device and a manufacturing method thereof, and more particularly, to a circuit device including a wiring board in which a metal core layer made of a thick metal is incorporated and a manufacturing method thereof. Furthermore, the present invention relates to a wiring board having a metal core layer made of a thick metal and a method for manufacturing the same.

  As electronic devices such as mobile phones become smaller and more functional, circuit devices housed therein are mainly provided with a multilayer wiring layer. A circuit device having a multilayer substrate 107 will be described with reference to FIG.

  Here, a circuit device is configured by mounting circuit elements such as a package 105 on the first wiring layer 102 </ b> A formed on the upper surface of the multilayer substrate 107.

  In the multilayer substrate 107, wiring layers are formed on the front surface and the back surface of the base material 101 made of a resin such as glass epoxy. Here, the first wiring layer 102 </ b> A and the second wiring layer 102 </ b> B are formed on the upper surface of the substrate 101. The first wiring layer 102A and the second wiring layer 102B are stacked with an insulating layer 103 interposed therebetween. A third wiring layer 102 </ b> C and a fourth wiring layer 102 </ b> D are stacked on the lower surface of the substrate 101 with an insulating layer 103 interposed therebetween. Each wiring layer is connected at a predetermined location by a connecting portion 104 provided through the insulating layer 103.

  A package 105 is fixed to the uppermost first wiring layer 102A. Here, the package 105 in which the semiconductor element 105A is resin-sealed is surface-mounted via a connection electrode 106 made of solder or the like. In addition to the package 105, passive elements such as chip capacitors and chip resistors, bare semiconductor elements, and the like may be mounted on the surface of the multilayer substrate 107. Here, the thickness of the multilayer substrate 107 is, for example, about 1 mm.

A method for manufacturing the multilayer substrate 107 having the above-described configuration is as follows. First, the second wiring layer 102B and the third wiring layer 102C are formed on the upper and lower surfaces of the base material 101 made of a resin-based material such as an epoxy resin. These wiring layers are formed by etching or selectively plating the attached conductive film. Next, the second wiring layer 102B and the third wiring layer 102C are covered with an insulating layer 103 made of resin. Further, a first wiring layer 102A and a fourth wiring layer 102D are formed on the surface of the insulating layer 103. The method of forming these wiring layers is the same as that of the second wiring layer 102B and the like described above. Further, a connection portion 104 that penetrates the insulating layer 103 and connects the first wiring layer 102A and the second wiring layer 102B is formed.
JP 2003-324263 A

  However, in the circuit device including the multilayer substrate 107 having the above-described configuration, the area occupied by the connection portion 104 is large, which has a problem that the size reduction of the multilayer substrate 107 is hindered. For example, when the thickness of the insulating layer 103 covering the first wiring layer 102B is 100 μm, a hole that penetrates the insulating layer 103 is provided by a removal method such as laser irradiation, and the connecting portion 104 is provided in this hole. When formed, the planar size of the connecting portion 104 is, for example, a circular shape having a diameter of about 100 μm. If a large number of connection portions 104 having such a size are provided, the first wiring 102A and the like cannot be freely routed in the region where the connection portions 104 are provided, so that the degree of freedom in pattern design is reduced. . As a result, miniaturization of the multilayer substrate 107 is hindered by unnecessary routing of the first wiring layer 102A and the like.

  The present invention has been made in view of the above problems, and its main object is to reduce the overall shape of the device by reducing the planar shape of the interlayer connection portion for connecting the wiring layers to each other. Another object of the present invention is to provide a manufacturing method thereof, a wiring board, and a manufacturing method thereof.

  The circuit device of the present invention comprises a wiring board and a circuit element mounted on the wiring board, and the wiring board includes a metal core layer, an insulating layer covering the upper surface and the lower surface of the metal core layer, The first wiring layer and the second wiring layer formed on the upper surface and the lower surface of the insulating layer, and electrically connecting the first wiring layer or the second insulating layer and the metal core layer through the insulating layer The interlayer connection portion is formed in a region including a connecting portion to be connected and provided with a protruding portion in which the metal core layer is partially protruded in the thickness direction.

  The method of manufacturing a circuit device according to the present invention includes a step of providing a protruding portion partially protruding in the thickness direction on a main surface of a conductive foil serving as a metal core layer, and covering an upper surface and a lower surface of the metal core layer with an insulating layer. The first wiring layer and the second wiring layer are provided on the upper surface and the lower surface of the insulating layer, and the projecting portion is provided as an interlayer connection portion for conducting the first wiring layer or the second wiring layer and the metal core layer. A step of forming the first wiring layer and a step of electrically connecting a circuit element to the first wiring layer.

  The wiring board of the present invention includes a metal core layer, an insulating layer covering the upper and lower surfaces of the metal core layer, a first wiring layer and a second wiring layer formed on the upper and lower surfaces of the insulating layer, An interlayer connecting portion that penetrates the insulating layer and electrically connects the first wiring layer or the second insulating layer and the metal core layer, and the metal core layer partially protrudes in the thickness direction; The interlayer connection portion is formed in a region where the protruding portion is provided.

  The method for manufacturing a wiring board according to the present invention includes a step of providing a protruding portion partially protruding in the thickness direction on a main surface of a conductive foil serving as a metal core layer, and covering an upper surface and a lower surface of the metal core layer with an insulating layer. The first wiring layer and the second wiring layer are provided on the upper surface and the lower surface of the insulating layer, and the projecting portion is provided as an interlayer connection portion for conducting the first wiring layer or the second wiring layer and the metal core layer. And a step of forming in a region.

  According to the circuit device and the wiring board of the present invention, the metal core layer partially protrudes in the thickness direction to provide a protrusion, and this protrusion provides an interlayer connection that penetrates the insulating layer and makes each layer conductive. It is formed in the place. Accordingly, since the thickness of the interlayer connection portion is reduced, when the interlayer connection portion having the same aspect ratio is formed, the planar size can be reduced to about half that of the conventional example. Therefore, even when a large number of interlayer connection portions are formed on the wiring board, the total area occupied by the interlayer connection portions can be reduced, and the degree of freedom in designing the wiring layer can be ensured.

  In the manufacturing process, the metal core layer is partially thickened to provide a protruding portion, and the thin insulating layer covering the protruding portion is removed to provide an interlayer connection portion. Therefore, the metal core layer is removed to provide an interlayer connection portion. The thickness of the insulating layer to be reduced is reduced. Therefore, there is an advantage that the removal of the insulating layer using a laser becomes easy. Further, the interlayer connection part is formed by partially removing the insulating layer and providing a hole, and then providing a plating film in the hole. By making it thinner, the depth of the hole becomes shallower and the formation of the plating film becomes easier.

<First Embodiment>
In this embodiment, the configuration of the circuit device of this embodiment will be described with reference to FIGS.

  The configuration of the circuit device 10A will be described with reference to FIG. 1A is a cross-sectional view of the circuit device 10A, and FIG. 1B is a plan view showing a conductive pattern 11 built in the circuit device 10A.

  Referring to FIG. 1A, circuit device 10A is configured by mounting circuit elements such as semiconductor element 21 on the upper surface of wiring board 50 having a metal core layer. Further, the wiring substrate 50 includes a conductive pattern 11 functioning as a metal core layer, a first wiring layer 14 stacked on the upper surface of the conductive pattern 11 via the first insulating layer 12, and a second insulating layer 13. The second wiring layer 15 is mainly provided on the lower surface of the conductive pattern 11. A circuit element such as the semiconductor element 21 is mounted on the first wiring layer 14 of the wiring board 50. Furthermore, in this embodiment, the conductive pattern 11 is partially protruded in the thickness direction to provide the protruding portion 60, and the interlayer connection portion 19 and the like for conducting the layers are formed at the location where the protruding portion 60 is provided.

  The conductive pattern 11 functions as a metal core layer that bears the mechanical strength of the entire wiring board 50 and improves heat dissipation. Therefore, the conductive pattern 11 is formed thicker than the other wiring layers, and the thickness is, for example, about 100 μm to 200 μm. As the material of the conductive pattern 11, a metal mainly made of copper, a metal mainly made of aluminum, an alloy, or the like can be adopted. Further, when a rolled metal such as a rolled copper foil is employed as the material of the conductive pattern 11, the mechanical strength and heat dissipation of the conductive pattern 11 can be further improved. The rolled metal has an excellent thermal conductivity of several percent compared to the plated film.

  The conductive patterns 11 are separated from each other at a predetermined interval by a separation groove 16 including a first separation groove 17 and a second separation groove 18. The width of the separation groove 16 is, for example, about 100 μm to 150 μm. Here, the first separation groove 17 is provided by selectively half-etching the conductive foil as the material of the conductive pattern 11 from the upper surface, and the second separation groove 18 is formed by selectively etching the back surface of the conductive foil. Is provided. The first separation groove 17 is filled with the first insulating layer 12 covering the upper surface of the conductive pattern 11, and the second separation groove 18 is filled with the second insulating layer 13 covering the lower surface of the conductive pattern 11. The

  Here, the side surfaces of the first separation groove 17 and the second separation groove 18 are curved, and the adhesion strength with the insulating layer filled therein is improved. In addition, the first separation groove 17 and the second separation groove 18 formed by isotropically proceeding wet etching constitute the separation groove 16 so that the vicinity of the central portion of the separation groove 16 is constricted (conductivity). The side surface of the pattern 11 protrudes outward). Also by this, the adhesion strength between the first insulating layer 12 and the second insulating layer 13 and the conductive pattern 11 is improved.

  The first insulating layer 12 and the second insulating layer 13 cover the upper and lower surfaces of the conductive pattern 11. The first insulating layer 12 is filled in the first separation groove 17, and the second insulation layer 13 is filled in the second separation groove 18. The thickness with which the first insulating layer 12 and the second insulating layer 13 cover the conductive pattern 11 is, for example, about 50 μm to 100 μm. Furthermore, as a material for the first insulating layer 12 and the second insulating layer 13, a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyethylene resin can be employed.

  Furthermore, when a resin material filled with fibrous or particulate filler is adopted as the material of the first insulating layer 12 and the second insulating layer 13, the thermal resistance of these resin layers is reduced, and the heat dissipation of the wiring board 50 is achieved. Can be improved. Silicon oxide or silicon nitride can be used as the filler material. In addition, when these fillers are mixed into the first insulating layer 12 and the second insulating layer 13, the thermal expansion coefficient of the insulating layer approaches the conductive material such as the conductive pattern 11, and a temperature change occurs. Warpage of the wiring board 50 is suppressed.

  The first wiring layer 14 is a wiring layer formed on the upper surface of the first insulating layer 12, and is formed by selectively etching the rolled conductive film or the plating film attached to the first insulating layer 12. Since the thin conductive film or the like is patterned by etching, the first wiring layer 14 can be miniaturized, and the wiring width can be reduced to about 20 μm to 50 μm. Further, the first wiring layer 14 is electrically connected to the conductive pattern 11 via an interlayer connection portion 19 provided through the first insulating layer 12.

  In addition, circuit elements such as the chip element 22 and the semiconductor element 21 are electrically connected to the first wiring layer 14. The chip element 22 has electrodes at both ends fixed to the first wiring layer 14 via a conductive bonding material such as solder. The semiconductor element 21 such as an LSI or a transistor is fixed to the land-like first wiring layer 14 via a conductive or insulating bonding agent, and the electrode provided on the upper surface is connected to the first via a fine metal wire. Connected to one wiring layer 14.

  The second wiring layer 15 is a wiring layer formed on the lower surface of the second insulating layer 13, and the wiring width can be reduced to about 20 μm to 50 μm similarly to the first wiring layer 14 described above. In addition, the second wiring layer 15 is electrically connected to the lower surface of the conductive pattern 11 through an interlayer connection portion 20 provided through the second insulating layer 13. An external electrode made of a conductive adhesive such as solder may be welded to the second wiring layer 15.

  The interlayer connection portion 19 and the interlayer connection portion 20 are made of a conductive material such as a plating film formed in an exposed hole provided by removing the insulating layer, and have a function of connecting each wiring layer and the conductive pattern. Here, the first wiring layer 14 and the conductive pattern 11 are connected by an interlayer connection portion 19 provided through the first insulating layer 12. Further, the second wiring layer 15 and the conductive pattern 11 are connected by the interlayer connection portion 20 provided through the second insulating layer 13. Here, each interlayer connection portion may function as a path through which an electric signal passes, or may be a so-called dummy member through which an electric signal does not pass. Even if the interlayer connection portion 19 does not allow electric signals to pass therethrough, it can be used as a thermal via hole through which heat passes through the interlayer connection portion 19. Furthermore, in this embodiment, the interlayer connection parts 19 and 20 are connected to the protruding part 60 provided by protruding the conductive pattern 11 in the thickness direction. Details of this matter will be described later.

  Further, in the figure, a three-layer multilayer wiring composed of the first wiring layer 14, the conductive pattern 11, and the second wiring layer 15 is configured. By stacking a multilayer wiring layer further through an insulating layer, Four or more wiring layers may be constructed.

  The first wiring layer 14 and the second wiring layer 15 described above can be conducted through the interlayer connection portion 19 and the like. In this case, both wiring layers are electrically connected through a route of the first wiring layer 14 → the interlayer connection portion 19 → the conductive pattern 11 → the interlayer connection portion 20 → the second wiring layer 15.

  Here, the first wiring layer 14 and the second wiring layer 15 described above may be covered with a solder resist (resin film) except for a portion connected to the outside and a portion where a circuit element is mounted. Here, referring to FIG. 1A, the lowermost second wiring layer 15 is almost entirely covered with a solder resist 53, and the resist 53 is partially removed, so that the second wiring layer 15 is removed. Is partially exposed. Further, an external electrode 54 made of solder or the like is welded to the lower surface of the second wiring layer 15 exposed from the resist 53. Furthermore, the first wiring layer 14 and the second wiring layer 15 exposed from the resist may be covered with a gold plating film in order to improve the bondability.

  In this embodiment, a protruding portion 60 is provided in which the conductive pattern 11 is integrally protruded in the thickness direction, and the interlayer connection portions 19 and 20 are connected to the protruding portion 60. Specifically, a protrusion 60 that partially protrudes upward is formed on the upper surface of the conductive pattern 11 by an etching process or the like. The specific shape of the projecting portion 60 is, for example, a substantially cylindrical shape with a hem spread, and has a thickness of about 20 μm to 50 μm and a diameter of about 20 μm to 50 μm. Here, the shape of the protruding portion 60 is not necessarily a substantially cylindrical shape, and the planar shape may be a polygon such as a quadrangle.

  The interlayer connection portion 19 is provided above the protruding portion 60. That is, the first insulating layer 12 covering the upper surface of the interlayer connection portion 19 is removed to provide a hole, and a conductive material made of metal is formed inside the hole, so that the conductive pattern 11 and the first wiring layer are formed. 14 is formed. The thickness of the first insulating layer 12 covering the upper surface of the conductive pattern 11 is, for example, about 50 μm to 100 μm, but the thickness of the first insulating layer 12 in the region where the protruding portion 60 is embedded is, for example, about 20 μm to 50 μm. It consists of.

  As described above, by providing the interlayer connection portion 19 through the first insulating layer 12 in the region where the protrusion 60 is embedded, the thickness of the interlayer connection portion 19 can be reduced. Therefore, when the aspect ratio is the same as the conventional one, the width (diameter) of the interlayer connection portion 19 is reduced. For example, if the thickness of the protruding portion 60 is more than half of the thickness of the first insulating layer 12 covering the first conductive pattern 11, the thickness of the interlayer connection portion 19 is less than half that of the conventional example, and the width is less than half. Can be. As a result, when the circuit device 10A is viewed from above, the area occupied by the interlayer connection portion 19 is ¼ or less.

  From the above, the area of each interlayer connection portion 19 becomes extremely small. Therefore, even when a large number of interlayer connection portions 19 are provided, the area occupied by the interlayer connection portions 19 is reduced, and the first wiring layer 14 is designed. The degree of freedom increases. In particular, the uppermost first wiring layer 14 is connected to a semiconductor element 21 such as an LSI having a large number of electrodes. Furthermore, in order to configure a multifunctional SIP, a large number of circuit elements may be connected to the first wiring layer 14. For this reason, a large number of complicated first wiring layers 14 may be required. However, in the circuit device 10A according to the present embodiment, the area of the interlayer connection portion 19 is reduced by the above configuration, and the pattern design time is reduced. The requirement is satisfied by reducing the constraints.

  Furthermore, as described above, the conductive pattern 11 is made of a rolled metal that is rolled, and has a thermal conductivity superior to that of the plated film. On the other hand, the interlayer connection portion 19 is generally made of a plating film embedded in a hole provided by partially removing the first wiring layer 14. From this, by providing the protrusion part 60, the thickness of the interlayer connection part 19 made of plating whose thermal conductivity is slightly inferior is reduced, and the heat dissipation through the interlayer connection part 19 can be improved by this amount. This effect is remarkable when the interlayer connection portion 19 is disposed below the semiconductor element 21 and used as the thermal via hole 46.

  Furthermore, the protrusion 60 having the above-described configuration is also provided on the lower surface of the conductive pattern 11. Here, a protruding portion 60 that protrudes downward from the lower surface of the conductive pattern 11 is provided, and the interlayer connection portion 20 is provided below the protruding portion 60. The conductive pattern 11 and the second wiring layer 15 are electrically and thermally connected via the interlayer connection portion 20. The relationship between the interlayer connection 20 and the protrusion 60 is the same as the relationship between the interlayer connection 19 and the protrusion 60 described above.

  Here, the protrusions 60 may be provided only on the upper surface of the conductive pattern 11 that is the metal core layer, may be provided only on the lower surface, or may be provided on both main surfaces.

  Furthermore, the conductive pattern 11 is thermally coupled to each wiring layer via the interlayer connection portion 19 and the interlayer connection portion 20 whose upper and lower surfaces function as thermal vias, and is used as a pattern for improving heat dissipation. Also good. Here, a plurality of thermal via holes 46 are provided below the semiconductor element 21, and the semiconductor element 21 is thermally coupled to the conductive pattern 11 directly below via the thermal via hole 46. Thus, even if a power transistor having a large calorific value is adopted as the semiconductor element 21, a large amount of generated heat is favorably released to the outside through the thermal via hole 46 and the conductive pattern 11.

  FIG. 1B shows an example of a planar shape of the conductive pattern 11 embedded in the wiring board 50. Here, a large number of conductive patterns 11 are separated by substantially uniform separation grooves 16. In other words, the conductive patterns 11 are electrically separated (insulated) by the first insulating layer 12 and the second insulating layer 13 filled in the separation groove 16. Therefore, by connecting each conductive pattern 11 to the first wiring layer 14 or the second wiring layer 15 via the interlayer connection portions 19 and 20, the potential of each conductive pattern 11 can be made different. For example, these conductive patterns 11 may be used as a signal pattern through which an electric signal input / output to / from the first wiring layer 14 and the second wiring layer 15 passes, or a fixed potential (for example, a power source) at a predetermined location. (Potential or ground potential) may be used as a pattern for extracting.

  Still further, referring to FIG. 1B, the outer peripheral end of the conductive pattern 11 that is the metal core layer is located inside the insulating layer 51 (the first insulating layer 12 and the second insulating layer 13). ing. That is, as shown in FIG. 1A, the side surface of the outermost peripheral portion of the conductive pattern 11 is covered with the insulating layer 51 including the first insulating layer 12 and the second insulating layer 13 and is not exposed to the outside. . As a result, a structure in which all the conductive patterns 11 are enclosed by the insulating layer 51 and are not exposed to the outside is realized, and the conductive patterns 11 can be insulated from the outside.

  Further, in the wiring board 50 described above, it is preferable that the remaining ratio of each layer (the ratio of the pattern or the area of the wiring layer to the area of the entire board) is substantially constant. For example, the remaining ratio of the first wiring layer 14, the conductive pattern 11, and the second wiring layer 15 is preferably about 80% ± 10%. Thus, by making the remaining rate of each layer substantially constant, it is possible to prevent the wiring substrate 50 from warping in a process involving heating, such as a wire bonding process. In addition, when the metal core layer is a solid one that is not patterned as shown in FIG. 2, the remaining rates of the first wiring layer 14 and the second wiring layer 15 may be made substantially equal in the above-described range.

  Furthermore, considering the heat dissipation of the entire substrate, the first wiring layer 14 made of a metal material has better thermal conductivity than the first insulating layer 12 made of a resin material, so the first wiring layer 14 etc. The higher the remaining rate of each layer, the better. For example, the remaining ratio of the first wiring layer 14, the conductive pattern 11, and the second wiring layer 15 is preferably 50% or more, more preferably 70% or more, and particularly preferably 80% or more. Thus, by increasing the residual ratio of each layer such as the first wiring layer 14, the steady thermal resistance is reduced, and the heat generated from the circuit elements such as the semiconductor element 21 can be satisfactorily externalized via the wiring substrate 50. Can be released. Here, when the metal core layer is a solid one that is not patterned as shown in FIG. 2, the residual ratio of the first wiring layer 14 and the second wiring layer 15 may be increased within the above-described range.

  Next, with reference to FIG. 2, the configuration of another form of circuit device 10B will be described. 2A is a cross-sectional view of the circuit device 10B, and FIG. 2B is a plan view showing the conductive foil 25 incorporated therein. The basic configuration of the circuit device 10B is the same as that of the circuit device 10A described above, and the difference is that an unpatterned plate-like conductive foil 25 is employed as the metal core layer.

  Referring to FIG. 2A, the circuit device 10B includes a solid conductive foil 25 that is not patterned as a metal core layer. The thickness and material of the conductive foil 25 may be the same as those of the conductive pattern 11 described above. The conductive foil 25 may pass an electric signal input / output to / from a circuit element mounted on the first wiring layer 14, and a fixed potential (a ground potential or a power supply potential) may pass through the interlayer connection portion at a predetermined location. Or may be used only for heat dissipation by being electrically floating. By adopting such a conductive foil 25 as the metal core layer, the mechanical strength of the entire wiring board 50 is improved by the conductive foil 25. Furthermore, since a predetermined potential (ground potential or power supply potential) can be taken out from the conductive foil 25 via the interlayer connection portion 19 and the interlayer connection portion 20 at an arbitrary place, the first wiring layer 14 and the second wiring layer 14 The degree of freedom in designing the wiring layer 15 can be improved.

  Furthermore, the upper and lower surfaces of the conductive foil 25 are formed with protruding portions 60 that partially protrude in the thickness direction. On the upper surface of the conductive foil 25, an interlayer connection portion 19 for connecting the first wiring layer 14 and the conductive foil 25 is formed above the protruding portion 60 protruding in the thickness direction. On the lower surface of the conductive foil 25, an interlayer connection portion 20 that electrically connects the second wiring layer 15 and the conductive foil 25 is formed below the protruding portion 60.

  A connection hole 42 is provided through the conductive foil 25 partially in the thickness direction. The connection hole 42 includes a first connection hole 27 provided from the upper surface of the conductive foil 25 and a second connection hole 28 provided from the lower surface of the conductive foil 25. The first connection hole 27 is filled with the first insulating layer 12, and the second connection hole 28 is filled with the second insulating layer 13. The diameter of the connection hole 42 having a circular shape in plan is, for example, about 100 μm to 200 μm.

  Referring to FIGS. 2A and 2B, the through-connection portion 23 is provided through the resin material filled in the connection hole 42, and the upper first wiring layer 14 and the lower layer are connected to each other. The second wiring layer 15 is electrically connected. Specifically, the through-connecting portion 23 is provided with a through-hole so that the first insulating layer 12 and the second insulating layer 13 that are located inside the through-hole 24 in plan view are penetrated, and copper or the like is provided in the through-hole. It is formed by embedding a conductive material. The diameter of the through connection portion 23 is, for example, about 50 μm to 100 μm. By providing the through connection portion 23, the first wiring layer 14 and the second wiring layer 15 can be electrically connected without passing through the conductive foil 25.

  Referring to FIG. 2B, the outer peripheral end of conductive foil 25 that is a metal core layer is located inside the outer peripheral end of wiring substrate 50. That is, since the side surface of the conductive foil 25 is covered with the insulating layer 51, the conductive foil 25 is insulated from the outside, and a sufficient withstand voltage is secured.

  Next, the configuration of another form of circuit device 10C will be described with reference to FIG. 3A is a cross-sectional view of the circuit device 10C, and FIG. 3B is a plan view thereof. The basic configuration of the circuit device 10C is the same as that of the circuit device 10A described above, and the difference is the configuration of the conductive pattern 11B and the wirings 47A and 47B. Also here, the protrusions 60 are formed in the conductive pattern 11B and the wirings 47A and 47B.

  With reference to FIG. 3B, the wiring 47 </ b> A extends longer than the other conductive pattern 11 and is connected to another wiring layer via the interlayer connection portion 20. Here, the wiring 47A is connected to the first wiring layer 14 shown in FIG. On the other hand, the wiring 47B is connected to the second wiring layer 15 via the two interlayer connection portions 20. Here, one of the wirings 47 </ b> A and 47 </ b> B may be connected to the first wiring layer 14 via the interlayer connection portion 19, and the other may be connected to the second wiring layer 15 via the interlayer connection portion 20. By providing the wiring 47A and the like, the conductive pattern 11 functioning as a metal core layer can have a function of routing the wiring, and a more multifunctional electric circuit can be built in the circuit device 10C.

  Two wires 47A and 47B are formed close to each other on the right side of the drawing. The wiring 47A located in the upper part is separated by the first separation grooves 17C and 17D, and the first separation groove 17D is formed wider than the first separation groove 17C. Specifically, for example, the width of the first separation groove 17C is about 150 μm, whereas the width of the first separation groove 17D is about 150 μm to 500 μm. Further, the lower wiring 47B is separated by the second separation grooves 18D and 18E, and the second separation groove 18D is formed wider than the second separation groove 18E. Here, for example, the width of the second separation groove 18D is 150 μm to 500 μm, whereas the second separation groove 18E is about 150 μm.

  Here, the wiring 47A and the wiring 47B can be brought very close to each other by arranging the upper first separation groove 17D and the lower second separation groove 18D so as to overlap in a plane. For example, the distance D1 between the wiring 47A and the wiring 47B can be shortened to about 20 μm. This greatly contributes to pattern miniaturization.

  Further, a protrusion 60 protruding in the thickness direction is provided on the upper surface of the wiring 47 </ b> A, and the interlayer connection 19 is formed above the protrusion 60. As described above, by providing the protruding portion 60, the width of the interlayer connection portion 19 can be reduced to half or less. Therefore, with this configuration, even if a thin wiring having a width of about 100 μm is provided, the wiring 47 A and the first wiring layer 14 can be connected via the interlayer connection portion 19. Further, in the wiring 47 </ b> B, a protruding portion 60 is formed on the lower surface, and the interlayer connection portion 20 is formed below the protruding portion 60.

  Here, regarding the wiring 47 </ b> A, a projecting portion 60 may be provided on the lower surface, and the interlayer connection portion 20 penetrating the second insulating layer 13 may be provided below the projecting portion 60. Further, with respect to the wiring 47B, a protruding portion 60 may be provided on the upper surface, and the interlayer connecting portion 19 penetrating the first insulating layer 12 may be provided above the protruding portion 60.

  Further, referring to FIG. 3A, a built-in element 26 is fixed to the upper surface of the conductive pattern 11B formed on the left side on the paper surface. Here, a chip capacitor, a chip resistor, or the like is employed as the built-in element 26. The upper surface of the conductive pattern 11B is formed such that the position of the upper surface is lower than the other conductive patterns 11 in accordance with the depth of the first separation groove 17B. Therefore, an increase in the thickness of the wiring board 50 due to the mounting of the built-in element 26 is suppressed. Here, a wide first separation groove 17B that separates the conductive patterns 11 from each other is provided, and two second separation grooves 18B and 18C are provided below the first separation groove 17B, whereby a thin conductive pattern 11B is formed. Is forming.

  Next, the configuration of another form of circuit device 10D will be described with reference to the cross-sectional view of FIG. The configuration of the circuit device 10D is different from other circuit devices described above in that the sealing resin 49 is provided. Here, the sealing resin 49 is formed so that the upper surfaces of the chip element 22, the semiconductor element 21, and the wiring substrate 50 are covered. The sealing resin 49 is formed by an injection mold using a thermoplastic resin or a transfer mold using a thermosetting resin. The configuration of the sealing resin 49 is applicable to all the circuit devices described above.

<Second Embodiment>
In this embodiment, a method for manufacturing the circuit device 10A having the configuration shown in FIG. 1 will be described with reference to the cross-sectional views of FIGS.

  Referring to FIG. 5A, first, protrusions 60 are formed on the upper and lower surfaces of conductive foil 30 by selective wet etching. As a specific method, first, the conductive foil 30 is prepared, and the region where the protrusion 60 is to be formed is covered with an etching mask (not shown), and then wet etching is performed using an etchant. The conductive foil 30 is made of a metal or alloy whose main material is copper or aluminum, and has a thickness of about 100 μm to 200 μm, for example. In addition, when a rolled metal subjected to a rolling process is used as the material of the conductive foil 30, the rolled metal is excellent in mechanical strength, so that cracks and deformation of the substrate occur in the middle of the manufacturing process. Can be suppressed. By this step, the main surface of the portion of the conductive foil 30 that is not covered with the etching mask is etched, and as a result, the protruding portion 60 protruding in the thickness direction is obtained. The protrusion 60 has a substantially cylindrical shape whose side surface is curved and spreads around, and has a thickness of about 20 μm to 50 μm and a diameter of about 20 μm to 50 μm.

  Here, the protrusion 60 may be formed by an additive method (CU plating). By using the additive method, it is possible to provide the protrusion 60 that is finer than in the wet etching method.

  Referring to FIG. 5B, next, the first separation groove 17 is formed by partially etching the upper surface of the conductive foil 30. Here, after covering the upper surface of the conductive foil 30 excluding the region where the first separation groove 17 is to be formed with a resist (not shown), the conductive foil 30 is etched from the upper surface using this resist as an etching mask. is doing. The protrusion 60 formed in the previous step is also covered with an etching mask during etching.

  The depth of the first separation groove 17 formed in this step is preferably about half or more of the thickness of the conductive foil 30. Accordingly, the separation groove 16 can be constituted by the first separation groove 17 and the second separation groove 18 formed by isotropically proceeding wet etching, and the width of the separation groove 16 is narrowed to about half of the thickness of the separation groove. (See FIG. 5C). As a result, the area of the conductive pattern occupying the entire wiring board increases, and the mechanical strength and heat dissipation characteristics of the wiring board are improved.

  For example, if the thickness of the conductive foil 30 is in the range of 100 μm to 200 μm, the depth of the first separation groove 17 may be about 50 μm to 100 μm. Further, considering that the wet etching in this step proceeds isotropic, the width of the first separation groove 17 is 50 μm to 100 μm depending on the thickness of the conductive foil 30.

  Referring to FIG. 5C, next, the upper surface of the conductive foil 30 is covered with the first insulating layer 12 so that the first separation groove 17 is filled, and the first insulating layer 12 is covered with the first insulating layer 12. A conductive film 31 is attached. As a manufacturing method of the first insulating layer 12, a semi-solid or liquid resin material may be applied to the upper surface of the conductive foil 30 and then heat-cured, or a film-shaped resin material may be vacuumed on the upper surface of the conductive foil 30. You may make it contact | adhere with a press. In this step, since the first separation groove 17 does not penetrate the conductive foil 30 and terminates in the middle of the thickness direction, even if the liquid or semi-solid first insulating layer 12 is applied to the conductive foil 30, Problems such as leakage of the resin material from the first separation groove 17 do not occur. Furthermore, since the side surface of the first separation groove 17 is a curved surface formed by wet etching, the first insulating layer 12 is fitted to the side surface of the first separation groove 17 and the adhesion strength between them is high.

  Furthermore, in this step, the protrusion 60 is embedded in the first insulating layer 12. For example, when the thickness of the first insulating layer 12 covering the upper surface of the conductive foil 30 is about 50 μm to 100 μm, the protrusion 60 is embedded. In the region, the thickness of the first insulating layer 12 is about 20 μm to 50 μm.

  Furthermore, the upper surface of the first insulating layer 12 is entirely covered with the first conductive film 31. Here, the first insulating layer 12 to which the first conductive film 31 is adhered may be laminated on the conductive foil 30, or after the first insulating layer 12 is in close contact with the conductive foil 30, 31 may be attached to the first insulating layer 12. Moreover, the 1st electrically conductive film 31 may be comprised from a rolled metal, and may be formed by the plating method. The thickness of the first conductive film 31 is, for example, about 20 μm to 50 μm.

  As the resin material constituting the first insulating layer 12, both a thermosetting resin or a thermoplastic resin can be employed. Further, a resin material mixed with a fibrous or particulate filler may be adopted as the first insulating layer 12.

  Referring to FIG. 5D, next, the second separation groove 18 is formed by selectively etching from the back surface of the conductive foil 30, and the conductive foil 30 is separated to obtain the respective conductive patterns 11. Specifically, first, a resist (not shown) is formed so that the back surface of the conductive foil 30 in a region corresponding to the first separation groove 17 is exposed. Here, the protrusion 60 formed on the back surface of the conductive foil 30 is also covered with a resist (not shown). Next, the second separation groove 18 is formed by wet-etching the back surface of the portion of the conductive foil 30 exposed from the resist (not shown). Here, the second separation groove 18 is formed by wet etching until the first insulating layer 12 filled in the first separation groove 17 is exposed. In other words, the second separation groove 18 is formed until it reaches the first separation groove 17, and the first insulating layer 12 filled in the first separation groove 17 is exposed from the second separation groove 18.

  The depth of the second separation groove 18 needs to be at least greater than the depth at which the first insulating layer 12 filled in the first separation groove 17 is exposed. Therefore, for example, when the thickness of the conductive foil 30 is 100 μm to 200 μm and the depth of the first separation groove 17 is 50 μm to 100 μm, the depth of the second separation groove 18 is about 50 μm to 100 μm or more. That is, the distance obtained by adding the depth of the first separation groove 17 and the depth of the second separation groove 18 needs to be equal to or greater than the thickness of the conductive foil 30. In order to reliably expose the first insulating layer 12 filled in the first separation groove 17 from the second separation groove 18, a distance obtained by adding the depth of the first separation groove 17 and the depth of the second separation groove 18. Is preferably longer by about several tens of μm than the thickness of the conductive foil 30.

  Through the above steps, a conductive pattern having a shape as shown in FIG.

  Next, referring to FIG. 5E, the back surface of the conductive pattern 11 is covered with the second insulating layer 13, and the second conductive film 32 is attached to the surface of the second insulating layer 13. Here, the second insulating layer 13 is formed so that the lower surface of the conductive pattern 11 is covered and the second separation groove 18 is filled. The thickness, composition, and formation method of the second insulating layer 13 may be the same as those of the first insulating layer 12 described above. Furthermore, the thickness, material, and formation method of the second conductive film 32 formed on the lower surface of the second insulating layer 13 may be the same as those of the first conductive film 31 described above. In this step, the protruding portion 60 located on the lower surface of the conductive pattern 11 is embedded in the second insulating layer 13, and the thickness of the second insulating layer 13 is partially reduced in the region where the protruding portion 60 is provided. Yes.

  Referring to FIG. 6A, next, the first conductive film 31 and the second conductive film 32 in a region to be connected to the conductive pattern 11 are partially removed. Specifically, a resist (not shown) that functions as an etching mask is applied to the entire upper surface of the first conductive film 31, and then exposure and development processes are performed. As a result, the first conductive film 31 in the region overlapping the protrusion 60 is exposed from the resist. Further, wet etching is performed to remove the first conductive film 31 exposed from the resist. Through the above process, the first conductive film 31 located above the protrusion 60 is removed.

  Next, laser processing using the first conductive film 31 as a mask is performed, the first insulating layer 12 exposed from the exposed portion of the first conductive film 31 is removed, and the exposed hole 33 is formed. Here, the first insulating layer 12 exposed from the first conductive film 31 is laser-etched so that the upper surface of the protrusion 60 is exposed from the bottom of the exposure hole 33. If a residue such as an evaporated resin material remains on the bottom of the exposure hole 33 or the like by laser irradiation in this step, desmear treatment is performed to remove the residue. Side surfaces such as the exposure holes 33 formed in this step are inclined surfaces whose opening area increases toward the outside. Therefore, in the next process of performing the plating process, the flow of the plating solution in the exposed hole 33 is promoted, and there is an advantage that the plated film can easily adhere to the inner wall of the exposed hole 33.

  In this step, by embedding the protrusion 60, the upper surface of the protrusion 60 is exposed to the bottom surface of the exposure hole 33, for example, through the first insulating layer 12 whose thickness is reduced to about half. Accordingly, the exposure hole 33 can be easily formed by the thickness of the insulating layer to be removed. Furthermore, assuming that the aspect ratio of the hole formed by laser irradiation is the same, the depth and diameter of the exposed hole 33 can be reduced to about half (about 20 μm to 50 μm) by providing the protrusion 60. it can. Therefore, the size of the interlayer connection portion formed inside the exposure hole 33 is also reduced.

  A similar process is performed on the second conductive film 32 to partially remove the second conductive film 32 to form an exposed hole 34 and expose the lower surface of the exposed portion 60 on the upper surface of the exposed hole 34.

  Referring to FIG. 6B, next, an interlayer connection portion 19 is formed inside the exposure hole 33 to make the wiring layer and the conductive pattern conductive. The interlayer connection portion 19 may be composed of a metal film formed inside the exposure hole 33 by a plating method, or may be made of a conductive material such as solder or conductive resin paste embedded in the exposure hole 33. May be configured. When the interlayer connection portion 19 is formed by plating, first, a thin metal film (seed layer) by electroless plating is provided on at least the inner wall of the exposure hole 33, and then a voltage is applied to the seed layer to perform electrolysis. A plating film made of copper having a thickness of about several μm to several tens of μm is formed by plating. By the same method, the interlayer connection portion 20 is provided inside the exposed hole 34 that penetrates the second insulating layer 13. When filling plating is performed, a plating film can be generated so that the exposed holes 33 and the exposed holes 34 are embedded.

  Here, it is preferable that the thickness of the first insulating layer 12 covering the protruding portion 60 is equal to or less than the thickness of the plating provided in the above process. As a result, the depth of the exposed hole 33 is reduced, and the exposed hole 33 is almost completely embedded by the plating film accumulated by the above-described process, so that the interlayer connection portions 19 and 20 having excellent mechanical strength are formed.

  Referring to FIG. 6C, after the interlayer connection portions 19 and 20 are formed, the first conductive film 31 and the second conductive film 32 are selectively etched to form the first wiring layer 14 and the second wiring. Layer 15 is patterned. Since the thickness of the first conductive film 31 and the second conductive film 32 is as thin as about 10 μm, for example, the wiring width of the formed wiring layer can be as fine as about 20 μm to 50 μm.

  Here, the first wiring layer 14 is stacked above the conductive pattern 11 and the second wiring layer 15 is stacked below the conductive pattern 11 to realize a three-layer multilayer wiring. Four or more wiring layers may be realized by stacking layers. By increasing the number of wiring layers to be stacked, a larger-scale electric circuit can be incorporated into the wiring board.

  After the above steps are completed, the first wiring layer 14 and the second wiring layer 15 may be covered with a solder resist made of a resin film, except for a place where circuit elements are mounted or connected to the outside. .

  Next, referring to FIG. 6D, a circuit element is mounted on the first wiring layer 14 and electrically connected thereto. Here, the chip element 22 is connected to the first wiring layer 14 via a bonding material such as solder. Further, the back surface of the semiconductor element 21 such as LSI is mounted on the land-like first wiring layer 14 via a bonding material, and the electrode on the front surface is connected to the first wiring layer 14 via a fine metal wire.

  Further, after the resist 53 is formed so as to cover the second wiring layer 15, the resist 53 is removed so that the second wiring layer 15 is partially exposed, and the exposed second wiring layer 15 is formed. An external electrode 54 made of solder is welded. Further, the wiring board 50 of each unit is separated at a location where a one-dot chain line is shown. Further, after the sealing resin is formed on the upper surface of the wiring substrate 50 so as to cover the semiconductor element 21 and the like, the separation step may be performed. In this step, each wiring layer exposed from the resist 53 may be covered with a gold plating film.

  In this step, since the wiring substrate 50 is separated at the location where the separation groove 16 is formed (that is, in the region where the conductive pattern 11 and the first wiring layer 14 do not exist), a cutting means such as a dicing saw is used. Abrasion can be suppressed and separation can be performed. Moreover, since the conductive material such as copper is not separated, the generation of burrs associated with the separation is suppressed.

  Through the above process, for example, the circuit device 10A having the configuration shown in FIG. 1 is manufactured.

  Here, in the manufacturing method described above, the wiring layer is formed by etching the film-like conductive film (the first conductive film 31 and the second conductive film 32), but a plating film may be used instead of the conductive film. it can. According to the manufacturing method in which the wiring layer is provided by this plating film, the wiring layer is formed by etching a thin metal film having a thickness of about 5 μm to 10 μm, and therefore, a fine wiring layer having a width of about 40 μm or less can be formed. it can.

<Third Embodiment>
Next, a method for manufacturing the circuit device 10B having the configuration shown in FIG. 2 will be described with reference to the cross-sectional views of FIGS. The method for manufacturing the circuit device 10B is basically the same as the method for manufacturing the circuit device 10A described above. The difference between the two is that a through-connecting portion 23 that penetrates each insulating layer is formed, and that a metal core is constituted by a solid conductive foil 25 that is not patterned. A method for manufacturing the circuit device 10B will be described focusing on this difference.

  Referring to FIG. 7A, first, conductive foil 25 is partially etched from the upper surface to provide first connection hole 40. As the material of the conductive foil 25, a metal having a thickness of about 100 μm to 200 μm is adopted. Specifically, a metal mainly made of copper, a metal mainly made of aluminum, an alloy, a rolled metal, or the like is adopted. . Furthermore, protrusions 60 are provided in advance on the upper and lower surfaces of the conductive foil 25 by wet etching.

  The first connection hole 40 is formed by wet-etching the conductive foil 25 exposed from the etching mask after selectively covering the upper surface of the conductive foil 25 with an etching mask (not shown). Here, the 1st connection hole 40 is formed corresponding to the location in which the penetration connection part which penetrates the conductive foil 25 and connects wiring layers is provided. The depth of the first connection hole 40 is, for example, about half the thickness of the conductive foil 25 and is about 50 μm to 100 μm. Further, the width (diameter) of the first connection hole 40 formed by wet etching that proceeds isotropically is about 50 μm to 100 μm, similarly to the depth.

  Referring to FIG. 7B, next, the upper surface of the conductive foil 25 is covered with the first insulating layer 12 so as to fill the first connection hole 40, and the first upper surface of the first insulating layer 12 is covered with the first insulating layer 12. A conductive film 31 is attached. Further, the conductive foil 25 is removed from the back surface so that the first insulating layer 12 filled in the first connection hole 40 is exposed. Here, the connection hole 42 is constituted by the first connection hole 40 and the second connection hole 41 which are continuous in the thickness direction. The basic process of this step is the same as that of the second embodiment described above.

  Here, the second connection hole 41 is formed by selectively wet-etching the conductive foil 25 in the region below the first connection hole 40. The first insulating layer 12 filled in the first connection hole 40 is exposed from the second connection hole 41. Also here, in order to expose the first insulating layer 12 filled in the first connection hole 40 to the outside, the length obtained by adding the depth of the first connection hole 40 and the depth of the second connection hole 41 is the conductive length. It needs to be longer than the thickness of the foil 25. Here, the conductive foil 25 is completely removed from the back surface by so-called maskless etching that does not use an etching mask without performing selective etching for forming the second connection hole 41, and the first connection is made. The first insulating layer 12 filled in the holes 40 may be exposed on the back surface of the conductive foil 25.

  Referring to FIG. 7C, next, the back surface of the conductive foil 25 is covered with the second insulating layer 13 so that the second connection hole 41 is filled, and the lower surface of the second insulating layer 13 is further covered. The second conductive film 32 is attached to the substrate. The details of this process are also the same as in the second embodiment described above.

  Referring to FIG. 7D, next, the first conductive film 31 and the second conductive film 32 are partially etched to provide an exposed portion 43 and an exposed portion 44. The exposed portion 43 is provided corresponding to a location where an interlayer connection portion that connects the first conductive film 31 or the second conductive film 32 and the conductive pattern 11 is formed. That is, the exposed portion 43 is provided so as to overlap with the portion where the protruding portion 60 is provided. Further, the exposed portion 44 is provided by removing the first conductive film 31 located above the connection hole 42. Further, the exposed portion 44 is also provided below the connection hole 42 by removing the second conductive film 32. By providing the exposed portion 43 and the exposed portion 44, laser etching is performed using the first conductive film 31 and the second conductive film 32 as a mask, and the first insulating layer 12 and the second insulating layer 13 are partially removed. Can do.

  Referring to FIG. 8A, next, the first insulating layer 12 exposed from the first conductive film 31 is removed by irradiating a laser to form an exposed hole 33 and a through hole 24. The upper surface of the protrusion 60 is exposed from the bottom of the exposure hole 33. Further, the second insulating layer 13 exposed from the second conductive film 32 is removed with a laser to form an exposed hole 34, and the lower surface of the protruding portion 60 is exposed from the bottom of the exposed hole 34. In addition, with respect to the through hole 24, the first insulating layer 12 and the second insulating layer 13 filled in the connection hole 42 can be removed by irradiating laser from one main surface to reach the other main surface. good. Furthermore, the through-hole 24 may be formed partway with a laser irradiated from one main surface, and the remaining through-hole 24 may be formed with a laser irradiated from the other main surface.

  In this step, a through hole 24 penetrating the first insulating layer 12 and the second insulating layer 13 filled in the connection hole 42 is provided. The diameter of the through hole 24 is smaller than that of the connection hole 42 and is, for example, about 50 μm to 100 μm. Further, the through hole 24 is provided apart from the side wall of the connection hole 42 in order to insulate the connection portion formed later in the through hole 24 from the conductive pattern 11.

  Furthermore, in this embodiment, since the exposed hole 33 is provided in the portion of the first insulating layer 12 that is thinned by embedding the protruding portion 60, there is an advantage that the first insulating layer 12 can be easily removed by laser irradiation. The same applies to the exposed hole 34 provided by removing the second insulating layer 13.

  Referring to FIG. 8B, next, a metal film is formed by an electroless plating method and an electrolytic plating method, and interlayer connection portions 19 and 20 and through connection portion 23 are formed. An interlayer connection portion 19 made of a plating film is formed in the exposed hole 33 penetrating the first insulating layer 12 to connect the first conductive film 31 and the conductive pattern 11. Further, an interlayer connection portion 20 made of a plating film is provided inside the exposed hole 34 that penetrates the second insulating layer 13 to connect the second conductive film 32 and the conductive pattern 11. Further, the through-connection portion 23 is formed by the metal film generated inside the through-hole 24. The first conductive film 31 and the second conductive film 32 stacked with the conductive pattern 11 interposed therebetween are electrically connected without passing through the conductive foil 25 by the through connection portion 23.

  Also in this step, by providing the projecting portion 60, there are advantages such that the depth of the exposed holes 33 and 34 becomes shallow and the formation of the interlayer connection portions 19 and 20 made of plating becomes easy.

  Referring to FIG. 8C, next, the first conductive layer 31 and the second conductive layer 32 are selectively etched, and the first wiring layer 14 and the second wiring layer 15 are patterned. Here, the first wiring layer 14 and the second wiring layer 15 are electrically connected via the through connection portion 23.

  Next, referring to FIG. 8D, circuit elements are mounted on the first wiring layer 14. Here, the chip element 22 and the semiconductor element 21 are connected to the first wiring layer 14.

  Through the above steps, the circuit device 10B having the structure shown in FIG. 2 is manufactured.

It is a figure which shows the circuit apparatus of this invention, (A) is sectional drawing, (B) is a top view. It is a figure which shows the circuit apparatus of this invention, (A) is sectional drawing, (B) is a top view. It is a figure which shows the circuit apparatus of this invention, (A) is sectional drawing, (B) is a top view. It is sectional drawing which shows the circuit apparatus of this invention. It is a figure which shows the manufacturing method of the circuit apparatus of this invention, (A)-(E) is sectional drawing. It is a figure which shows the manufacturing method of the circuit apparatus of this invention, (A)-(D) is sectional drawing. It is a figure which shows the manufacturing method of the circuit apparatus of this invention, (A)-(D) is sectional drawing. It is a figure which shows the manufacturing method of the circuit apparatus of this invention, (A)-(D) is sectional drawing. It is sectional drawing which shows the structure and manufacturing method of the multilayer substrate of background art.

Explanation of symbols

10A, 10B, 10C, 10D CIRCUIT DEVICE 11, 11B Conductive pattern 12 First insulating layer 13 Second insulating layer 14 First wiring layer 15 Second wiring layer 16, 16A Separation groove 17, 17B, 17C, 17D First separation groove 18, 18B, 18C, 18D, 18E Second separation groove 19, 19A, 20 Interlayer connection part 21 Semiconductor element 22 Chip element 23 Through connection part 24 Through hole 25 Conductive foil 26 Built-in element 27 First connection hole 28 Second connection hole 30 conductive foil 31 first conductive film 32 second conductive film 33, 34 exposed hole 40 first connection hole 41 second connection hole 42 connection hole 43, 44 exposed part 46 thermal via hole 47A, 47B, 47C wiring 49 sealing resin 50 Wiring board 51 Insulating layer 53 Resist 54 External electrode 60 Projection

Claims (12)

Comprising a wiring board and a circuit element mounted on the wiring board;
The wiring board includes a metal core layer, an insulating layer covering the top and bottom surfaces of the metal core layer, a first wiring layer and a second wiring layer formed on the top and bottom surfaces of the insulating layer, and the insulating layer. And an interlayer connection portion that electrically connects the first wiring layer or the second insulating layer and the metal core layer,
The circuit device is characterized in that the interlayer connection portion is formed in a region provided with a protruding portion in which the metal core layer is partially protruded in the thickness direction.   2. The circuit device according to claim 1, wherein the interlayer connection portion is made of a plating film formed in an exposed hole provided by partially removing the insulating layer covering the protruding portion.   The circuit device according to claim 2, wherein a thickness of the insulating layer covering the protruding portion is set to be equal to or smaller than a thickness of the plating film. A first interlayer connecting portion that connects the first wiring layer and the metal core layer through the insulating layer; and a second interlayer connection portion that connects the second wiring layer and the metal core layer through the insulating layer. Having two interlayer connections,
The circuit device according to claim 1, wherein the first interlayer connection portion and the second interlayer connection portion are provided in regions where the protruding portions are provided on both main surfaces of the metal core layer.   The circuit device according to claim 1, wherein an outer peripheral end portion of the metal core layer is located on an inner side separated from an outer peripheral end portion made of the insulating layer.   The circuit device according to claim 1, wherein the metal core layer is a plurality of conductive patterns separated by a separation groove or a single continuous conductive foil. A step of partially providing a protrusion protruding in the thickness direction on the main surface of the conductive foil serving as the metal core layer;
An upper surface and a lower surface of the metal core layer are covered with an insulating layer, a first wiring layer and a second wiring layer are provided on the upper surface and the lower surface of the insulating layer, and the first wiring layer or the second wiring layer and the metal core layer are provided. Forming an interlayer connection in a region where the protrusion is provided; and
And a step of electrically connecting a circuit element to the first wiring layer.   The method of manufacturing a circuit device according to claim 7, wherein the protruding portions are provided on both main surfaces of the conductive foil.   The interlayer connection portion is formed by removing the insulating layer covering the protruding portion to form an exposed hole, exposing the protruding portion to the exposed hole, and then providing a plating film on the exposed hole. The method of manufacturing a circuit device according to claim 7.   The method for manufacturing a circuit device according to claim 9, wherein the insulating layer covering the protruding portion is made thinner than the plating film, and the plating film is embedded in the exposed hole. A metal core layer; an insulating layer covering the upper and lower surfaces of the metal core layer; a first wiring layer and a second wiring layer formed on the upper and lower surfaces of the insulating layer; An interlayer connection portion for electrically connecting the first wiring layer or the second insulating layer and the metal core layer;
The wiring board is characterized in that the interlayer connection portion is formed in a region provided with a protruding portion in which the metal core layer is partially protruded in the thickness direction. A step of partially providing a protrusion protruding in the thickness direction on the main surface of the conductive foil serving as the metal core layer;
An upper surface and a lower surface of the metal core layer are covered with an insulating layer, a first wiring layer and a second wiring layer are provided on the upper surface and the lower surface of the insulating layer, and the first wiring layer or the second wiring layer and the metal core layer are provided. And a step of forming an interlayer connection portion that conducts in a region where the protruding portion is provided.

Images