JP4528018B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP4528018B2
JP4528018B2 JP2004129644A JP2004129644A JP4528018B2 JP 4528018 B2 JP4528018 B2 JP 4528018B2 JP 2004129644 A JP2004129644 A JP 2004129644A JP 2004129644 A JP2004129644 A JP 2004129644A JP 4528018 B2 JP4528018 B2 JP 4528018B2
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wiring
chip
layer
formed
wiring layer
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JP2005311240A (en
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昌宏 春原
啓 村山
光敏 東
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新光電気工業株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]

Description

  The present invention relates to a technique for manufacturing a semiconductor device, and more particularly, to a semiconductor device having a package structure in which chips such as semiconductor elements and electronic components are mounted inside a wiring board, and a method for manufacturing the same.

  In the following description, a semiconductor device in which a chip is mounted inside a wiring board is also referred to as a “chip built-in package” for convenience.

  In recent years, printed circuit boards have been required to be lighter, and equipped with BGA (Ball Grid Array), PGA (Pin Grid Array), CSP (Chip Size Package), etc., which are small and multi-pinned. Therefore, miniaturization and high density of wiring are required. However, since a conventional printed wiring board requires a large area for forming a via hole, the degree of freedom in design is limited and it is difficult to miniaturize the wiring. Therefore, a printed wiring board (build-up multilayer wiring board) using a build-up method has been put into practical use in recent years. This build-up multilayer wiring board can be manufactured in various types by combining the material of the interlayer insulating layer and the process of forming the via hole. The basic process is for the formation of the insulating layer and the interlayer connection in the insulating layer. The conductor layers are stacked while successively repeating the formation of the via holes and the formation of the conductor layers (patterned wiring, pads, etc.) including the inside of the via holes. In a multilayer wiring board obtained by such a build-up method, it is possible to mount even a semiconductor element (chip) whose degree of integration has progressed.

  On the other hand, a package structure intended to form a required circuit block by incorporating or stacking semiconductor elements (chips) in a substrate is proposed as a method for achieving higher integration and higher functionality of a semiconductor device. Has been. In this package structure, since the chip is embedded and mounted in the substrate, there is an advantage that the thickness of the entire package after mounting can be reduced as compared with a type in which the chip is mounted on the surface of the substrate.

  In a semiconductor device (chip built-in package) having such a package structure, when a wiring is drawn out from a built-in chip, in the conventional technology, after the chip is mounted in the package, the chip connection is formed on the electrode pad of the chip. Connected to the wiring layer on the package from the chip through the via hole of the package, the wiring is drawn out (re-wiring) on the package, and the outside of the back surface of the package is electrically connected to the drawn wiring. The wiring is routed to the pad (external terminal pad) to which the connection terminal is bonded.

As a technique related to the above-described chip built-in package, for example, as described in Patent Document 1, in a semiconductor device in which a wiring pattern is formed on a core substrate via an insulating layer, an inner layer in which the wiring pattern is formed In addition, there is one in which a semiconductor element thinner than the thickness of the insulating layer is mounted by being electrically connected to the wiring pattern by flip chip connection.
JP 2001-177045 A

  As described above, in the conventional package with a built-in chip (semiconductor device), the wiring is drawn out (re-wiring) from the chip on the package while the chip is mounted in the package, and further to the external terminal pad on the back surface of the package. I was trying to route the wiring.

  In this case, the electrode pad (chip pad) of the built-in chip and the external terminal pad of the package usually need to be connected to each other as specified by the customer, depending on the design (layout) specified by the customer. Inconveniently, each wiring connecting each chip pad and each external terminal pad of the package crosses each other in the same wiring layer. That is, in some cases, it is not always possible to draw out the required wiring in the same wiring layer (one layer).

  In such a case, as a general method in the prior art, the wiring layer of the package is increased by one layer, and some of the crossed portions of the wiring are routed in the increased wiring layer. Then, there is a method for enabling the three-dimensional intersection of each wiring.

  However, in this method, it is necessary to increase not only the wiring layer but also the interlayer insulating layer, and accordingly, the thickness of the entire package is increased, and the manufacturing process of the package is increased accordingly. There was a problem of becoming higher.

  The present invention was created in view of the problems in the prior art, and enables the required wiring to be pulled out without increasing the total number of wiring layers, thereby reducing the thickness of the package and contributing to the reduction in manufacturing cost. An object of the present invention is to provide a semiconductor device (chip built-in package) that can be manufactured and a method for manufacturing the same.

In order to solve the above-described problems of the prior art, according to one aspect of the present invention, there is provided a semiconductor device having a package structure in which a chip is mounted inside a wiring board, wherein the wiring board is formed on both sides. And the insulating base material which has the conductor layer electrically connected mutually, the insulating layer formed in both surfaces of this insulating base material, respectively, and the wiring was each drawn out in the required shape on this insulating layer A wiring layer, wherein the chip is electrically connected to an electrode pad exposed from an opening of the protective film on the chip, and a wiring is drawn out in a required shape on the protective film And is mounted on one surface of the insulating base material with the surface opposite to the side on which the wiring layer of the chip is formed facing the insulating base material side . it on the portion extending in the wiring in the wiring layer The formed pad has a corresponding wiring layer on the wiring substrate through a first via hole formed through the insulating layer in the thickness direction in the area where the wiring layer of the chip is formed. In addition, the insulating substrate is electrically connected to each of the wirings via a second via hole formed in the peripheral region of the chip through the insulating layer in the thickness direction. A semiconductor device is provided which is electrically connected to the corresponding upper conductor layer .

According to the semiconductor device of this embodiment, the wiring layer for drawing the wiring is divided into the wiring layer on the built-in chip and the wiring layer on the wiring substrate, and each has a predetermined connection relationship between them. The wiring is pulled out (re-wiring) while maintaining the above. The predetermined connection relationship is that a pad is formed on the extended portion of each wiring in the wiring layer on the chip and reaches the pad in the area where each wiring on the chip is formed. The first via hole is formed and is connected to each wiring in the corresponding wiring layer on the wiring board through the first via hole. That is, instead of drawing the wiring from the chip on the package after the chip is built into the package (wiring board) as in the past, the wiring is divided into the chip and the wiring board in the required shape. Therefore, the required wiring can be drawn without increasing the total number of wiring layers. In other words, in the conventional technique, it was necessary to increase the wiring layer by one in order to prevent the wiring from crossing in the same wiring layer, but in the present invention, this is not necessary, so the wiring is compared with the conventional type. The total number of layers can be reduced by one layer.

  As a result, the thickness of the entire mounted semiconductor device (chip built-in package) can be relatively reduced, which can contribute to a reduction in manufacturing cost.

Further, according to another aspect of the present invention, the wafer level packaging technique is used to electrically connect to the electrode pad exposed from the opening of the protective film, and the wiring is formed in a required shape on the protective film. The chip wiring layer is formed on one surface of the insulating substrate having a step of producing a chip having a drawn wiring layer and a conductive layer formed on each side and electrically connected to each other. Mounting the chip with the surface opposite to the side facing the insulating base, forming the insulating layer on both sides of the insulating base and covering the chip, and the insulating layer on the side where the chip is mounted, at a position corresponding to the portion where the pad is formed of a wiring layer of the chip, to form a first via hole so as to reach the said pad, said insulating group Conductor layer on the material is formed In a position corresponding to a portion that is, forming a second via hole so as to reach the conductor layer, wiring required shape, including the inside of the first via hole and the second via hole is drawn Forming a wiring layer. A method for manufacturing a semiconductor device is provided.

  According to the method for manufacturing a semiconductor device according to this embodiment, a chip on which wiring has been performed in a separate process in advance using a wafer level packaging technique is manufactured, and the chip is processed in the process of manufacturing a wiring substrate (package). Is embedded and implemented. That is, as in the semiconductor device according to the above embodiment, wiring is performed in a required shape in a state of being divided into a chip and a wiring board, so that the required wiring can be drawn without increasing the total number of wiring layers. And the thickness of the entire semiconductor device after mounting can be reduced. In addition, since the number of manufacturing steps of the package associated with the addition of the wiring layer (and the interlayer insulating layer) does not increase as in the conventional case, it is possible to contribute to further reduction of the manufacturing cost.

  Other structural features of the present invention and the advantages obtained thereby will be described with reference to the detailed embodiments described below.

  FIG. 1 schematically shows a configuration of a semiconductor device (chip built-in package) according to an embodiment of the present invention in the form of a sectional view.

  The semiconductor device 10 according to this embodiment includes a wiring board 20 provided as a package and a semiconductor element (silicon (Si) chip) 30 embedded and mounted in the wiring board (package) 20. In the wiring substrate (package) 20, 21 is an insulating base material (for example, glass cloth impregnated with a thermosetting resin such as epoxy resin or polyimide resin) as a core substrate of this package, and 22a and 22b are cores. Conductor layers (for example, copper foils) 23 patterned on both sides of the substrate 21 in a required shape are formed on the inner walls of through holes formed through the core substrate 21 at required positions in the thickness direction. The conductor layer (for example, Cu plating layer), 24 is an insulator (for example, epoxy resin) filled inside the Cu plating layer 23 in the through hole, and 25a and 25b are conductor layers 22a and 25b on both sides of the core substrate 21, respectively. 22b, a conductor layer (for example, Cu) patterned in a required shape on the Cu plating layer 23 and the insulator 24, respectively, and 26a, 26b are conductors on both sides of the core substrate 21. Resin layers (for example, epoxy resin layers) 27a and 27b as interlayer insulation layers formed on the layers 22a and 22b and the conductor layers 25a and 25b, respectively, are required on the resin layers 26a and 26b on both sides of the core substrate 21, respectively. The wiring layer (for example, Cu) patterned in the shape of is shown.

  Each wiring layer 27a, 27b is formed into a pattern in a required shape, and at this time, it is formed so as to include the pad 27P. That is, the pad 27P of the wiring layer 27a on the side (in the illustrated example) on which the external semiconductor element (chip) is mounted is patterned so as to correspond to the position of the electrode of the external semiconductor chip to be mounted. The pads 27P of the wiring layer 27b on the opposite side (lower side) are patterned so as to correspond to the joint positions of the external connection terminals used when mounted on a printed wiring board such as a mother board. Further, the upper wiring layer 27a fills the inside of the via hole VH1 formed so as to reach the pad 33P of the wiring layer 33 on the chip in the mounting area of the built-in chip 30, and the area around the chip The pattern is formed so as to fill the inside of the via hole VH2 formed so as to reach the conductor layer 25a on the core substrate 21. On the other hand, the lower wiring layer 27b is patterned so as to fill the inside of the via hole VH2 formed so as to reach the conductor layer 22b on the core substrate 21. In the illustrated example, the wiring layer 27a formed in the area around the built-in chip 30 is connected to the lower wiring layer 27b via the conductor layer 25a, the conductor layer 23, and the conductor layer 22b on the core substrate 21. Yes.

  28a and 28b are solder resist layers 29a as protective films formed so as to cover the wiring layers 27a and 27b and the resin layers 26a and 26b so that the pads 27P of the wiring layers 27a and 27b on both sides are exposed. , 29b are nickel (Ni) / gold (Au) plating layers deposited on the pads 27P exposed from the solder resist layers 28a, 28b, respectively.

  On the other hand, the chip 30 built in the wiring board (package) 20 is re-wired in a separate process in advance using a wafer level packaging technique as will be described later, and an external semiconductor chip is mounted. Embedded in the resin layer 26a on the side to be processed. Around the chip 30, for example, electrode pads 31 made of a metal such as aluminum (Al) are arranged, and each electrode pad 31 is formed of a passivation film 32 as a protective film formed so as to cover the chip 30. It is exposed from the opening. In addition, a wiring layer 33 electrically connected to each electrode pad 31 is re-wired in the inner direction of the chip 30, and a die attach / attach is provided on the surface opposite to the side where the wiring layer 33 is formed. A film 34 is attached. The chip 30 is mounted on the core substrate 21 via the die attach film 34. A pad 33P is defined on a portion extending inward of the wiring layer (redistribution layer) 33, and the pad 33P is connected to the wiring layer 27a via a via hole VH1 formed in the resin layer 26a. It is connected to the. Since the chip 30 is embedded and mounted in the wiring substrate 20, it is desirable to use a chip having the smallest possible thickness. In the current technology, semiconductor chips having a thickness of about 50 μm to 100 μm are provided, and it is technically possible to embed the semiconductor chip in a substrate if the semiconductor chip has such a thickness. Therefore, in this embodiment, a thin chip having a thickness of about 50 μm to 100 μm is used as the built-in chip 30.

  Unless otherwise defined in the following description, the term “chip” is simply connected to the electrode pad 31 exposed from the opening of the passivation film 32 of the chip 30 and is reconnected in the inner direction. The term “device” refers to a “device” having a wired wiring layer 33 and having a die attach film 34 attached to a surface opposite to the side on which the wiring layer 33 is formed.

  FIG. 2 schematically shows, in a plan view, an example of wiring drawing on the chip 30 and an example of wiring drawing on the package 20 in the semiconductor device (chip built-in package) 10 of the present embodiment. .

  In the drawing, (a) shows the arrangement of the electrode pads 31 of the chip 30 (part), the arrangement of the pads 33P in the wiring layer 33 on the chip, and the wirings (33) for connecting the electrode pads 31 to the pads 33P. An example of drawing is shown. In the illustrated example, five wires (33) are drawn out. On the other hand, (b) shows the arrangement of the pads 27P in the wiring layer 27a on the package 20 in the portion corresponding to the area where the wiring layer 33 of the chip 30 is formed, and the positions corresponding to the pads 33P on the chip 30 (that is, The drawing shows an example of drawing out each wiring (27a) for connecting the chip connection via hole VH1 to the pad 27P.

  As described above, the package 10 with a built-in chip according to the present embodiment is built in the package 20 and in this case, instead of drawing the wiring (rewiring) on the package after the chip is mounted in the package as in the prior art. It is characterized in that the wiring is drawn out (re-wiring) while being divided into the chips 30 individually and maintaining an organic relationship between them. The “organic relationship” here means that a via hole VH1 is provided so as to reach the pad 33P in an area where each wiring (33) of the chip 30 is formed, and each wiring of the package 20 is formed on the via hole VH1. The relationship (27a) is formed. That is, the portions indicated by the same numbers surrounded by circles in FIGS. 2A and 2B (1 to 5 in the illustrated example) are planar when the chip 30 is mounted in the package 20. A relationship that overlaps at the same position.

  When an external semiconductor chip is mounted on the device (chip built-in package) 10, for example, the pad 27P (Ni / Au plating) of the wiring layer 27a exposed from the opening of the upper solder resist layer 28a is used. The chip is flip-chip connected to the layer 29a) so that electrodes such as solder bumps bonded onto the pads of the semiconductor chip to be mounted are electrically connected, and further, an underfill is formed between the solder resist layer 28a. Fill with resin, heat cure and bond. Further, when the present device (chip built-in package) 10 is mounted on a printed wiring board such as a mother board, the pad 27P (Ni / Au plating layer) exposed from the opening of the lower solder resist layer 28b is similarly applied. 29b), solder balls provided as external connection terminals are joined by reflow (solder bumps), connected to corresponding pads or lands on the motherboard via the solder bumps, and further to the solder resist layer 28b. Fill underfill with underfill resin, heat cure and bond.

  The semiconductor device (chip built-in package) 10 according to the present embodiment can be manufactured using a build-up technique. However, in the manufacturing method according to the present embodiment, as described below, a chip 30 that has been re-wired in a separate process in advance using a wafer level packaging technique is manufactured, and the wiring substrate (package) 20 is mounted. The chip 30 is embedded and mounted in the middle of the manufacturing process. Hereinafter, an example of the manufacturing method will be described with reference to FIGS.

<Manufacturing process of chip 30: see FIG. 3>
In the first step (see FIG. 3A), a wafer 30a in which a plurality of devices are fabricated is manufactured by a method well known to those skilled in the art. That is, after a predetermined device process is performed on a silicon (Si) wafer having a predetermined thickness (for example, a thickness of about 725 μm in the case of an 8-inch diameter wafer), one side of the wafer (illustrated In this example, a passivation film 32 made of silicon nitride (SiN), phosphorus glass (PSG), or the like is formed on the upper surface), and a part of an aluminum (Al) wiring layer formed in a predetermined pattern on each device. A portion of the passivation film 32 corresponding to the electrode pad 31 to be formed is removed, and the portion is opened. This opening is performed by laser processing such as a YAG laser or an excimer laser. As a result, a wafer 30a whose surface is covered with the passivation film 32 and the electrode pads 31 are exposed as shown in the drawing is produced.

  In the next step (see FIG. 3B), rewiring is patterned into a required shape for each device on the surface of the wafer 30a where the electrode pads 31 are exposed (formation of the wiring layer 33). ).

  Specifically, first, chromium (Cr) or titanium (Ti) is deposited on the entire surface on the side where the electrode pad 31 is exposed by sputtering, and further copper (Cu) is deposited thereon by sputtering, A seed layer (not shown) having a two-layer structure of Cr (Ti) / Cu is formed. Next, a plating resist is formed on the entire surface of the seed layer (for example, a photosensitive dry film is laminated), and exposure is performed so that a specific portion (a portion corresponding to a position where the wiring layer 33 is to be formed) is exposed. And developing (patterning of the dry film) to open the corresponding portion of the plating resist, and then subjecting the seed layer exposed from the opening to electrolytic Cu plating using the seed layer as a power feeding layer, Cu wiring A layer (rewiring pattern) 33 is formed. Thereafter, the plating resist is peeled off, and the exposed portion of the seed layer (Cr (Ti) / Cu) is removed by wet etching (first Cu is etched and then Cr (Ti) is etched). At this time, the exposed wiring layer 33 is also etched, but since the film thickness is considerably thicker than that of the seed layer (Cr (Ti) / Cu), the etched portion is only the surface layer portion of the wiring layer 33. Absent.

  In the above-described steps (see FIGS. 3A and 3B), the wiring layer 33 is formed on the passivation film 32. However, as another form, an epoxy resin or a polyimide resin is further formed on the passivation film 32. Alternatively, an insulating layer made of resin or the like may be formed, the electrode pad 31 may be exposed from the insulating layer, and then the wiring layer 33 may be formed on the insulating layer made of resin. In this case, the insulating layer made of resin can be formed by depositing a resin by spin coating or by laminating resin films. The electrode pad 31 is exposed by laser processing an insulating layer made of resin. Or when this resin has photosensitivity, the electrode pad 31 is exposed by exposing and developing the insulating layer made of resin.

  In the last step (see FIG. 3C), a chip 30 as a device built in the package is manufactured.

  Specifically, first, the back surface (the lower surface in the illustrated example) of the rewiring wafer 30a is ground using a known grinding apparatus, and thinned to a predetermined thickness (for example, about 50 μm to 100 μm). To do. Next, the die attach film 34 is affixed to the back surface of the wafer subjected to the back surface grinding. The die attach film 34 has a structure in which an adhesive is applied to a base material such as a PET film having heat resistance (up to about 240 ° C.), and the back surface of the wafer is interposed through the adhesive layer. Is pasted. This film 34 is provided to cope with the possibility of wafer cracking due to mechanical impact during subsequent dicing, and functions as a reinforcement for the chip when it is separated into individual chips. To do. The reason why the film 34 needs to be “heat resistant” is that it can withstand the heating temperature at that time in order to perform “cure” when the build-up resin is laminated in the subsequent manufacturing process of the wiring board (package). This is to make it possible. Finally, the rewiring wafer with the die attach film 34 attached to the back surface is cut by a dicer or the like and divided into individual rewiring chips 30 (three devices in the illustrated example). To do.

<Manufacturing Process of Wiring Board 20: See FIGS. 4 to 6>
In the first step (see FIG. 4A), a copper-clad laminate (for example, a prepreg (insulating base material 21) made of glass cloth as a base material and impregnated with epoxy resin, BT resin, polyimide resin, etc.) A plate in which copper foils 22a and 22b are laminated and bonded to each other is prepared, and a through hole TH is formed at a required position by drilling with a mechanical drill.

  In the next step (see FIG. 4B), a Cu plating layer 23 is deposited on the inner wall of the through hole TH by, for example, electroless Cu plating. Furthermore, an epoxy resin is filled in the through hole TH to which the Cu plating layer 23 is deposited by, for example, screen printing (insulator 24). At this time, since the portion filled with the resin is not necessarily flat, the portion is polished and flattened as necessary.

  In the next step (see FIG. 4C), conductor layers 25a and 25b are formed in required pattern shapes on the copper foils 22a and 22b, the Cu plating layer 23 and the insulator 24 on both sides of the core substrate 21, respectively. Further, the copper foils 22a and 22b laminated on both surfaces of the core substrate 21 are respectively patterned into required shapes to partially expose the core substrate 21.

  Specifically, first, a seed layer (not shown) is formed on both flattened surfaces by electroless Cu plating, and then a plating resist is formed on the entire surface (for example, a photosensitive dry film is laminated). Then, exposure and development (patterning of the dry film) are performed so that the specific part (part corresponding to the position where the conductor layers 25a and 25b are to be formed) is exposed, and after opening the part of the plating resist, On the seed layer exposed from the opening, electrolytic Cu plating is performed using the seed layer as a power feeding layer to form conductor layers 25a and 25b. Further, after removing the plating resist (dry film), an etching resist is formed on the entire surface (for example, a photosensitive liquid resist is applied or a photosensitive film resist is laminated), and the etching resist is formed into a required shape. After patterning and opening the part, the seed layer (Cu) and the copper foils 22a and 22b exposed from the opening are removed by wet etching to partially expose the core substrate 21. Thereafter, the etching resist is removed.

  In the next step (see FIG. 4D), the core substrate 21 was fabricated on the exposed portion of one surface (the upper side in the illustrated example) by the steps of FIGS. 3A to 3C. The wiring layer 33 has a wiring layer 33 that is electrically connected to the redistributed chip 30, that is, the electrode pad 31 exposed from the opening of the passivation film 32 and is rewired inward. The “device” is mounted in a state where the die attach film 34 is attached to the surface opposite to the side on which is formed.

  In the next step (see FIG. 5A), both surfaces of the core substrate 21 on which the chip 30 (including the electrode pad 31, the passivation film 32, the wiring layer 33, and the die attach film 34) is mounted on one surface. Further, resin layers (interlayer insulating layers) 26a and 26b are formed so as to cover the chip 30, the copper foils 22a and 22b, and the conductor layers 25a and 25b, respectively. For example, a thermosetting resin such as an epoxy resin or a polyimide resin is laminated. Then, a curing (curing) process is performed together with the planarization and the press process.

In the next step (see FIG. 5B), specific positions of the resin layers 26a and 26b respectively formed on both surfaces (for the upper resin layer 26a, the pads of the wiring layer 33 redistributed on the chip 30). The copper foil 22b on the core substrate 21 is formed on the lower resin layer 26b at a position corresponding to the portion where the 33P is formed and the portion where the conductor layer 25a is formed on the core substrate 21. A via hole VH1 for chip connection is formed so as to reach the pad 33P, and a via hole VH2 for substrate connection is formed so as to reach the conductor layer 25a and the copper foil 22b. For example, the via holes VH1 and VH2 are formed by removing the corresponding portions of the resin layers 26a and 26b with a CO 2 laser, a UV-YAG laser, or the like.

  In the next step (see FIG. 6A), wiring layers 27a and 27b are formed on the resin layers 26a and 26b on both sides in a required pattern shape including the insides of the via holes VH1 and VH2, respectively. Each of the wiring layers 27a and 27b can be formed basically in the same manner as the process performed in the step of FIG.

  For example, a seed layer (not shown) is formed on the entire surface of each of the resin layers 26a and 26b including the inside of the via holes VH1 and VH2 by electroless Cu plating, and then a plating resist is formed on the entire surface (for example, photosensitive After laminating a dry film, exposure and development (patterning of the dry film) are performed so that the specific part (at least the part corresponding to the position of the via holes VH1 and VH2) is exposed, and the corresponding part of the plating resist is opened On the seed layer exposed from the opening, electrolytic Cu plating is performed using the seed layer as a power feeding layer to form wiring layers 27a and 27b. Thereafter, the plating resist is peeled off, and the exposed portion of the seed layer (Cu) is removed by wet etching. At this time, the exposed wiring layers 27a and 27b are also etched, but since the film thickness thereof is considerably thicker than that of the seed layer (Cu), the etched portion is only the surface layer portion of the wiring layers 27a and 27b. .

  When the wiring layers 27a and 27b are thus formed, the electrode pads 31 of the built-in chip 30 are connected to the wiring layer 33 (pad 33P) on the chip and the conductor (the wiring layer 27a of the wiring layer 27a) filled in the via hole VH1. It is connected to the wiring layer 27a via a part). The wiring layer 27a is connected to a wiring layer 27a formed in another region via an external semiconductor chip mounted on the package, and further, a conductor (wiring layer 27a filled in the via hole VH2). ), The conductor layer 25a on the core substrate 21, the Cu plating layer 23, and the copper foil 22b are connected to the lower wiring layer 27b.

  In the last step (see FIG. 6B), a solder resist layer (protective film) is formed so as to cover the wiring layers 27a and 27b and the resin layers 26a and 26b so that the pads 27P of the wiring layers 27a and 27b on both sides are exposed. ) 28a and 28b are formed. For example, a photosensitive solder resist is applied to both sides, and exposure and development (solder resist patterning) are performed so as to follow the required shape of the pad 27P, respectively, and a portion of the solder resist layer corresponding to the area of the pad 27P is opened. To do. As a result, only the pads 27P of the wiring layers 27a and 27b are exposed, and the other wiring layers 27a and 27b are covered with the solder resist layers 28a and 28b.

  Further, Ni plating and Au plating are performed on each pad 27P (Cu) exposed from the solder resist layers 28a and 28b, thereby forming Ni / Au plating layers 29a and 29b. This is to improve the adhesion with the pad 27P when solder bonding is performed at a later stage. As a result, the semiconductor device (chip built-in package) 10 of this embodiment is manufactured.

  As described above, according to the semiconductor device (chip built-in package) 10 and the manufacturing method thereof according to the present embodiment, the wiring layer from which the wiring is drawn is formed on the wiring layer 33 on the built-in chip 30 and the wiring substrate 20. The wiring layer 27a is divided into the wiring layers 27a, and the wiring is drawn out (re-wiring) individually and while maintaining the above-described organic relationship. In other words, the wiring is not drawn in a lump in a state where the chip is built in the package (wiring board) as in the conventional case, but the rewiring is performed in a required shape in the state where the chip 30 and the wiring board 20 are divided. Therefore, the required wiring can be drawn without increasing the total number of wiring layers.

  In other words, in the conventional technique, it is necessary to increase the wiring layer by one layer in order to prevent the wiring from crossing in the same wiring layer. However, in the present embodiment, this is not necessary. The total number of wiring layers can be reduced by one layer. As a result, the overall thickness of the semiconductor device (package with a built-in chip) 10 after mounting can be relatively reduced, and the manufacturing process of the package accompanying the increase of the wiring layers (and interlayer insulating layers) as in the prior art can be reduced. Since it does not increase, the manufacturing cost can be reduced.

  Further, in the conventional technique, a chip connection via hole (laser via) formed by laser processing is directly provided on the electrode pad of the built-in chip, and thus the chip may be damaged during laser processing. In this embodiment (see the process of FIG. 5B), the area where the laser via VH1 is redistributed on the chip 30 (that is, on the wiring layer 33 redistributed on the electrode pad 31 via the passivation film 32). Therefore, the possibility that the chip 30 is directly damaged during laser processing can be eliminated.

  In this regard, in the prior art, there is a technique in which a laser via stopper layer is formed on the chip by Cu plating in order to reduce the possibility of the chip being damaged during laser processing. Then (see the process of FIG. 3B), the wiring layer (Cu plating layer) 33 formed in the rewiring process on the wafer 30a can also be used as a stopper layer. That is, the formation of the stopper layer and the rewiring process on the wafer can be performed at the same time, which contributes to further reduction in manufacturing cost.

  In the above-described embodiment, the case where the chip 30 is built in the buildup layer (resin layer 26a) stacked on the upper side of the core substrate 21 (the side on which the external semiconductor chip is mounted) has been described as an example. Of course, the resin layer containing 30 is not limited to this. For example, the chip 30 can be built in the build-up layer on the lower side of the core substrate 21 (the side on which the package 10 is mounted on a motherboard). It is. As is apparent from the gist of the present invention, the point is that, as schematically shown in FIG. 2, the chip 30 and the package 20 are separated individually and an organic relationship is maintained between them. It is sufficient that each wiring is drawn out (re-wiring).

  In the above-described embodiment, the case where one chip 30 is built in one package has been described as an example. However, a function required for the package 10 or an external semiconductor chip mounted on the package 10 is described. Depending on the function required, two or more chips 30 may be appropriately incorporated.

It is sectional drawing which shows the structure of the semiconductor device (chip built-in package) which concerns on one Embodiment of this invention. FIG. 2 is a plan view schematically showing an example of wiring drawing on a “chip” and a wiring drawing example on a “package” in the semiconductor device of FIG. 1; FIG. 3 is a cross-sectional view showing a manufacturing process of a “chip” portion constituting the semiconductor device of FIG. 1. FIG. 7 is a cross-sectional view showing a manufacturing process (No. 1) of a portion of “package” constituting the semiconductor device of FIG. It is sectional drawing which shows the manufacturing process (the 2) following the manufacturing process of FIG. FIG. 6 is a cross-sectional view showing a manufacturing process (part 3) following the manufacturing process of FIG. 5;

Explanation of symbols

10: Semiconductor device (chip built-in package),
20: Wiring board (package),
21 ... Core substrate (insulating base material),
22a, 22b ... copper foil (conductor layer),
23 ... Cu plating layer (conductor layer),
24 ... Resin (insulator),
25a, 25b ... Cu plating layer (conductor layer),
26a, 26b ... resin layer (insulating layer),
27a, 27b ... wiring layer (rewiring layer),
27P ... pad,
28a, 28b ... solder resist layer (protective film),
29a, 29b ... Ni / Au plating layer,
30: Semiconductor element (chip),
31 ... Al pad (electrode pad),
32 ... Passivation film (protective film),
33 ... Wiring layer (rewiring layer),
33P ... pad,
34 ... Die attach film,
TH ... Through hole,
VH1, VH2 ... via holes.

Claims (4)

  1. A semiconductor device having a package structure in which a chip is mounted inside a wiring board,
    The wiring board is formed on both surfaces and has an insulating base material having a conductor layer electrically connected to each other, an insulating layer formed on each surface of the insulating base material, and an insulating layer on the insulating layer. Each has a wiring layer in which wiring is drawn out in a required shape,
    The chip has a wiring layer electrically connected to an electrode pad exposed from an opening of a protective film on the chip and a wiring is drawn out in a required shape on the protective film, and the insulating property Mounted on one surface of the base material with the surface opposite to the side where the wiring layer of the chip is formed facing the insulating base material side,
    Pads respectively formed on the extended portion of each wiring in the wiring layer on the chip are formed through the insulating layer in the thickness direction in the area where the wiring layer of the chip is formed. The first via hole is electrically connected to each wiring in the corresponding wiring layer on the wiring board, and the wiring layer further extends the insulating layer in the thickness direction in the region around the chip. A semiconductor device, wherein the semiconductor device is electrically connected to a corresponding conductor layer on the insulating substrate through a second via hole formed therethrough .
  2.   The semiconductor device according to claim 1, wherein a protective film is formed on the wiring layer by exposing a pad of the wiring layer on the wiring substrate.
  3. A step of producing a chip having a wiring layer electrically connected to an electrode pad exposed from the opening of the protective film and having a wiring drawn out in a required shape on the protective film , using wafer level packaging technology When,
    One surface of an insulating base material having conductor layers formed on both surfaces and electrically connected to each other, the surface opposite to the side where the wiring layer of the chip is formed is the insulating base material. Mounting the chip toward the side,
    Forming an insulating layer on both sides of the insulating base material so as to cover the chip;
    A first via hole is formed so as to reach the pad at a position corresponding to a portion where the pad of the wiring layer of the chip is formed on the insulating layer on the side where the chip is mounted . Forming a second via hole so as to reach the conductor layer at a position corresponding to a portion where the conductor layer is formed on the substrate;
    Forming a wiring layer in which wiring is drawn out to a required shape including the inside of the first via hole and the second via hole.
  4. 4. The semiconductor according to claim 3 , further comprising a step of forming a protective film covering the wiring layer and the insulating layer so that a pad of the wiring layer is exposed after the step of forming the wiring layer. Device manufacturing method.
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JPWO2010134511A1 (en) * 2009-05-20 2012-11-12 日本電気株式会社 Semiconductor device and manufacturing method of semiconductor device
US8810008B2 (en) 2010-03-18 2014-08-19 Nec Corporation Semiconductor element-embedded substrate, and method of manufacturing the substrate
KR101555142B1 (en) * 2014-04-15 2015-09-23 주식회사 코리아써키트 Integrated chip manufacturing method FPCB

Citations (3)

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Publication number Priority date Publication date Assignee Title
JP2001217337A (en) * 2000-01-31 2001-08-10 Shinko Electric Ind Co Ltd Semiconductor device and manufacturing method therefor
JP2003046028A (en) * 2001-07-27 2003-02-14 Ibiden Co Ltd Method of manufacturing multilayer printed wiring board
JP2005216935A (en) * 2004-01-27 2005-08-11 Casio Comput Co Ltd Semiconductor device and its production process

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001217337A (en) * 2000-01-31 2001-08-10 Shinko Electric Ind Co Ltd Semiconductor device and manufacturing method therefor
JP2003046028A (en) * 2001-07-27 2003-02-14 Ibiden Co Ltd Method of manufacturing multilayer printed wiring board
JP2005216935A (en) * 2004-01-27 2005-08-11 Casio Comput Co Ltd Semiconductor device and its production process

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