TWI241006B - Semiconductor package substrate with conductive structure of interlayer and method for fabricating the same - Google Patents

Abstract

A semiconductor package substrate with conductive structure of interlayer and a method for fabricating the substrate are proposed, which includes: providing an inner substrate including patterned conductive metal layers formed thereon and a plurality of plated through holes formed therethrough; applying an insulating layer on the inner substrate and within the plated through holes and then forming an opening corresponding to each plated through hole, wherein the dimension of the opening is less than the plated through hole; forming a metal layer on the insulating layer and within the openings. Accordingly, making vertical electrical connection between different circuit layers via the metal layer within the plated through hole can significantly reduce conductive pathway of signals, improve the electrical performance of the substrate, decrease the amount of blind vias, and extend area of circuits layout of the substrate.

Description

1241006 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a manufacturing method, especially a circuit layer with special layers, which is improved by half [Previous technology]: With the booming and high performance of the electronics industry Research and development trends (Integrati ο η) and miniaturization for more active and passive components and the evolution from double-layer board to multi-layer board space, the use of interlayer connections to expand semiconductor package substrates combined with high electron density integrated electric low-package substrates Thickness in terms of the amount of lines and components. In order to respond to microprocessors and semiconductor packages with wires, the frequency bandwidth and impedance control functions are good. However, in order to comply with the development direction of semiconductors and high-frequency, we are expanding. Existing semiconductor packaging bases: including wire width (Aspect ratio), etc., with small line accuracy. R & D of semiconductor package substrates with interlayer conductive structures and interlayer conductive structures to conductively connect upper and lower conductor packaging substrates. The development of electronic products has gradually moved into multi-functionality. In order to meet the packaging requirements of semiconductor packages (Miniaturization), circuit mounting, semiconductor packaging substrates (Multi-layer board) have gradually been limited to limited technology (Interlayer connection) to make available the layout area of the circuit, so that the integrated circuit needs to accommodate more chipsets and graphics chips in the same substrate unit area. The substrate also needs to improve its signal transmission. To improve the development of high I / 〇 number packages, packages are thin, short, multifunctional, and high X speed. Package substrates have been oriented towards fine lines and small apertures. The board manufacturing process has been changed from the traditional line size of 100 micrometers to X. Width), line space (Space), and deep reduction to less than 30 microns, and continue to be more π

1241006 V. Description of the invention (2) ^ ~ 'In order to improve the wiring accuracy of the semiconductor package substrate, the industry has developed a build-up technology, that is, a core circuit board X (\ 〇re circuit board) On the surface, multiple layers of insulation layers and circuit layers are alternately stacked by using a circuit build-up technology, and conductive blind holes (conductive v 1 a) are opened in the insulation layer for the electrical connection between upper and lower lines. Among them, the circuit layer

This is the key to affecting the circuit density of the semiconductor package substrate. According to the current technology, most of the industry's semi-additive method (Semi-additive prOcess, SA plating method (Pattern plating method)) is used to make circuit layering. 1 A to 1 C, the so-called semi-additive method provides a core circuit board 10, and an insulating layer 11 is formed on the surface. The laser drilling (hs

dr i U i ng) technology forms openings in the insulating layer 11, and aSeF u 1 i u M runs through the inner circuit layer 1 2 of the core circuit board 10 (as shown in FIG. 1A). A conductive seed layer is formed on the insulating layer 11 by electroless copper plating, and a patterned resist layer 14 is applied on the seed layer 13 to perform electroplating, so as to: the surface of the layer 1 3 A patterned circuit layer 15 is formed (as shown in FIG. 1B). After that, the resist layer 14 is peeled off and etched to remove the seed layer 1 3 (shown in FIG. 1C), which was previously covered under the resist layer 4; as such, the steps are repeated to form an insulation layer. The layer and the build-up circuit layer are used to form a semiconductor package substrate having a plurality of circuit layers. In addition, as shown in FIGS. 2A to 2C, the circuit plating method also first provides a core circuit board 20, and forms a surface of the core circuit board 20, such as resin coated copper fl (Resin coated copper, RCC). The metal compression insulation layer 21 is formed with an opening 2 1 0 in the insulation layer 21 by means of laser drilling or the like, so as to communicate with the inner circuit layer 2 2 of the core circuit board 20 (as shown in FIG. 2A). Show).

17448 全 punishment.ptd Page 8 1241006 V. Description of the invention (3) Then, on the insulating layer 21 having a thin metal layer, there is no electric clock and a conductive seed layer 23 'and a pattern is applied on the seed layer 23 The resistive layer 24 is chemically bonded for electrical bonding, and a patterned circuit layer 25 is formed on the conductive seed layer 23 (as shown in FIG. 2B). After that, the resist layer 24 is peeled off for an additional time to remove the seed layer 2 3 previously covered under the resist layer 24 (as shown in FIG. 2C). Then, the above steps can be repeated to form the insulating layer and the build-up circuit layer to complete a semiconductor package substrate having a multilayer circuit layer. However, when a multi-layer semiconductor package substrate manufactured according to the aforementioned semi-additive method or circuit power method is used to transmit the right chip signal from the uppermost layer to the lowermost layer of the semiconductor package substrate, the §fL number must be added from the uppermost layer to the circuit. The upper build-up circuit layer and the conductive blind holes between the upper circuit layers reach the core circuit board, and then pass through the plated thru hole (PTH) inside the core circuit board, and the conductive blindness between the lower build-up circuit layers. The hole and the lower build-up circuit layer 'reach the bottom layer of the substrate. The signal transmission path is too long, which can easily increase the inductance and cause cross-talk or noise (nois es), which will damage the quality of electrical transmission. Second, the traditional core circuit board manufacturing process is shown in Figures 3 to 3D. First, a metal compression insulation layer 300, such as a resin laminated copper box (Resin Coat (i copper, RCC)) is provided, and drilled therein. A plurality of through-holes 302 (as shown in FIG. 3A) are provided, and then a copper plating and patterning process is performed to form an inner-layer circuit layer 30 3 on the surface of the insulating layer 3 0 and the through-holes 3 2 2 A metal layer (as shown in FIG. 3B) is deposited on the hole wall, and a conductive or non-conductive filler 3 1 (such as an insulating ink or a copper-containing conductive paste) is further filled to fill the through-hole 3 0 2 residue Void, and a plated through hole ({) 1 ^) 3〇2 &

17448 全懋 .ptd Page 9 1241006 V. Description of the invention (4) The inner layer of the insulation layer 300 on the upper and lower surfaces is connected to and removed from the redundant filling material 31 in order to maintain eucalyptus and moxibustion. Brush grinding process (as shown in Figure 3C). Hold the core ... the flatness of the surface of the circuit board However, the core circuit board increases the manufacturing cost of the substrate during the manufacturing process. Especially important for the ^ hole and brush grinding process, there will be a lot of plated through holes' often leading to the formation of the layered circuit layer formed on the upper surface of the core circuit J to pattern it: the through holes on the surface extend out of the electrical connection pad (p must Self-plating guide (conduct UCtlve Vla), so that a wave of Vt board is not formed to form a conductive blind hole miniaturization packaging trend, it will be because the wiring area of the gate, the position is unfavorable and affect the use of substrate space. Plating via [Content of the invention]: / The above-mentioned conventional technology is used to provide a semiconductor package substrate sound, 'Gate: The main purpose of the description is to expand the circuit layout of the package substrate ^ V electrical structure and its manufacturing method, borrow

IntTayer circuits) layout flexibility. "Interlayer wiring (Another object of the present invention is the interlayer conductive structure and its manufacturing method = the oil and gas in the core circuit board manufacturing process of the semiconductor package substrate directly plugs the hole to replace the conventional connection surface and the connection of the circuit connection surface ^ The production process is strong, and the insulation layer is improved. The present invention +0 again avoids interfacial peeling. The inductive conductive structure and its manufacturing *: Borrowing the layer of the substrate. The purpose of the present invention is to provide a relationship between m and m. Layers of backing conductor packaging substrate

17448 全懋 .ptd Page 10 1241006 V. Description of the invention (5) The conductive structure and its manufacturing method are used to shorten the signal transmission path to avoid crosstalk and noise and further improve the electrical quality of the semiconductor package substrate. For the above and other purposes, the present invention discloses an interlayer conductive structure of a semiconductor package substrate, including: an inner layer substrate on which an inner layer circuit layer and a plurality of plated vias penetrating through the inner layer substrate are formed; and an insulating layer forming the inner layer A through hole having a size smaller than that of the plated through hole is formed in the surface of the circuit layer and the plated through hole, and a patterned metal layer is formed in the surface of the insulating layer and the hole. . The invention also discloses a method for manufacturing an interlayer conductive structure of a semiconductor package substrate, which includes: providing an inner substrate, wherein the inner substrate is formed with a plurality of plated through holes penetrating through its surface, and an inner circuit layer is formed on the inner substrate surface; An insulating layer is formed on the inner layer substrate and in the plated through hole, and a through hole having a size smaller than the plated through hole is formed at the insulating layer corresponding to the plated through hole; and on the insulating layer and in the hole A patterned metal layer is formed. The patterned metal layer on the insulating layer and in the opening can be formed by forming a conductive film on the surface of the insulating layer and the opening, and then forming a patterned plating resist layer on the conductive film. Way to form. Subsequently, the insulating layer and the patterned metal layer can be repeatedly stacked to fabricate a multilayer semiconductor package substrate. Because the present invention is to form an additional opening in the plated through hole (Plated thr ughugh ο 1 e) of the inner substrate, and a metal layer is formed in the opening, so that the metal layer is electrically connected to the substrate through the metal layer. Patterned

17448 懋 .ptd Page 11 1241006 V. Description of the invention (6) Circuit structure for vertical conductive connection between different circuit layers will shorten the signal conduction path control so that the signal of the upper circuit layer can be directly formed on the plating The metal layers and plated vias of the vias in the vias are transferred to the underlying circuit layer without the need for additional external wiring of conductive blind vias, and the number of conductive blind vias can be reduced, thereby increasing the circuit layout area of the package substrate and enabling circuit layout. More flexibility. In addition, the use of the metal formed in the openings in the plating conduction for signal transmission between layers, in addition to shortening the conductive path, reducing inductance, crosstalk and noise generation, there is no need to implement ink plug holes and Brushing process to simplify process steps and costs. In addition, the use of the same insulating layer on the circuit surface and the plug hole can further improve the bonding strength between the insulating material and the interface between the circuit layer and the plated through hole, avoid interface peeling, and improve the reliability of the package substrate. [Embodiment]: The following is a description of specific embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied by other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the spirit of the present invention. Hereinafter, the preferred embodiments of the interlayer conductive structure of the semiconductor package substrate of the present invention and the manufacturing method thereof will be described in detail with reference to FIGS. 4A to 4L. It should be noted that these drawings are simplified schematic diagrams, and the substrate structure of the present invention is only illustrated schematically. However, the drawings only show the elements related to the present invention, and the elements shown are not the actual implementation, and the actual implementation

17448 Quan 懋 .ptd Page 12 1241006 V. Description of the invention (7) The number of components, shape and size ratio is an optional design, and its component layout may be more complicated. As shown in Figs. 4A and 4B, first, a single-layer or multi-layer circuit board having a pre-processing completed is provided. In the drawing of this embodiment, the inner substrate 40 is made of an insulating layer 400 and a thin metal layer 401 formed on the surface of the insulating layer 400, which is formed by mechanical drilling. A plurality of first openings 4 0 2 (see FIG. 4B) penetrating the substrate are drilled in the inner substrate 40. Wherein, the insulating layer 400 may be epoxy resin, polyimide, cyanate Ester, glass fiber, bismaleic acid imine / trimethylimide Nitrogen brand (Bismaleimide Triazine, BT) or FR5 material mixed with epoxy resin and glass fiber; The thin metal layer 401 is generally based on copper (Cu), which has better conductivity, and is used as a wire material for signal transmission. And the metal thin layer 401 can be first laminated or deposited on the insulating core layer 'or made of resin laminated copper foil (Resin coated copper, RCC), because it can effectively provide the adhesion of the subsequent electroplated metal layer. The preferred embodiment is that before the thin metal layer 401 is deposited, the surface of the insulating layer 401 must be roughened in advance. At the same time, a resin-compressed copper box (RCC) is used as an example in this embodiment. Be explained. As shown in Figure 4C, next, physical vapor deposition (PVD), chemical vapor deposition (CVD), electroless plating, or chemical deposition are used, such as sputtering, evaporation, and arc vapor deposition. (Arc vapor deposition), ion beam sputtering (laser beam sputtering), laser ablation deposition (laser ablation deposition), plasma-assisted chemical vapor deposition or electroless plating, etc.

17448 Quan 懋 .ptd Page 13 1241006 V. Description of the invention (8) A conductive layer (not shown) is formed on the surface of the inner substrate 40 and the first opening 4 02, and the conductive layer is used for current conduction. In order to form a conductive metal layer 403 with sufficient thickness on the surface of the inner layer substrate 40 and on the wall of the first opening 402, a conductive metal layer is formed. As shown in FIG. 4D, a photoresist layer (not shown) is formed, and processes such as exposure, development, and etching are performed to pattern the conductive metal layer 403. In turn, an inner layer circuit layer 403a is formed on the upper and lower surfaces of the inner substrate 40, and a plated through hole (PTH) 402a is formed in the first opening hole 402. As shown in FIG. 4E, an insulating layer 41 is formed on the inner substrate 40, so that the upper and lower surfaces of the inner substrate 40 and the inner circuit layer 403a are covered by the insulating layer 41, respectively. The insulating layer 41 is filled into the remaining space in the plated through hole 40 2 a. The insulating layer 41 may be, for example, ABF (Ajinomoto Build-up Film, trade name, manufactured by Ajinomoto). As shown in FIG. 4F, a second opening 4 1 0 is then opened at the insulating layer 4 1 corresponding to the plated-through hole 4 0 2 a by using a technique such as mechanical drilling, wherein the second opening 4 10 is penetrating the insulating layer, and the hole diameter is smaller than the hole diameter of the plated through hole. As shown in FIG. 4G, next, a patterned circuit build-up process is performed, which can first form a conductive film 4 1 1 and a patterned plating resist layer 412 on the insulating layer 41. The conductive film 411 is mainly described later. The current conducting path required for the metal layer of the clock can be constructed of metal, alloy or stacked metal layers

17448 Quan 懋 .Ptd Page 14 1241006 V. Description of the invention (9) It can be formed from metals selected from the group consisting of copper, tin, nickel, chromium, titanium, and copper-chromium alloys. The conductive film 41 1 may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), electroless plating, or chemical deposition, such as sputtering, evaporation, and arc vapor deposition ( Arc vapor deposition), ion beam sputtering, laser ablation deposition, plasma-assisted chemical vapor deposition, or electroless plating. However, according to actual operation experience, the conductive film 4 1 1 is preferably composed of copper particles having no bond. As shown in FIG. 4, the electroplating method is used to form a plated metal layer 4 2 a in the opening of the patterned plating resist layer 4 1 2, and then the electric bond resist layer 4 1 2 and the conductive layer covering it are removed. The film 4 1 1 forms a patterned metal layer in the insulating layer 41 and the second opening 4 1 0 of the inner substrate 4 0. The patterned metal layer includes a first build-up line on the surface of the insulating layer 41. A layer 42 (First build-up circuits layer) and a plated metal layer 42a filled in the second opening 410. As shown in FIG. 4I and FIG. 4J, a dielectric insulating layer 43 is formed on the first build-up circuit layer 42, and at least one of the dielectric insulating layers 43 is formed. The exposed part of the first build-up circuit layer 4 2 outside the blind hole 4 3 0; the " electricity, and layer 4 3 may be, for example, ABF (Ajinomoto Build-up Film) Epoxy Resin, cyanide Made of ester (Cyanate Ester), glass fiber (Glass Fiber), bismaleimide / triazine (CBismaleimide Triazine, BT) or mixed epoxy resin and glass fiber materials, and can be made by thunder Perforation technique to form the blind holes

17448 全懋 .ptd-page 15 1241006 V. Description of invention (ίο) 4 3 0. Of course, an insulating layer with a thin metal layer (such as resin-coated copper foil) can also be formed on the first build-up circuit layer, and blind holes can be formed by laser drilling technology. As shown in FIG. 4K, a patterned circuit build-up process is then performed to form a second build-up circuit layer 4 4 and a conductive blind hole 4 3 0 a on the dielectric insulating layer 4 3 and the blind hole 4 3 0. Therefore, the conductive blind hole 4 3 0 a can be electrically connected to the first and second layered circuit layers 42 and 44 to complete the production of the layered circuit. Of course, the subsequent build-up process can be continued to form a multilayer circuit structure. The above-mentioned layered layered process for patterned circuits is for illustration only, and is not intended to limit the application scope of the present invention, which will be described together. As shown in FIG. 4L, a patterned solder resist layer (S ο 1 dermask) 4 5 can be formed on the second build-up circuit layer 44 as a protective layer. The solder resist layer 45 has a plurality of openings. A part of the second build-up circuit layer 44 is exposed to produce a multilayer semiconductor package substrate (this embodiment is a six-layer board of 2 + 2 + 2). The interlayer conductive structure of the semiconductor package substrate of the present invention, as shown in FIG. 4 (a), includes: an inner substrate 40, on which an inner circuit layer 4 0 3a is formed, and most of the electrical keys passing through the inner substrate 40 are in conduction The hole 4 〇 2 a ′ an insulating layer 41 is formed on the surface of the inner circuit layer 4 0 3 a and the key vias 40 2 a, and the size corresponding to the plated via 40 2 a is smaller than the plating A second opening 410 of the via 402a; and a patterned build-up circuit layer 42 formed on the surface of the insulating layer 41 and an electrical metal layer 42a in the second opening 410.俾 By forming in the plating through hole (Plating through

17448 Quan 懋 .ptd Page 16 1241006 V. Description of the invention (11) The metal layer of the second opening in the (11) hole) replaces the conductive via (Conductive via) to make vertical conductive connection between different circuit layers, so that the upper layer of the substrate The signal can be quickly connected to the opposite side directly through the metal layer in the second opening (that is, the semiconductor package substrate underneath the other side of the inner substrate) to effectively shorten the signal conduction path, thereby improving the electrical quality of the substrate , Reduce the number of blind holes, and achieve the purpose of expanding the packaging substrate circuit layout area. Therefore, the interlayer conductive structure of the semiconductor package substrate of the present invention and the method for manufacturing the same are an additional opening formed in the electrical through hole of the inner substrate, and a metal layer is formed in the opening to pass through the opening. The metal layer is electrically connected to the patterned circuit structure formed in the substrate for vertical conductive connection between different circuit layers, which can shorten the signal conduction path, so that the signal of the upper circuit layer can be directly formed by the opening formed in the plating via hole. The metal layer of the hole and the plated via are passed to the underlying circuit layer. There is no need to route outside the key via to conduct the conductive blind vias, and the number of conductive blind vias can be reduced, thereby expanding the circuit layout area of the package substrate and making the circuit layout more flexibility. In addition, using the metal formed in the opening of the key to conduct electricity for signal transmission between layers, in addition to shortening the conductive path, reducing inductance, crosstalk and noise generation, there is no need to implement ink plugging holes and Brushing process to simplify process steps and costs. In addition, the use of the same insulating layer on the surface of the circuit and the plug hole can further improve the bonding strength between the insulating material and the interface between the circuit layer and the through hole of the electric money, and avoid interface peeling.

17448 全懋 .ptd Page 17 1241006 V. Description of the invention (12) Equivalent substitution steps of substrate manufacturing process, equipment or materials, such as replacing layers by hot pressing or changing the number of layers of multilayer packaging substrates, etc. The scope of the invention. The above-mentioned embodiments are merely illustrative for explaining the principle of the present invention and its effects, and are not intended to limit the present invention. Anyone skilled in the art can modify and change the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application mentioned later.

17448 Quan 懋 .ptd Page 18 1241006 Simple illustration of the drawings [Simplified illustration of the drawings]: Figures 1A to 1C are schematic diagrams of the conventional semi-additive semiconductor package substrate manufacturing process; Figures 2A to 2 2C is a schematic diagram of the manufacturing process of a semiconductor package substrate by the conventional circuit plating method, and FIGS. 3A to 3D are schematic diagrams of a manufacturing process of forming a plating via hole of an inner substrate by the conventional ink plugging method; and FIGS. 4A to 4L FIG. Is a schematic cross-sectional view of a method for manufacturing an interlayer conductive structure of a semiconductor package substrate of the present invention. 10.20 Core circuit board 11.21 Insulating layer 1 1 0, 2 1 0 Opening, 12.22 Inner circuit layer 13, 23 Seed layer 14.24 Resistive layer 15.25 Patterned circuit layer 3 0 0, 4 0 0 Insulating layer 3 0 2 Through hole 3 0 2a Plating vias 3 0 3 Inner circuit layer 31 Filler 40 Inner substrate 401 Metal thin layer

17448 懋 .ptd page 19 1241006

Brief description of the drawing 402 First opening 4 0 2a Plating vias 403 Conductive metal layer 4 0 3a Inner circuit layer 41 Insulating layer 410 Second opening 411 Conductive film 412 Plating resist layer 42 First increasing circuit layer 42a Plating metal Layer 43 Insulation layer 430 Blind hole 4 3 0a Conductive blind hole 44 Second build-up circuit layer 45 Solder resist layer 17448 Full 懋 .ptd Page 20

Claims (1)

1241006 VI. Application for Patent Scope 1. A method for manufacturing an interlayer conductive structure of a semiconductor package substrate, including providing an inner substrate, wherein the inner substrate is formed with a plurality of plated through holes penetrating through its surface, and an inner layer circuit is formed on the surface of the inner substrate Forming an insulating layer on the inner substrate and in the plated through hole, and the insulating layer corresponding to the plated through hole is formed with a through opening smaller in size than the plated through hole; and on the insulating layer and the A patterned metal layer is formed in the opening. 2. The method for manufacturing an interlayer conductive structure of a semiconductor package substrate according to item 1 of the patent application scope, wherein the inner substrate includes a multilayer board structure composed of an insulating core layer and at least one circuit pattern formed on the surface of the insulating core layer. . 3. For example, a method for manufacturing an interlayer conductive structure of a semiconductor package substrate according to item 1 of the scope of patent application, wherein the insulating layer is ABF (A ji η 〇m 〇t 〇Build-up Film) 0 4. The method for manufacturing an interlayer conductive structure of a semiconductor package substrate according to the item, wherein the opening is formed by mechanical drilling technology. 5. For example, the method for manufacturing an interlayer conductive structure of a semiconductor package substrate according to the scope of the patent application, wherein the patterned metal layer on the insulating layer and in the opening can be formed on the insulating layer and the surface of the opening. A conductive layer and a patterned plating resist layer are successively formed, and then formed by electroplating. 6. The interlayer conductive junction of the semiconductor package substrate such as the scope of patent application No. 1 17448 Quan 懋 .ptd Page 21 1241006 VI. Patent application method, in which an insulating layer and a patterned metal layer can be repeatedly stacked on the patterned metal layer to obtain a semiconductor package substrate with a multilayer circuit. 7. An interlayer conductive structure of a semiconductor package substrate, comprising: an inner layer substrate on which an inner circuit layer and a plurality of plated vias penetrating through the inner substrate are formed; an insulating layer forming the surface of the inner circuit layer and the A through hole having a size smaller than the plated through hole is formed in the plated through hole corresponding to the electric mine through hole; and a patterned metal layer is formed on the surface of the insulating layer and the hole. 8. The interlayer conductive structure of the semiconductor package substrate according to item 7 of the patent application scope, wherein the inner layer substrate comprises a multi-layer board structure composed of an insulating core layer and at least one circuit pattern formed on the surface of the insulating core layer. 9. The interlayer conductive structure of the semiconductor package substrate according to item 7 of the patent application scope, wherein the insulating layer is A B F (A j i η 〇 m 〇 t ο B u i 1 d-u p Film). 10. The interlayer conductive structure of a semiconductor package substrate according to item 7 of the scope of patent application, wherein the opening is formed by mechanical drilling technology. 1 1. If the interlayer conductive structure of the semiconductor package substrate according to item 7 of the patent application scope, wherein the patterned metal layer can be repeatedly stacked with an insulating layer and a patterned metal layer, a semiconductor package substrate with a multilayer circuit is fabricated. 17448 懋 .ptd Page 22