201023319 六、發明說明： 【發明所屬之技術領域】 尤指一種適用 本發明係關於一種封裝基板及其製法， 於增加佈線密集度及有利於细線路設計之封裝基板及其製 法。 ' 【先前技術】 • 隨著電子產業的蓬勃發展，電子產品亦逐漸進入多功 能、高性能的研發方向。為滿足半導體封裝件高積集度 10 (Integrati〇n)以及微型化（Miniaturization)的封裝要求，提供 給多數主被動元件及線路連接用之電路板，亦逐漸由單層 板演變成多層板，以使在有限的空間下，藉由層間連接技 術（Interlayer connection)而擴大電路板上可利用的佈線面 積，且能配合高電子密度之積體電路（Integrated circu⑴需 15 求。 泰在封裝基板的製作方法中，一般習知載板之製程係由 一核心基板開始，經過鑽孔、鍍金屬、塞孔、線路成型等 製程元成内層結構，再經由線路增層製程完成多層載板， 其中’傳統設計一般係將導電盲孔設置於導電通孔旁，請 20參見圖1 ’係為習知導電盲孔設置於導電通孔旁之封裝基板 剖7JT圖。 如圖1所示’該封裝基板係由一載板10經由鑽孔、鍵金 屬、線路成型等製程完成内層結構後，再經由線路增層製 程形成線路增層結構30。更詳言之，載板10形成貫通第一 4 201023319 5 ❹ 10 15 ❹ 20 表面10a與第二表面i〇b之導電通孔11，，且載板1〇之第一表 面10a及第二表面1〇上分別形成第一線路層21a及第二線路 層21b’其中，第一線路層21a與第二線路層21b係藉由該導 電通孔11電性連接，而第一線路層2ia與第二線路層2ib耳 有複數電性連接墊22a，22b，係設於該導電通孔π，旁之第一 表面10a及第二表面i〇b上。爾後’藉由線路增層製程，即 可形成包括有介電層31、線路層32及複數導電盲孔33之線 路增層結構30於内層結構兩側表面，其中，如圖1所示，導 電盲孔33係設置於導電通孔丨丨，旁之電性連接墊22a，22b上。 於上述導電盲孔設置於導電通孔旁之封裝基板中，由 於導電通孔旁之電性連接墊佔用部份載板表面，故造成於 封裝基板空間内線路佈局之靈活度受到限制，且不利於高 線路密集度之發展趨勢。據此，為增加佈線密集度及靈活 度，將導電盲孔設置於導電通孔上（Via 〇η ρτΗ，ν〇ρτΗ) 之設計便應運而生。 请參見圖2Α至圖2F，係為習知導電盲孔設置於導電通 孔上（Via〇nPTH，VOPTH)之封裝基板製程示意圖。首先， 如圖2A所示，提供一載板1〇，其具有第一表面1〇a及相對之 第二表面i〇b’且形成貫通第一表面1〇a與第二表面l〇b之通 孔11，其中，第一表面1〇a、第二表面1〇b及該通孔丨丨之内 壁表面形成第一金屬層12，而該通孔丨丨與其内壁表面之第 一金屬層12構成為一導電通孔u，，且該導電通孔u，内填充 有一填充材料13。接著，如圖2B所示，移除第一表面10a 及第二表面H)b上之部份第一金屬層12，以降低第一金屬層 5 201023319 12之厚度；隨後，再移除填充材料13高於第一金屬層η之 部份，以使填充材料13之兩端與第一金屬層12齊平，如圖 2C所示。之後，如圖2D所示，形成一導電層2〇1於第一金 屬層12上，再施加一阻層6〇於導電層2〇1上，並經由曝光及 5顯影方式，於阻層60中形成開口區61 ;爾後，藉由電鍍方 式，形成一第二金屬層層2〇2於開口區61中。最後，依序移 除阻層60及其覆蓋之導電層2〇1與第一金屬層12，以分別形 成第一線路層21 a及第二線路層21b於载板1〇之第一表面 ® l〇a與第二表面i〇b，俾完成内層結構，如圖2E所示，第— 10 線路層21a及第二線路層21b具有複數電性連接墊22a，22b， 係为別δ又於該導電通孔11 ’之兩端。爾後，便可藉由線路增 層製程’形成包括有介電層31、線路層32及複數導電盲孔 33之線路增層結構30於内層結構兩側表面，其中，如圖2F 所示’導電盲孔33係設置於導電通孔U，上（Via 〇n PTH)。 15 藉此’由於該封裝基板之電性連接墊係設置於導電通孔之 兩端’其未佔用載板表面，因而可提高線路佈局之靈活度 φ 及密集度。 於上述封裝基板中，雖然導電盲孔設計於導電通孔上 (Via on PTH)可有效增加線路佈局之靈活度及密集度，但為 20 符合细線路之需求，線路厚度亦隨著線路寬度縮小而減 薄’電性連接墊22a,22b因為厚度較薄而機械強度不足，導 致其與填充材料13接合處可靠度不佳、容易發生分層 (delamination)現象，而不利於细線路之設計。據此，如何 改善習知導電盲孔設置於導電通孔上（Via on PTH)應用於 6 201023319201023319 VI. Description of the Invention: [Technical Field of the Invention] In particular, the present invention relates to a package substrate and a method of manufacturing the same, which are used to increase the wiring density and facilitate the thin circuit design of the package substrate and the method thereof. '[Prior Art] • With the booming electronics industry, electronic products are gradually entering the direction of multi-functional, high-performance research and development. In order to meet the packaging requirements of semiconductor package high integration 10 and miniaturization, the circuit boards for most active and passive components and circuit connections are gradually evolved from single-layer boards to multi-layer boards. In order to expand the available wiring area on the board by the interlayer connection technology in a limited space, and to integrate the high electron density integrated circuit (Integrated circu (1) requires 15 In the manufacturing method, generally, the process of the carrier is started from a core substrate, and the process elements such as drilling, metal plating, plugging, and line forming are formed into an inner layer structure, and then the multilayer carrier is completed through a line build-up process, wherein In the conventional design, the conductive blind hole is generally disposed beside the conductive via hole. Please refer to FIG. 1 for a 7JT diagram of a package substrate which is a conventional conductive via hole disposed beside the conductive via hole. After the inner layer structure is completed by a carrier 10 through drilling, key metal, line forming, etc., the line build-up structure 30 is formed through the line build-up process. In other words, the carrier 10 forms a conductive via 11 penetrating through the first 4 201023319 5 ❹ 10 15 ❹ 20 surface 10a and the second surface i〇b, and the first surface 10a and the second surface 1 of the carrier 1〇 A first circuit layer 21a and a second circuit layer 21b are formed on the first circuit layer 21a and the second circuit layer 21b, wherein the first circuit layer 21a and the second circuit layer 21b are electrically connected by the conductive via hole 11, and the first circuit layer 2ia and the second circuit are electrically connected. The layer 2ib has a plurality of electrical connection pads 22a, 22b disposed on the first conductive surface π, adjacent to the first surface 10a and the second surface i〇b, and then formed by the line build-up process. The line build-up structure 30 having the dielectric layer 31, the circuit layer 32 and the plurality of conductive blind holes 33 is on both sides of the inner layer structure, wherein, as shown in FIG. 1, the conductive blind holes 33 are disposed on the conductive via holes. The electrical connection pads 22a, 22b are disposed in the package substrate adjacent to the conductive vias, and the electrical connection pads beside the conductive vias occupy part of the surface of the carrier, thereby causing the package substrate to be spaced. The flexibility of line layout is limited and is not conducive to the development of high line density Accordingly, in order to increase the wiring density and flexibility, the design of the conductive blind vias on the conductive vias (Via 〇η ρτΗ, ν〇ρτΗ) has emerged. See Figure 2Α to Figure 2F for A schematic diagram of a package substrate process in which a conductive via is disposed on a conductive via (Via〇nPTH, VOPTH). First, as shown in FIG. 2A, a carrier 1 is provided, which has a first surface 1〇a and a relative surface thereof. a second surface i〇b′ and forming a through hole 11 penetrating the first surface 1〇a and the second surface 10b, wherein the first surface 1〇a, the second surface 1〇b, and the through hole The first metal layer 12 is formed on the inner wall surface, and the first metal layer 12 of the inner wall surface and the inner wall surface thereof is formed as a conductive through hole u, and the conductive through hole u is filled with a filling material 13. Next, as shown in FIG. 2B, a portion of the first metal layer 12 on the first surface 10a and the second surface H)b is removed to reduce the thickness of the first metal layer 5 201023319 12; then, the filling material is removed. 13 is higher than a portion of the first metal layer η such that both ends of the filling material 13 are flush with the first metal layer 12, as shown in FIG. 2C. Then, as shown in FIG. 2D, a conductive layer 2〇1 is formed on the first metal layer 12, and a resist layer 6 is applied on the conductive layer 2〇1, and exposed to the resist layer 60 via exposure and 5 development. An open region 61 is formed in the middle; then, a second metal layer 2〇2 is formed in the open region 61 by electroplating. Finally, the resist layer 60 and the conductive layer 2〇1 and the first metal layer 12 are sequentially removed to form the first circuit layer 21 a and the second circuit layer 21 b on the first surface of the carrier 1 L〇a and the second surface i〇b, 俾 complete the inner layer structure, as shown in FIG. 2E, the -10-th circuit layer 21a and the second circuit layer 21b have a plurality of electrical connection pads 22a, 22b, which are different from δ and Both ends of the conductive via 11 '. Thereafter, a line build-up structure 30 including a dielectric layer 31, a circuit layer 32, and a plurality of conductive blind vias 33 can be formed on both sides of the inner layer structure by a line build-up process, wherein, as shown in FIG. 2F, 'conducting The blind via 33 is disposed on the conductive via U, (Via 〇n PTH). 15 because the electrical connection pads of the package substrate are disposed at both ends of the conductive vias, which do not occupy the surface of the carrier, thereby improving the flexibility and density of the layout. In the above package substrate, although the conductive blind hole is designed on the conductive via (Via on PTH), the flexibility and density of the line layout can be effectively increased, but the line thickness is also reduced according to the requirement of the fine line. However, the thinned electrical connection pads 22a, 22b have insufficient mechanical strength due to their thin thickness, resulting in poor reliability and delamination of the joints with the filler material 13, which is disadvantageous for the design of the fine lines. Accordingly, how to improve the conventional conductive blind vias on the conductive vias (Via on PTH) is applied to 6 201023319
细線路、高佈線密度所面臨可靠度不佳之問題 亟欲解決之課題。 【發明内容】 5 本發明之主要目的係在提供—種封裝基板，其 電盲孔設置於導電通孔上（ViaQnPTH)之設計，以增加線 佈局之靈活度及密集度，應用於细線路設計時，可改善 知封裝基板關械強度*足所導致之分層現象，: 產品可靠度。 捉升 1〇 為達成上述目&，本發明提供-種封裝基板，包括： 一載板，係具有第一表面及袓對之第二表面；一第—線路 層及一第二線路層，係分別設於載板之第一表面與第二表 面；以及-導電通孔，係貫通載板且電性連接第一線路層 與第二線路層，其中導電通孔係填充有一填充材料，且其 15兩端各與第一表面及第二表面具有一落差，而與部份導電 通孔之内壁表面形成第一凹陷與第二凹陷；其中，第一線 ►路層及第二線路層具有複數電性連接墊，係分別設於導電 通孔之兩端，且填入於第一凹陷及第二凹陷，以使該些電 性連接墊厚度大於第一表面及第二表面上之第一線路層及 20第二線路層之厚度。在此，本發明封裝基板中之導電通孔 可由貝通s亥載板之通孔及其内壁表面上之一第一金屬層所 構成。 據此，於本發明所提供之封裝基板中，由於導電通孔 兩端之電性連接墊厚度係大於線路層厚度，故應用於细線 201023319 路設計時，導電通孔兩端之電性連接墊仍具有足夠之厚 度，進而可改善習知封裝基板因機械強度不足所導致之分 層（delamination)現象，俾能提升產品可靠度及應用性。 此外’本發明更提供一種製作上述封褒練之方法， 5包m載板’其具有第—表面及相對之第二表面，且 形成一貫通第一表面與第二表面之通孔，於第一表面、第 二表面及通孔之内壁表面形成一第一金屬層，其中，通孔 與其内壁表面之第-金屬層成為一導電通孔，並於導電通 孔内填充-填充材料；移除載板之第一表面與第二表面上 10之部份第-金屬層；移除部份填充材料，以使填充材料之 兩端各與第一表面及第二表面具有一落差，而與部份導電 通孔之内壁表面形成第一凹陷與第二凹陷；形成一導電層 於第一金屬層及填充材料表面；形成一具有開口區之阻層 於導電層之表面，並於該阻層之開口區中形成一第二金屬 15層；以及移除該阻層、該阻層所覆蓋之導電層及第一金屬 層，以分別形成一第一線路層及一第二線路層於載板之第 ，一表面與第二表面，其中，第一線路層及第二線路層具有 複數電性連接墊，係分別設於導電通孔之兩端，且填入於 第一凹陷及第二凹陷，以使該些電性連接墊厚度大於第一 20表面及第二表面上之第一線路層及第二線路層之厚度。 於本發明之封裝基板及其製法中，該載板可為一絕緣 板、銅箔基板、兩層或多層電路板，而該填充材料可為樹 脂。 8 201023319 於本發明之封裝基板及其製法中，該填充材料可藉由 雷射燒融（1· ablatiGn)等方式，使其兩端分別與第 及第二表面形成—落差’且不傷害導電通孔内之第 層。 苟 5 【實施方式】 以下係藉由特定的具體實施例說明本發明之實施方 10 15 式’熟習此技藝之人士可由本說明書所揭示之内容輕易地 了解本發明之其他優點與功效。本發明亦可藉由其他不同 的具體實施例加以施行或應用，本說明書中的各項細節亦 可基於不_點與制，在不,_本發明之精神下 種修#與變更。 本發明之實施例中該等圖式均為簡化之示意圖。惟該 等圖式僅顯示與本發明有關之元件，其所顯示之元件非為ζ 實際實施時之態樣，其實際實施時之元件數目、形狀等比 例為-選擇性之設計’且其元件佈局型態可能更複雜。 請參考圖3Α至圖3G，係本實施例之封裝基板製程示意 圖。首先，如圖3Α所示，提供一載板40,其具有第一表面 40a及相對之第二表面4〇b，且形成貫通第一表面4〇a與第二 表面40b之通孔41，其中，第一表面4〇a、第二表面斗⑽及通 孔41之内壁表面形成第一金屬層42，而該通孔斜與其内壁 表面之第一金屬層42成為一導電通孔41，，且導電通孔41， 内填充一填充材料43。在此，該載板40可為一絕緣板、銅 20 201023319 箔基板、兩層或多層電路板。於本實施例中，該載板40為 一絕緣板，而填充材料43為一樹脂。 接著，如圖3B所示，移除載板40之第一表面40a與第二 表面40b上之部份第一金屬層42,以降低第一金屬層42之厚 5 度；隨後，如圖3C所示，藉由雷射燒融等方式，移除部份 填充材料43，以使填充材料43之兩端43a,43b各與第一表面 40a及第二表面40b具有一落差e，而與部份導電通孔41’之内 壁表面42a及42b形成第一凹陷與第二凹陷。 _ 爾後，如圖3D所示，利用無電電鍍形成一導電層501 10 於第一金屬層42及填充材料43表面；隨後，施加一阻層60 於導電層501上，並經由曝光及顯影方式，於阻層60中形成 開口區61。 接著，如圖3E所示，藉由電鍍方式，形成一第二金屬 層502於開口區61中。據此，由於導電通孔41’内新增有第 15 二金屬層502,故可增加其機械強度，避免分層現象之發生。 最後，依序移除阻層60及其覆蓋之導電層501與第一金 ❹ 屬層42，以分別形成第一線路層51a及第二線路層51b於載 板40之第一表面40a與第二表面40b，如圖3F所示，第一線 路層51a及第二線路層51b具有複數電性連接墊52a,52b，係 20 分別設於導電通孔41’之兩端，且填入於第一凹陷及第二凹 陷，以使該些電性連接墊52a，52b厚度大於第一表面40a及第 二表面40b上之第一線路層51a及第二線路層51b之厚度。 據此，如圖3F所示，本實施例所提供之封裝基板係包 括：一載板40,係具有第一表面40a及相對之第二表面40b ; 201023319 一第一線路層51a及一第二線路層51b，係分別設於載板4〇 之第一表面40a與第二表面40b ;以及一導電通孔41，，係貫 通該載板40且電性連接第一線路層51a與第二線路層5化， 其中導電通孔41，係填充有一填充材料43，且其兩端43&，43匕 5 各與第表面4〇a及第一表面40b具有一落差，而與部份導 電通孔41，之内壁表面42a，42b形成第一凹陷與第二凹陷；其 中，第一線路層51a及第二線路層51b具有複數電性連接墊 52a，52b，係分別設於導電通孔41，之兩端，且填入於第一凹 陷及第二凹陷，以使該些電性連接墊52a,52b厚度大於第一 10表面4〇a及第二表面401)上之第一線路層51a及第二線路層 51b之厚度。 爾後，本實施例所提供之封裝基板可應用於導電盲孔 設置於導電通孔上（ViaonPTH)之設計，如圖3G所示，藉由 線路增層製程，可進一步形成包括有介電層71、線路層372 15及複數導電盲孔73之線路增層結構7〇於第一線路層5u及 第二線路層51b表面，其中，導電盲孔73係設置於導電通孔 ❹ 41上(Vla on PTH) ’以提咼線路佈局之靈活度及密集度， 其中，由於導電通孔41’兩端之電性連接墊523,5孔厚度係大 於第一線路層51a及第二線路層51b厚度，故應用於细線路 20 δ又计時’仍可使導電通孔41’兩端之電性連接墊52a，52b具有 足夠之厚度。據此，本發明所提供之封裝基板可增加導電 通孔兩端電性連接塾之機械強度，降低分層現象發生之可 能’以改善習知封裝基板不利细線路設計之缺點，進而增 加產品之可靠度。 曰 201023319 上述實施例僅係為了方便說明而舉例而已，本發a月$ 主張之權利範圍自應以申請專利範圍所述為準，而非僅限 於上述實施例。 5 【圖式簡單說明】 圖1係習知導電盲孔設置於導電通孔旁之封裝基板剖示圖。 ❹ 10 圖2Α至圖2F係習知導電盲孔設置於導電通孔上之封裝基 板製程示意圖。 圖3Α至圖观本發明—較佳實_之封裝基板製法流程 示意圖。 【主要元件符號說明】 10, 40 載板 10a, 40a 第一表面 10b, 40b 第二表面 11, 41 通孔 11，，41’ 導電通孔 12, 42 第一金屬層 13, 43 填充材料 201, 501 導電層 202, 502 第二金屬層 21a, 51a 第一線路層 21b, 51b 第一線路層 22a, 22b, 52a, 52b 電性連接塾 12 201023319 30, 70 線路增層結構 31，71 介電層 32, 72 線路層 33, 73 導電盲孔 42a, 42b 導電通孔之内壁表面 43a, 43b 填充材料之兩端 60 阻層 61 開口區 e 落差 13The problem of poor reliability due to thin wiring and high wiring density is a problem to be solved. SUMMARY OF THE INVENTION The main purpose of the present invention is to provide a package substrate with an electric blind hole disposed on a conductive via (ViaQnPTH) to increase the flexibility and density of the line layout, and to apply to a fine circuit design. When it is known, the delamination caused by the mechanical strength of the package substrate can be improved: Product reliability. In order to achieve the above objectives, the present invention provides a package substrate comprising: a carrier having a first surface and a second surface of the pair; a first circuit layer and a second circuit layer; The first and second surfaces of the carrier are respectively disposed; and the conductive vias are through the carrier and electrically connected to the first circuit layer and the second circuit layer, wherein the conductive vias are filled with a filling material, and Each of the two ends of the 15 has a drop with the first surface and the second surface, and forms a first recess and a second recess with the inner wall surface of the partial conductive via; wherein the first line and the second layer have a plurality of electrical connection pads respectively disposed at two ends of the conductive vias and filled in the first recess and the second recess such that the thickness of the electrical connection pads is greater than the first on the first surface and the second surface The thickness of the circuit layer and the 20 second circuit layer. Here, the conductive via in the package substrate of the present invention may be formed by a through hole of a Beton s-borne carrier and a first metal layer on the surface of the inner wall. Accordingly, in the package substrate provided by the present invention, since the thickness of the electrical connection pads at both ends of the conductive via is greater than the thickness of the circuit layer, the electrical connection between the two ends of the conductive via is applied to the design of the thin line 201023319. The pad still has sufficient thickness, which can improve the delamination phenomenon caused by insufficient mechanical strength of the conventional package substrate, and can improve product reliability and applicability. In addition, the present invention further provides a method for manufacturing the above-mentioned sealing and cultivating, wherein a 5-package m-board has a first surface and an opposite second surface, and a through hole penetrating the first surface and the second surface is formed. a surface of the inner wall of the surface, the second surface and the through hole forms a first metal layer, wherein the through hole and the first metal layer of the inner wall surface form a conductive through hole, and the filling material is filled with a filling material; a first metal layer on the first surface and the second surface of the carrier; a portion of the filler material is removed such that both ends of the filler material have a drop with the first surface and the second surface, and Forming a first recess and a second recess on the inner wall surface of the conductive via; forming a conductive layer on the surface of the first metal layer and the filling material; forming a resist layer having an open region on the surface of the conductive layer, and forming a resist layer Forming a second metal layer 15 in the opening region; and removing the resist layer, the conductive layer covered by the resist layer, and the first metal layer to form a first circuit layer and a second circuit layer respectively on the carrier layer First, a surface and a second surface, The first circuit layer and the second circuit layer have a plurality of electrical connection pads respectively disposed at two ends of the conductive vias and filled in the first recesses and the second recesses to make the thickness of the electrical connection pads Greater than the thickness of the first circuit layer and the second circuit layer on the first 20 surface and the second surface. In the package substrate of the present invention and the method of manufacturing the same, the carrier may be an insulating plate, a copper foil substrate, two or more circuit boards, and the filling material may be a resin. 8 201023319 In the package substrate of the present invention and the method for manufacturing the same, the filling material can be formed by laser ablation (1· ablatiGn), etc., so that both ends thereof form a drop-off with the second surface and do not damage the conductive The first layer in the through hole. 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The present invention may also be embodied or applied by other different embodiments, and the details in the present specification may also be based on a non-point and system. The drawings in the embodiments of the present invention are simplified schematic diagrams. However, the drawings only show the components related to the present invention, and the components shown therein are not in the actual implementation, and the actual number of components in the actual implementation, the ratio of the components is a selective design and its components The layout type can be more complicated. Please refer to FIG. 3A to FIG. 3G, which are schematic diagrams of the process of the package substrate of the embodiment. First, as shown in FIG. 3A, a carrier 40 is provided having a first surface 40a and an opposite second surface 4〇b, and forming a through hole 41 penetrating the first surface 4a and the second surface 40b, wherein a first metal layer 42 is formed on the inner surface of the first surface 4a, the second surface hopper (10), and the through hole 41, and the through hole is inclined to form a conductive through hole 41 with the first metal layer 42 of the inner wall surface thereof, and The conductive via 41 is filled with a filling material 43. Here, the carrier 40 can be an insulating plate, a copper 20 201023319 foil substrate, a two-layer or multi-layer circuit board. In this embodiment, the carrier 40 is an insulating plate, and the filling material 43 is a resin. Next, as shown in FIG. 3B, the first surface 40a of the carrier 40 and a portion of the first metal layer 42 on the second surface 40b are removed to reduce the thickness of the first metal layer 42 by 5 degrees; subsequently, as shown in FIG. 3C. As shown, the portion of the filling material 43 is removed by laser burning or the like so that the ends 43a, 43b of the filling material 43 each have a drop e with the first surface 40a and the second surface 40b, and The inner wall surfaces 42a and 42b of the conductive via 41' form a first recess and a second recess. Then, as shown in FIG. 3D, a conductive layer 501 10 is formed on the surface of the first metal layer 42 and the filling material 43 by electroless plating; subsequently, a resist layer 60 is applied on the conductive layer 501, and exposed and developed, An open region 61 is formed in the resist layer 60. Next, as shown in Fig. 3E, a second metal layer 502 is formed in the opening region 61 by electroplating. Accordingly, since the 15th metal layer 502 is newly added in the conductive via 41', the mechanical strength can be increased to avoid delamination. Finally, the resist layer 60 and the conductive layer 501 and the first metal layer 42 are sequentially removed to form the first circuit layer 51a and the second circuit layer 51b on the first surface 40a of the carrier 40, respectively. The second surface 40b, as shown in FIG. 3F, the first circuit layer 51a and the second circuit layer 51b have a plurality of electrical connection pads 52a, 52b, respectively, which are respectively disposed at opposite ends of the conductive via 41' and filled in a recess and a second recess such that the thickness of the electrical connection pads 52a, 52b is greater than the thickness of the first circuit layer 51a and the second circuit layer 51b on the first surface 40a and the second surface 40b. Accordingly, as shown in FIG. 3F, the package substrate provided in this embodiment includes: a carrier 40 having a first surface 40a and an opposite second surface 40b; 201023319 a first circuit layer 51a and a second The circuit layer 51b is respectively disposed on the first surface 40a and the second surface 40b of the carrier 4A; and a conductive via 41 extending through the carrier 40 and electrically connecting the first circuit layer 51a and the second line The layer 5 is formed, wherein the conductive via 41 is filled with a filling material 43, and both ends 43&, 43匕5 have a drop with the first surface 4a and the first surface 40b, and a part of the conductive via 41, the inner wall surfaces 42a, 42b form a first recess and a second recess; wherein the first circuit layer 51a and the second circuit layer 51b have a plurality of electrical connection pads 52a, 52b, respectively disposed in the conductive through holes 41, The two ends are filled in the first recess and the second recess so that the thickness of the electrical connection pads 52a, 52b is greater than the first circuit layer 51a and the first surface of the first 10 surface 4a and the second surface 401) The thickness of the second wiring layer 51b. Then, the package substrate provided in this embodiment can be applied to the design of the conductive via hole disposed on the conductive via (ViaonPTH). As shown in FIG. 3G, the dielectric layer 71 can be further formed by the line build-up process. The line build-up structure 7 of the circuit layer 372 15 and the plurality of conductive blind holes 73 is disposed on the surfaces of the first circuit layer 5u and the second circuit layer 51b, wherein the conductive blind holes 73 are disposed on the conductive vias 41 (Vla on PTH) 'to increase the flexibility and density of the layout of the circuit, wherein the thickness of the 5 holes is greater than the thickness of the first circuit layer 51a and the second circuit layer 51b due to the electrical connection pads 523 at both ends of the conductive via 41' Therefore, it is applied to the thin line 20 δ and the timing 'still allows the electrical connection pads 52a, 52b at both ends of the conductive via 41' to have a sufficient thickness. Accordingly, the package substrate provided by the invention can increase the mechanical strength of the electrical connection between the two ends of the conductive via, and reduce the possibility of delamination occurring to improve the disadvantages of the conventional thin circuit design of the package substrate, thereby increasing the product. Reliability.曰 201023319 The above embodiments are merely examples for convenience of explanation, and the scope of claims of the present invention is based on the scope of the patent application, and is not limited to the above embodiments. 5 [Simple Description of the Drawings] FIG. 1 is a cross-sectional view of a package substrate in which a conductive blind via is disposed beside a conductive via. ❹ 10 Fig. 2Α to Fig. 2F are schematic diagrams showing the process of a package substrate in which a conductive via is disposed on a conductive via. Fig. 3 is a schematic view showing the process flow of the package substrate of the present invention. [Description of main component symbols] 10, 40 carrier plates 10a, 40a first surface 10b, 40b second surface 11, 41 through holes 11, 41' conductive vias 12, 42 first metal layer 13, 43 filling material 201, 501 conductive layer 202, 502 second metal layer 21a, 51a first circuit layer 21b, 51b first circuit layer 22a, 22b, 52a, 52b electrical connection 塾12 201023319 30, 70 line build-up structure 31, 71 dielectric layer 32, 72 circuit layer 33, 73 conductive blind holes 42a, 42b inner wall surface 43a of conductive vias, 43b both ends of the filling material 60 resist layer 61 open area e drop 13