JP2018101776A - Printed circuit board and package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a printed circuit board.SOLUTION: A printed circuit board according to one aspect of the present invention includes: an insulation part; an outer conductor pattern layer including a first conductor pattern and a second conductor pattern each embedded in one surface of the insulation part; a first surface treatment layer which is formed on the first conductor pattern so as to protrude from the one surface of the insulation part; a seed layer which is formed between the first conductor pattern and the first surface treatment layer so as to protrude from the one surface of the insulation part; a second surface treatment layer which is formed on the second conductor pattern and contains an organic material; and recess parts which are formed on both sides of the first conductor pattern and/or seed layer.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a printed circuit board and a package.

  Usually, a printed circuit board is produced by sequentially laminating a plurality of build-up layers on a core substrate. In this way, the production of a printed circuit board by sequentially laminating build-up layers is also referred to as a sequential laminating method.

  When manufacturing a printed circuit board by a sequential lamination method, the number of lamination processes increases as the number of layers of the printed circuit board increases. Such a laminating process also applies heat to the already laminated parts, causing unnecessary and unpredictable deformation. As the number of such deformations increases, the alignment between layers becomes more difficult.

  For this reason, a collective laminating method has been developed in which a plurality of unit substrates are simultaneously laminated at the same time to produce a printed circuit board after the build-up layers are separately produced on the unit substrates.

Korean Published Patent No. 10-2011-0066044

  According to the embodiment of the present invention, a printed circuit board and a package capable of reducing a loss of a conductor pattern when a surface treatment layer is formed are provided.

It is a figure which shows the printed circuit board which concerns on one Example of this invention. It is a figure which shows the package which concerns on one Example of this invention. It is a figure which shows 1 process of the manufacturing method of the printed circuit board which concerns on one Example of this invention. FIG. 4 is a diagram showing a step subsequent to FIG. 3. It is a figure which shows the next process of FIG. It is a figure which shows the next process of FIG. It is a figure which shows the next process of FIG. It is a figure which shows the next process of FIG. It is a figure which shows the next process of FIG. FIG. 10 is a diagram showing a step subsequent to that in FIG. 9. FIG. 11 is a diagram showing a step subsequent to FIG. 10. FIG. 12 is a diagram showing a step subsequent to FIG. 11. FIG. 13 is a diagram showing a step subsequent to FIG. 12. It is a figure which shows the next process of FIG.

  The terms used in the present application are merely used to describe particular embodiments, and are not intended to limit the present invention. A singular expression includes the plural expression unless it is expressly stated in the sentence.

  In this application, terms such as “comprising” or “having” designate the presence of features, numbers, steps, operations, components, parts or combinations thereof as described in the specification, It should be understood that the existence or additional possibilities of one or more other features or numbers, steps, actions, components, parts or combinations thereof are not excluded in advance.

  Further, throughout the specification, “on” means located above or below the target portion, and does not necessarily mean located above the gravity direction.

In addition, the term “coupled” does not mean that in the contact relationship between the components, the components are physically directly in contact with each other, and other configurations are interposed between the components. It is used as a concept encompassing even when the components are in contact with other components.
The size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, and the present invention is not necessarily limited thereto.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a printed circuit board and a package according to the present invention will be described in detail with reference to the accompanying drawings, and the same or corresponding components will be denoted by the same reference numerals in the description with reference to the accompanying drawings. In addition, a duplicate description regarding this will be omitted.

(Printed circuit boards and packages)
(Printed circuit board and)
FIG. 1 is a diagram illustrating a printed circuit board according to an embodiment of the present invention.

  Referring to FIG. 1, a printed circuit board 1000 according to an embodiment of the present invention includes an insulating part 20, outer conductor pattern layers 110 and 610, a first surface treatment layer 40, a seed layer 30, and a second surface. The processing layer 50 and the recess R may be included, and the inner conductor pattern layers 210, 310, 410, 510 and the via 60 may be further included.

The insulating unit 20 is formed by stacking a plurality of insulating layers 120, 220, 320, 420, 520, 620.
The insulating unit 20 electrically insulates the first to sixth conductor pattern layers 120, 210, 310, 410, 510, and 610 from each other.

  In the following description, when the plurality of insulating layers 120, 220, 320, 420, 520, and 620 are required to be distinguished from each other, the first insulating layers are respectively formed from the top to the bottom with reference to FIG. These layers are referred to as a layer 120, a second insulating layer 220, a third insulating layer 320, a fourth insulating layer 420, a fifth insulating layer 520, and a sixth insulating layer 620. However, when it is not necessary to distinguish between them, they are commonly referred to as insulating layers 120, 220, 320, 420, 520, and 620.

  Further, in the description of the plurality of conductor pattern layers 110, 210, 310, 410, 510, and 610, when it is necessary to distinguish between them, the first conductors are respectively formed from the top to the bottom with reference to FIG. These are referred to as a pattern layer 110, a second conductor pattern layer 210, a third conductor pattern layer 310, a fourth conductor pattern layer 410, a fifth conductor pattern layer 510, and a sixth conductor pattern layer 610. However, when it is not necessary to distinguish between the first conductor pattern layer to the sixth conductor pattern layer 110, 210, 310, 410, 510, 610, or the conductor pattern layers 110, 210, 310, 410, 510, This is commonly referred to as 610.

  On the other hand, in FIG. 1, each of the insulating layers 120, 220, 320, 420, 520, 620 and the conductor pattern layers 110, 210, 310, 410, 510, 610 is formed in six layers. It will never be done. As an example, each of the insulating layer and the conductive pattern layer may be formed in four layers.

  The plurality of conductor pattern layers 110, 210, 310, 410, 510, and 610 are, if necessary, outer layer conductor pattern layers 110 and 610 corresponding to the outermost conductor pattern layer of the printed circuit board 1000 according to the present embodiment. And the inner conductor pattern layers 210, 310, 410, 510 formed between the outer conductor pattern layers 110, 610.

  In the case of FIG. 1, the first conductor pattern layer 110 and the sixth conductor pattern layer 610 are outer conductor pattern layers, and the second conductor pattern layer to the fifth conductor pattern layers 210, 310, 410, 510 are inner conductor pattern layers. . However, in the following description, for convenience of description, the outer layer conductor pattern means the first conductor pattern layer 110 unless a separate drawing symbol is shown.

  Each of the insulating layers 120, 220, 320, 420, 520, 620, together with any one of the conductor pattern layers 120, 210, 310, 410, 510, 610, unit substrates 100, 200, 300, which will be described later. 400, 500, and 600. That is, the first insulating layer 12 is included in the first unit substrate 100 described later together with the first conductor pattern layer 110. The first to sixth unit substrates 100, 200, 300, 400, 500, and 600 are sequentially stacked at the same time after being formed separately from each other, unlike the sequential stacking method.

  Each of the insulating layers 120, 220, 320, 420, 520, and 620 includes a photocurable resin, and may be a photosensitive insulating layer made of a substance that reacts with light.

  Hereinafter, only the first insulating layer 120 among the insulating layers 120, 220, 320, 420, 520, 620 will be described for convenience of explanation. The first insulating layer 120 is referred to as a photosensitive insulating layer. However, in this explanation, at least one of the first to sixth insulating layers 120, 220, 320, 420, 520, 620 is a non-photosensitive material such as a normal prepreg or ABF (Ajinomoto Build-up Film). It is not to exclude the formation of a conductive insulating material.

  The degree of cure of the photosensitive insulating layer 120 can be adjusted by light. However, since the photosensitive insulating layer 120 is also thermosetting, the degree of curing can be adjusted by heat.

  Since the photosensitive insulating layer 120 can be subjected to a photolithography process, it is advantageous for realizing a fine hole as compared with the case of processing a hole in a non-photosensitive insulating layer such as a prepreg. Since a plurality of holes can be formed simultaneously by only one photolithography process, the hole forming process can be simplified.

  In addition, the photosensitive insulating layer 120 can be easily formed into various shapes by a photolithography process. For example, the shape of the vertical cross section of the hole may have an inverted trapezoidal shape, a regular trapezoidal shape, a rectangular shape, or the like.

  The photosensitive insulating layer 120 may be a positive type or a negative type. In the case of the positive type photosensitive insulating layer 120, the exposed portion of the photopolymer polymer bond is broken. Thereafter, when the development process is performed, the portion where the photopolymer polymer bond is broken is removed by receiving light. In the case of the negative-type photosensitive insulating layer 120, the exposed portion undergoes a photopolymerization reaction to change from a single structure to a three-dimensional chain structure having a chain structure. When the development process is performed, the portion not receiving light is removed. Is done.

  The photosensitive insulating layer 120 may be one in which an inorganic filler is contained in a photocurable resin. The inorganic filler improves the rigidity of the photosensitive insulating layer 120 and reduces the thermal expansion coefficient.

As inorganic fillers, silica (SiO ₂ ), alumina (Al ₂ O ₃ ), silicon carbide (SiC), barium sulfate (BaSO ₄ ), talc, clay, mica powder, aluminum hydroxide (AlOH ₃ ), magnesium hydroxide (Mg _(OH) 2), calcium carbonate (CaCO _3), magnesium carbonate (MgCO _3), magnesium oxide (MgO), boron nitride (BN), aluminum borate (alBO _3), barium titanate (BaTiO ₃₎ and At least one selected from the group consisting of calcium zirconate (CaZrO ₃ ) can be used.

  The outer conductor pattern layers 110 and 610 are formed on the outermost insulating layers 120 and 620, respectively. That is, the first conductor pattern layer 110 is formed on the first insulating layer 120, and the sixth conductor pattern layer 61 is formed on the sixth insulating layer 620.

  The outer conductor pattern layers 110 and 610 may include at least one of a signal pattern, a power pattern, a ground pattern, and an external connection terminal, which are conductor patterns of a normal printed circuit board.

  The outer conductor pattern layer 110 includes a first conductor pattern 111 and a second conductor pattern 112 respectively embedded in one surface of the insulating portion 20. Unlike the normal circuit pattern, the first conductor pattern 111 and the second conductor pattern 112 correspond to external connection terminals of the printed circuit board 1000 according to the present embodiment. Specifically, the first conductor pattern 111 is connected to an active element such as a semiconductor die (die, 700 in FIG. 2), and the second conductor pattern 112 is connected to a passive element such as MLCC or another substrate such as a main board. Can be done.

  As shown in FIG. 1, the first conductor pattern 111 includes a mounting pad 111-1 on which a die (die, 700 in FIG. 2) is mounted, and a die (die, die) through a wire (W in FIG. 2). The bonding pad 111-2 is electrically connected to the external connection terminal 700) in FIG. In addition, the first conductor pattern 111 may further include a flip chip bonding pad (not shown) for flip chip bonding.

  A passive element such as MLCC can be electrically connected to the second conductor pattern 112 by SMT (Surface Mounting Technology). As an example, the second conductor pattern may be electrically connected to the MLCC by being coupled to an external electrode of the MLCC.

  The first surface treatment layer 4 is formed on the first conductor pattern 111 and protrudes from one surface of the insulating unit 20. That is, the first surface treatment layer 40 is formed on the first conductor pattern 111 so as to protrude from the upper surface of the first insulating layer 120 based on FIG.

  The first surface treatment layer 40 is formed on the first conductor pattern 111 to facilitate signal transmission and heat transfer between the first conductor pattern 111 and a die (die, 700 in FIG. 2). . Specifically, the first surface treatment layer 40 formed on the mounting pad 111-1 facilitates heat transfer between the die (700 in FIG. 2) and the mounting pad 111-1. The first surface treatment layer 40 formed on the bonding pad 111-2 facilitates signal transmission between the die (die, 700 in FIG. 2) and the bonding pad 111-2. The first surface treatment layer 40 may include a material having excellent electrical conductivity and thermal conductivity. As an example, the first surface treatment layer may include gold (Au).

  The seed layer 30 is formed between the first conductor pattern 111 and the first surface treatment layer 40 and protrudes from one surface of the insulating unit 20. The seed layer (30) can be formed from a copper foil (CF in FIG. 3) of a carrier (C in FIG. 3) described later.

  The first surface treatment layer 40 includes a material having a standard reduction potential higher than the standard reduction potential of the material forming the first conductor pattern 111 and / or the seed layer 30. For example, when the first conductor pattern 111 and the seed layer 30 are formed of copper (Cu), the first surface treatment layer 40 includes gold (Au) having a standard reduction potential higher than the standard reduction potential of copper. be able to.

  The second surface treatment layer 50 is formed on the second conductor pattern 112 and includes an organic substance. That is, the second surface treatment layer 50 can be a normal OSP layer.

  At least a part of the second surface treatment layer 50 is embedded in the insulating unit 20. As will be described later, the second conductor pattern 112 is soft etched before the second surface treatment layer 50 is formed.

  Therefore, the second conductor pattern 112 is recessed from the upper surface of the insulating part 20 of FIG. 1 after the soft etching. Since the second surface treatment layer 50 is formed on the second conductor pattern 112 after the soft etching, as a result, at least a part of the second surface treatment layer 50 is embedded in the insulating portion 20.

  The recess R is formed on both sides of the first conductor pattern 111 and / or the seed layer 30. The recess portion R is formed by soft etching in order to form the second surface treatment layer 50. That is, at the time of soft etching, the first surface treatment layer 40 made of a material having a standard reduction potential higher than the standard reduction potential of the first conductor pattern 111 is already formed on the first conductor pattern 111. Therefore, when soft etching is performed, the recessed portion R is formed by overetching (galvanic corrosion) of the first conductor pattern 111 and / or the seed layer 30.

  The phenomenon of over-etching becomes more prominent on both sides of the first conductor pattern 111 and / or the seed layer 30 that are not covered by the first surface treatment layer 40. However, in the case of the printed circuit board 1000 according to an embodiment of the present invention, since the first conductor pattern 111 is formed in a form embedded in one surface of the insulating portion 20, it is exposed to an etching solution during soft etching. The area of the first conductor pattern 111 can be minimized. Thereby, the overetching phenomenon of the 1st conductor pattern 111 which generate | occur | produces at the time of the soft etching for forming the 2nd surface treatment layer 50 can be minimized.

  The recess portion R formed in the first conductor pattern 111 has a cross-sectional area that decreases from one surface of the insulating portion 20 to the inside of the insulating portion 20. That is, the size of the recess portion R decreases as it goes from one surface of the insulating portion 20 to the inside of the insulating portion 20.

  The inner conductor pattern layers 210, 310, 410, 510 are formed inside the insulating unit 20. That is, each of the internal conductor pattern layers 210, 310, 410, 510 is formed in each of the second insulating layer to the fifth insulating layers 220, 320, 420, 520 and is located inside the insulating unit 20.

  Each of the conductor pattern layers 110, 210, 310, 410, 510, and 610 has excellent electrical characteristics such as copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), and titanium. (Ti), gold (Au), platinum (Pt), or the like can be used.

  The pattern shapes of the conductor pattern layers 110, 210, 310, 410, 510, and 610 may all be the same, or may be different from each other according to design needs.

  The via 60 connects the inner conductor pattern layers 210, 310, 410, 510 and the outer conductor pattern layers 110, 610 to each other. Further, the via 60 connects the inner conductor pattern layers 210, 310, 410, 510 adjacent to each other to each other. In addition, the via 60 can be stacked in a form similar to that of the stacked via, such as that formed in the lower portion of the mounting pad 111-1 of FIG.

The via 60 can be distinguished into a heat dissipation via formed in the lower part of the mounting pad 111-1 in FIG. 1 and a signal via formed in the lower part of the bonding pad 111-2 in FIG. The heat dissipation via can quickly remove the heat generated from the die (die, 700 in FIG. 2) placed on the placement pad 111-1 to the printed circuit board 1000 according to the present embodiment. The heat dissipation via can be formed to have a larger cross-sectional area than a normal signal via for quick heat dissipation.
The via 60 includes a high melting point metal layer 61 and a low melting point metal layer 62 having a melting point lower than the melting point of the high melting point metal layer 61.

  The high melting point metal layer 61 has excellent electrical characteristics and has a melting point higher than that of the low melting point metal layer 62, such as copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel ( Ni), titanium (Ti), gold (Au), platinum (Pt), or the like can be used. As an example, the refractory metal layer 61 and the conductive pattern layers 110, 210, 310, 410, 510, 610 can be all formed of copper, and in this case, since both are formed of the same kind of material, the bonding between them is performed. Power is improved. Further, the process can be simplified and the cost can be reduced as compared with the case where both are formed of different materials. However, the above-described example is merely an example, and the scope of the present invention is not limited thereto.

  The low melting point metal layer 62 has a melting point lower than that of the high melting point metal layer 61. The low melting point metal layer 62 can be formed of a solder material. Here, “solder” means a metal material that can be used for soldering, and may be an alloy containing lead (Pb) or may not contain lead. For example, the solder may be tin (Sn), silver (Ag), copper (Cu), or an alloy of metals selected from these. Specifically, the solder used in the embodiment of the present invention may be an alloy containing tin, silver and copper as components with a tin (Sn) content of 90% or more based on the entire solder.

  The low-melting point metal layer 62 is melted at least partially when a plurality of unit substrates 100, 200, 300, 400, 500, and 600, which will be described later, are collectively laminated, and the plurality of unit substrates 100, 200, 300, 400, and 500 are stacked. , 600 can be reduced.

  Since the low melting point metal layer 62 is at least partially melted by the temperature and pressure at the time of batch lamination, the low melting point metal layer 62 and the material constituting the high melting point metal layer 61 or the conductor pattern layers 110, 210, 310, 410, 510, 610 can be easily used. To form an intermetallic compound layer (Inter-Metal Compound, IMC). The intermetallic compound layer improves the physical bonding force between the conductor pattern layers 110, 210, 310, 410, 510, and 610.

(package)
FIG. 2 is a view showing a package according to an embodiment of the present invention.

As shown in FIG. 2, a package 2000 according to an embodiment of the present invention includes a printed circuit board 1000, a die 700, a passive element 800, and a coupling member 900.
Since the printed circuit board 1000 has been described above, a detailed description thereof will be omitted.

  The die 700 is a semiconductor element and is an electronic element formed by a semiconductor process. One surface of the die 700 may be an active surface on which an external connection terminal is formed, and the other surface of the die 700 may be an inactive surface (Inactive Surface). In the present embodiment, the other surface of the die 700 can be placed on the placement pad 111-1. The external connection terminal of the die 700 can be coupled to the bonding pad 111-2 of the printed circuit board 1000 through the wire W.

  The passive element 800 may be any one of an inductor, a capacitor, and a resistance element. That is, in the present specification, the description has been made on the assumption that MLCC is used as the passive element, but the present invention is not limited to this.

  The coupling member 900 is a member that electrically couples the second conductor pattern 112 to the passive element 800 and / or another substrate such as a main board. The coupling member 900 can be formed by an SMT process using a solder. The second surface treatment layer (50) described above is removed depending on the temperature during the SMT process.

  On the other hand, although not shown, the package 2000 according to the present embodiment is formed between the mounting pad 111-1 and the die 700, and is a bonding layer for fixing the die 700 or a die for fixing the die 700. A molding material covering 700 may be further included.

(Printed circuit board manufacturing method)
3 to 14 are views sequentially illustrating a method of manufacturing a printed circuit board according to an embodiment of the present invention.

  Specifically, FIGS. 3 to 8 are diagrams sequentially illustrating a manufacturing process of a unit substrate applied to a method of manufacturing a printed circuit board according to an embodiment of the present invention, and FIGS. 3 to FIG. 8 are diagrams showing a plurality of unit substrates manufactured according to FIGS. 3 to 8 being stacked together, and FIGS. 11 to 14 are diagrams sequentially showing processes after the batch stacking.

(Unit board manufacturing method)
3 to 8 are diagrams sequentially illustrating a unit substrate manufacturing process applied to the printed circuit board manufacturing method according to the embodiment of the present invention.
Hereinafter, a manufacturing process of the second unit substrate 200 shown in FIG. 9 will be described as an example with reference to FIGS.

  First, referring to FIG. 3, a carrier C in which a copper foil CF is formed on both surfaces of a support portion SF is prepared. The support portion SF can be formed of any one of a metal material, an inorganic material, and an organic material having required rigidity. The copper foil CF can be formed on both surfaces of the support portion SF using a lamination process. Alternatively, the copper foil CF can be formed on both surfaces of the support portion SF using electroless plating and electrolytic plating processes.

Next, referring to FIG. 4, the second conductor pattern layer 210 is selectively formed on the copper foil CF.
The second conductor pattern layer 210 can be formed using an MSAP (Modified Semi-Additive Process) method in which the copper foil CF is a power feeding layer for electrolytic plating.

  The second conductor pattern layer 210 is formed by forming a plating resist having a reverse pattern to the second conductor pattern layer 210 on the copper foil CF, performing electrolytic plating, and removing the plating resist after completion of the electrolytic plating. Can do.

  On the other hand, in the above-described example, the MSAP method is limited to the normal circuit pattern forming method. However, any one of the well-known Subtractive method, Full-Additive method, and Semi-Additive method is used. The second conductor pattern layer 210 can also be formed.

Next, referring to FIG. 5, the second insulating layer 220 is formed on the second conductor pattern layer 210.
The second insulating layer 220 can include a photocurable resin.

  The second insulating layer 220 can be formed by laminating an insulating film to the carrier C. That is, the second insulating layer 220 can be laminated on the second conductor pattern layer 210 using a vacuum laminator. Alternatively, the second insulating layer 220 can be formed by applying a liquid insulating material to the carrier C and then curing it.

  Next, referring to FIG. 6, a via hole VH that selectively exposes a part of the second conductive pattern layer 210 is formed in the second insulating layer 220.

  The via hole VH can be formed by a photolithography method. That is, when the second insulating layer 220 is a photosensitive insulating layer, the via hole VH can be formed by selectively exposing and developing the second insulating layer 220. Alternatively, the via hole VH can be formed by laser drilling.

  The second insulating layer 220 is in a semi-cured state (B-stage) before the batch lamination even though the second exposure layer 220 is selectively subjected to the exposure process. For example, the second insulating layer 220 that has been subjected to the selective exposure process may have a curing degree of 10 to 20% as compared with a fully cured state (C-stage).

  On the other hand, if necessary, the second insulating layer 220 may be semi-cured by a separate process so as to have a degree of cure of 50% compared to the fully cured state (C-stage). The separate semi-curing process can be performed using UV light used in a photolithography process for forming the via hole VH. However, even in this case, the second insulating layer 220 is not completely cured before batch lamination.

  Next, referring to FIGS. 7 and 8, a refractory metal layer 61 and a low melting point metal layer 62 are sequentially formed in the via hole VH.

  The refractory metal layer 61 is formed by electrolytic plating. In the case of electrolytic plating, all anisotropic or isotropic plating is included. The refractory metal layer 61 is formed by copper electrolytic plating and can contain copper (Cu). In forming the refractory metal layer 61 by electrolytic plating, the second conductor pattern layer 210 can function as a power feeding layer.

  The low melting point metal layer 62 is formed by selectively plating a low melting point metal such as solder or by selectively applying a low melting point metal paste such as a solder paste and then drying the low melting point metal paste. Can do.

  The solder or the solder paste can be mainly composed of tin, silver, copper, or an alloy of a metal selected from these. Further, the solder paste used in the present invention may not contain a flux. The solder paste includes a sintered mold that hardens at a relatively high temperature (ex. 800 ° C.) and a curable mold that hardens at a relatively low temperature (ex. 200 ° C.). As the solder paste used in the present embodiment, a curing type that hardens at a relatively low temperature can be used in order to prevent the second insulating layer 220 from being completely cured when the solder paste is cured.

  The low melting point metal paste can have a relatively high viscosity and can maintain its shape after being formed on the high melting point metal layer 61. Further, the low melting point metal paste has low melting point metal particles, and the surface of the low melting point metal layer 62 formed by solidifying the low melting point metal paste with the particles may be bumpy.

  Next, the second unit substrate 200 is separated from the carrier C by separating the support portion SF and the copper foil CF. At this time, although not shown, a cover film can be formed on the low melting point metal layer 62 and the second insulating layer 220.

  The cover film is configured to protect the low-melting point metal layer 62 and the second insulating layer 220 before the batch lamination process, and is separated from the second unit substrate 200 immediately before the batch lamination process.

  In the above description, the second unit substrate 200 is used as a reference, but the first unit substrate 100 and the third unit substrate to the sixth unit substrates 300, 400, 500, and 600 can be manufactured by the same process.

  Further, in the above description and FIGS. 3 to 8, it has been described and illustrated that the process for forming the unit substrate is applied only to one surface of the carrier C. However, the same unit substrate is also applied to the other surface of the carrier. A process for forming the substrate or a process for forming another unit substrate may be applied.

(Step of stacking unit substrates in a batch)
FIGS. 9 and 10 are views showing that a plurality of unit substrates manufactured according to FIGS. 3 to 8 are stacked together.

  Referring to FIG. 9, a plurality of unit substrates 100, 200, 300, 400, 500, and 600 are vertically arranged. At this time, the plurality of unit substrates 100, 200, 300, 400, 500, 600 are aligned with each other using alignment marks formed on the plurality of unit substrates 100, 200, 300, 400, 500, 600. . Each of the fifth unit substrates 200, 300, 400, 500 from the second unit substrate excluding the first and sixth unit substrates 100, 600 is aligned after the copper foil CF is removed. The copper foil CF remaining on the first and sixth unit substrates 100 and 600 serves as a power feeding layer when the first surface treatment layer 40 described later is plated.

  Referring to FIG. 10, a plurality of aligned unit substrates 100, 200, 300, 400, 500, 600 are bonded together by high-temperature pressure bonding using a V-press laminator or the like.

  The temperature at the time of collective lamination can be set to 180 to 200 ° C., and the press pressure can be set to 30 to 50 kg / cm 2. The temperature and pressure at the time of collective lamination are not limited to these values. The insulating layer can be set differently depending on the components of the sixth insulating layers 120, 220, 320, 420, 520, 620, the component of the low melting point metal layer 62, and the like. In particular, the temperature at the time of batch stacking may be equal to or higher than the melting point of the low melting point metal layer 62.

  The low melting point metal layer 62 spreads toward the insulating layers 120, 220, 320, 420, 520, 620 due to the pressure at the time of collective lamination, whereby the upper cross-sectional area of the low melting point metal layer 62 and the low melting point metal layer 62 are expanded. The lower cross-sectional area may be different from each other.

  The first to sixth insulating layers 120, 220, 320, 420, 520, and 620 that are in a semi-cured state are completely cured by the temperature and pressure during the batch lamination.

  Next, referring to FIG. 11, the first surface treatment layer 40 is formed on the first insulating layer 120 and / or the sixth insulating layer 620. As described above, since the copper foil CF described above remains on the first unit substrate and the sixth unit substrate 100, 600, the copper foil CF is used as a power feeding layer when the first surface treatment layer 40 is formed by plating. be able to.

  The first surface treatment layer 40 can be formed by forming a plating resist having a reverse transfer pattern to the first surface treatment layer 40 on the copper foil CF, and removing the plating resist after performing electrolytic plating. . The first surface treatment layer 40 may include gold (Au) having excellent electrical conductivity and thermal conductivity for rapid signal transfer and heat transfer with the die (700 in FIG. 2). Although not shown, a bonding layer can be formed between the first surface treatment layer 40 and the copper foil CF. The bonding layer can include nickel (Ni) that has relatively high bonding force with the copper foil CF. The bonding layer can be formed by electrolytic plating using the copper foil CF as a power feeding layer.

  Next, referring to FIG. 12, the seed layer 30 is formed by selectively removing the copper foil CF. That is, the seed layer 30 is formed by removing a region of the copper foil CF where the first surface treatment layer 40 is not formed. The seed layer 30 can be removed by selectively etching the copper foil CF (such as quick etching and half etching). At this time, the first surface treatment layer 40 functions as an etching resist. By selectively etching the copper foil CF, the second conductor pattern 112 is exposed to the outside.

  Next, referring to FIG. 13, soft etching is performed. The soft etching process is a process performed before forming the second surface treatment layer 50 on the second conductor pattern 112, and forms a roughness on the surface of the second conductor pattern 112, and the second conductor pattern 112 and the second conductor pattern 112 2 This is a step for improving the bonding strength with the surface treatment layer 50.

  The soft etching is performed using an etchant that chemically reacts with the constituent material of the second conductor pattern 112. When the second conductor pattern 112 is formed of copper (Cu), the soft etching can be performed using a copper etchant. The first surface treatment layer 40 is already formed on the first conductor pattern 111, and the first surface treatment layer 4 has a standard reduction potential higher than the standard reduction potential of the first conductor pattern 111 and / or the seed layer 30. Since the first conductive pattern 111 and / or the seed layer 30 are formed on both sides of the first conductive pattern 111, the recess R is formed by the soft etching.

  Next, referring to FIG. 14, the second surface treatment layer 50 is formed on the second conductor pattern 112. The second surface treatment layer 50 may be a normal OSP layer containing an organic material.

  On the other hand, although not shown, before the second surface treatment layer 50 is formed after the soft etching, a pretreatment step of bonding an active group to the surface of the second conductor pattern 112 can be performed.

  In the above, one embodiment of the present invention has been described. However, those who have ordinary knowledge in the technical field can add components without departing from the spirit of the present invention described in the claims. The present invention can be modified and changed in various ways by changes or deletions, and it can be said that this is also included in the scope of the right of the present invention.

C Carrier CF Copper foil R Recessed portion SF Support portion W Wire VH Via hole 20 Insulating portion 30 Seed layer 40 First surface treatment layer 50 Second surface treatment layer 60 Via 61 High melting point metal layer 62 Low melting point metal layer 100, 200, 300 , 400, 500, 600 Unit substrate 110, 210, 310, 410, 510, 610 Conductive pattern layer 120, 220, 320, 420, 520, 620 Insulating layer 111 First conductive pattern 111-1 Mounting pad 111-2 Bonding Pad 112 Second conductor pattern 700 Die 800 Passive element 900 Coupling member 1000 Printed circuit board 2000 Package

Claims (10)

An insulating part;
An outer conductor pattern layer including a first conductor pattern and a second conductor pattern respectively embedded in one surface of the insulating portion;
A first surface treatment layer formed on the first conductor pattern and protruding from one surface of the insulating portion;
A seed layer formed between the first conductor pattern and the first surface treatment layer and protruding from one surface of the insulating portion;
A second surface treatment layer formed on the second conductor pattern and containing an organic substance;
A recess formed on both sides of at least one of the first conductor pattern and the seed layer;
Including printed circuit board. The first surface treatment layer is
The printed circuit board according to claim 1, comprising a material having a standard reduction potential higher than a standard reduction potential of a material forming at least one of the first conductor pattern and the seed layer.   The printed circuit board according to claim 1, wherein at least a part of the second surface treatment layer is embedded in the insulating portion. The recess portion formed in the first conductor pattern is
The printed circuit board according to any one of claims 1 to 3, wherein a cross-sectional area decreases from one surface of the insulating portion toward the inside of the insulating portion. An inner conductor pattern layer formed inside the insulating portion;
The printed circuit board according to claim 1, further comprising a via that connects the inner conductor pattern layer and the outer conductor pattern layer to each other. The via is
A refractory metal layer,
The printed circuit board according to claim 5, further comprising: a low melting point metal layer having a melting point lower than a melting point of the high melting point metal layer.   The printed circuit board according to claim 6, wherein the low-melting-point metal layer includes tin (Sn).   The printed circuit board according to claim 1, wherein the insulating portion includes a photocurable resin. An insulating part, a printed circuit board including a first pad part and a second pad part respectively formed on one surface of the insulating part;
A die coupled to the first pad portion;
A passive element coupled to the second pad portion,
The first pad portion is
A conductor pattern embedded in one surface of the insulating portion;
A seed layer formed on the conductor pattern;
A surface treatment layer formed on the seed layer, protruding from one surface of the insulating portion, and having a standard reduction potential higher than a standard reduction potential of at least one of the conductor pattern and the seed layer;
A recess formed on both sides of at least one of the conductor pattern and the seed layer;
Including the package.   And a coupling member interposed between the second pad part and the passive element, connecting the second pad part and the passive element, and having at least a part embedded in one surface of the insulating part. 9. The package according to 9.

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