TWI465171B - Package circuit board, method for manufacturing asme, and package structure - Google Patents

Description

Carrying circuit board, carrying circuit board manufacturing method and packaging structure

The present invention relates to the field of circuit board manufacturing, and in particular, to a carrier circuit board, a manufacturing method of the carrier circuit board, and a package structure.

Printed circuit boards have been widely used due to their high assembly density. For application of the board, please refer to the literature Takahashi, A. Ooki, N. Nagai, A. Akahoshi, H. Mukoh, A. Wajima, M. Res. Lab, High density multilayer printed circuit board for HITAC M-880, IEEE Trans On Components, Packaging, and Manufacturing Technology, 1992, 15(4): 1418-1425. The pads of the outer conductive traces of a common board are exposed on the same side of the board, and the pads exposed on the same side are on the same plane. When the wafer is mounted on the exposed pad, the pad is located below the wafer, thereby increasing the height of the board having the wafer and expanding the volume of the board having the wafer.

In view of the above, a carrier circuit board, a manufacturing method of the carrier circuit board, and a package structure are provided, and a circuit board having a receiving slot can be obtained, so that at least part of the chip is received in the receiving slot when the circuit board is formed into the package structure. Therefore, it is necessary to reduce the thickness of the package structure and reduce the size of the package structure.

A method for manufacturing a carrier circuit board includes the steps of: providing a core circuit substrate, the core circuit substrate comprising a glass substrate, a plurality of first electrical contact pads, and a peelable protective layer, wherein the plurality of glass substrates are disposed a metal conductive pillar, the first electrical contact pad and the corresponding metal conductive pillar are electrically connected to each other, the peelable protective layer is formed on the surface of the first electrical contact pad; and the support plate, the insulating substrate and the dielectric film are provided; An opening corresponding to the shape of the core circuit substrate is formed in the insulating substrate, the cross-sectional area of the opening is larger than the cross-sectional area of the core circuit substrate; and the core circuit substrate and the insulating substrate are disposed on one side of the support plate The peelable protective layer is in contact with the support plate, the core circuit substrate is received in the opening, and the dielectric film is located on a side of the core circuit substrate and the insulating substrate away from the support plate to form a stack a structure; pressing the stacked structure such that a portion of the dielectric film is filled into the opening to connect the core circuit substrate and the insulating substrate, the dielectric film, the core circuit substrate, and the insulating substrate Forming a circuit substrate together; separating the support plate from the circuit substrate; forming a plurality of second electrical contact pads on a surface of the insulating substrate away from the dielectric film, the surface of the dielectric film being away from the insulating substrate Forming a second outer conductive layer; and removing the peelable protective layer to form a receiving groove, the first electrical contact pad is exposed from the bottom of the receiving groove to obtain a carrying circuit board.

A carrier circuit board comprising a core circuit substrate, an insulating substrate, a dielectric film, a first outer conductive layer and a second outer conductive layer, the core circuit substrate comprising a glass substrate and a plurality of first electrical contacts a plurality of metal conductive pillars disposed in the glass substrate, wherein the first electrical contact pads are electrically connected to one end of a corresponding metal conductive pillar, and the insulating substrate has an opening corresponding to the core circuit substrate The cross-sectional area of the first opening is larger than the cross-sectional area of the core circuit substrate, the core circuit substrate is received in the opening, and the dielectric film is connected to the side of the core circuit substrate and the insulating substrate a surface formed in the opening to fill a gap between the insulating substrate and the core circuit substrate, wherein the first outer conductive layer is formed on the surface of the insulating substrate away from the dielectric film, and the second outer conductive layer Formed on the surface of the dielectric film, the carrier circuit board has a receiving groove, and the first electrical contact pad of the core circuit substrate is exposed from the receiving groove.

A package structure includes a first wafer and the carrier circuit board, the first wafer being interconnected with a first electrical contact pad in the receiving slot by a first solder ball.

The circuit board and the manufacturing method thereof provided by the technical solution first provide a core circuit substrate having a first conductive line pattern and an insulating substrate formed with an opening, and then the core circuit substrate and the insulating substrate are mutually exchanged by using a dielectric film The connection is then made to form an outer conductive layer. Since the conductive lines in the core circuit substrate are separately formed from the conductive lines of the outer layer, the conductive lines of the core circuit substrate can be made thin, and the conductive lines of the outer layer can be relatively thick, not only the thin circuit board is realized. The function, and avoiding the need of forming a thin circuit area, still requires a complicated circuit manufacturing process and forming a conductive circuit, thereby reducing the manufacturing process of the circuit board and reducing the manufacturing cost of the circuit board. In addition, in the manufacturing process, the thickness of the insulating substrate used is larger than the thickness of the core circuit substrate, and when the core circuit substrate is received in the opening of the insulating substrate, a receiving groove is formed. When the circuit board is packaged, part or all of the wafers packaged thereon can be received in the receiving groove, so that the size of the package structure after packaging can be reduced.

Further, the prior art uses plastic as the substrate of the core circuit substrate because of the core circuit substrate, and the wafer is usually made of tantalum. Since the thermal expansion coefficient of the plastic differs greatly from the thermal expansion coefficient of the crucible, when the wafer is packaged, it is easy to cause quality problems due to inconsistent expansion and contraction. In the technical solution, the core circuit substrate is made of a glass substrate, and the thermal expansion coefficient of the glass is less than that of the germanium, so that the quality of the formed package structure can be improved.

The technical solution provides a detailed description of the circuit board, the circuit board manufacturing method and the package structure provided by the technical solution according to specific embodiments.

The manufacturing method of the circuit board provided by the technical solution includes the following steps:

In the first step, referring to FIG. 1, two core circuit substrates 10 are provided.

The core layer circuit substrate 10 includes a glass substrate 11 , a first conductive wiring layer 12 , a first insulating layer 14 , a plurality of first electrical contact pads 15 , and a peelable protective layer 13 .

The glass substrate 11 has opposing first and second surfaces 113, 114. The glass substrate 11 has a thickness of from 100 micrometers to 500 micrometers. The first conductive wiring layer 12 is formed on the first surface 113 of the glass substrate 11. A plurality of first through holes 111 penetrating through the glass substrate 11 are formed in the glass substrate 11 , and a metal conductive pillar 112 filling the corresponding first through holes 111 is formed in each of the first through holes 111 . One end of each of the metal conductive pillars 112 is electrically connected to the first conductive wiring layer 12. The other end of each of the metal conductive pillars 112 is flush with the second surface 114 of the glass substrate 11. The spacing between adjacent metal conductive pillars 112 can be between 100 microns and 200 microns.

The first insulating layer 14 is formed on the first surface 113 side of the glass substrate 11 and covers the first conductive wiring layer 12 . The first electrical contact pad 15 is formed on a side surface of the first insulating layer 14 away from the glass substrate 11 . A plurality of conductive holes 141 are formed in the first insulating layer 14 , and the first conductive circuit layer 12 and the first electrical contact pads 15 are electrically connected to each other through the conductive holes 141 . The spacing between adjacent first electrical contact pads 15 is between 50 microns and 100 microns.

The peelable protective layer 13 covers the first electrical contact pad 15 to prevent the first electrical contact pad 15 from being damaged in a subsequent fabrication step. The peelable protective layer 13 may be a polymer film such as a polypropylene film, a polyethylene film, or a polyethylene terephthalate. Preferably, in the embodiment, the peelable protective layer 13 is a polyethylene terephthalate film. The peelable protective layer 13 can also be a peelable film or a peelable adhesive commonly used in other industries.

Referring to FIG. 1 to FIG. 8 together, the core circuit substrate 10 can be fabricated as follows:

First, a glass substrate 11 is provided, and a plurality of first blind holes 1111 that are in one-to-one correspondence with the first through holes 111 are formed in the glass substrate 11.

This step can be achieved by first forming a photoresist layer on the first surface 113 of the glass substrate 11, and then forming a barrier pattern 115 by exposure and development. A plurality of first blind holes 1111 are formed on the first surface 113 side of the glass substrate 11 not blocked by the barrier pattern 115 by sandblasting, ultrasonic drilling or wet etching. The plurality of first blind vias 1111 have a pore size of less than 50 microns.

Then, a metal conductive pillar 112 is formed in the plurality of first blind holes 1111.

Specifically, in this step, a copper layer is formed on the inner wall of the first blind via 1111 and the first surface 113 by sputtering or evaporation, and metal conduction is formed in the first blind via 1111 by electroplating. The pillar 112 forms a conductive layer on the first surface 113. Thereafter, the first conductive layer of the first surface 113 is removed by chemical mechanical planarization.

Next, a first conductive wiring layer 12 is formed on the first surface 113 of the glass substrate 11. The first conductive wiring layer 12 may be formed by electroless plating and then electroplating. The first conductive wiring layer 12 and the metal conductive pillars 112 are electrically connected to each other.

Next, a first insulating layer 14 is formed on the surface of the first conductive wiring layer 12. The material of the first insulating layer 14 may be polyimide. In the first insulating layer 14, a plurality of openings are formed such that a portion of the first conductive wiring layer 12 is exposed from the opening. The width of the opening is less than or equal to 10 microns.

Next, the glass substrate 11 is thinned from the second surface 114 side such that the other end of each of the metal conductive pillars 112 is exposed from the second surface 114 side of the glass substrate 11.

In this step, a part of the glass substrate 11 can be removed in the thickness direction by sanding.

Next, a plurality of first electrical contact pads 15 are formed on the side of the first insulating layer 14 away from the first conductive wiring layer 12.

The forming of the first electrical contact pad 15 includes first forming a deposited metal layer at the opening of the first insulating layer 14, and the deposited metal layer may be formed by chemical deposition. The deposited metal layer may be titanium, copper or nickel. Then, a solder ball or a conductive paste is formed on the deposited metal layer, thereby obtaining a plurality of first electrical contact pads 15.

Finally, a peelable protective layer 13 is formed on one side of the plurality of first electrical contact pads 15.

In the second step, referring to FIG. 9 to FIG. 12, a first insulating substrate 31, a second insulating substrate 32, a support plate 20, a first dielectric film 41, and a second dielectric film 42 are provided.

The first insulating substrate 31 and the second insulating substrate 32 are made of an insulating material, and may be made of a hard material or a soft material.

A first opening 33 penetrating the first insulating substrate 31 in the thickness direction is formed in the first insulating substrate 31. The first opening 33 corresponds to the core circuit substrate 10. The shape of the first opening 33 is the same as that of the core circuit substrate 10, and the cross-sectional area of the first opening 33 is larger than the cross-sectional area of the core circuit substrate 10.

A second opening 34 penetrating the second insulating substrate 32 in the thickness direction is formed in the second insulating substrate 32. The second opening 34 corresponds to the core circuit substrate 10. The shape of the second opening 34 is the same as that of the core circuit substrate 10, and the cross-sectional area of the second opening 34 is larger than the cross-sectional area of the core circuit substrate 10.

Preferably, the thicknesses of the first insulating substrate 31 and the second insulating substrate 32 are equal to the thickness of the core layer circuit substrate 10.

The support plate 20 includes a body 20a and a release film 201 formed on opposite surfaces of the body 20a. The release film 201 may be a polymer film such as a polypropylene film, a polyethylene film or a polyethylene terephthalate, and is preferably a polyethylene terephthalate film. In this embodiment, a poly film is used. A polyethylene terephthalate film is used as the release film 201. The release film 201 can also be a release paper commonly used in other industries.

The first dielectric film 41 and the second dielectric film 42 may be semi-cured films that are common in the art.

In the third step, referring to FIG. 13 , the two core circuit substrates 10 are respectively disposed on opposite sides of the support board 20 , and one surface of the peelable protective layer 13 of the core circuit substrate 10 is attached to the surface of the support board 20 . The first insulating substrate 31 and the second insulating substrate 32 are respectively disposed on opposite sides of the support board 20, and one core circuit substrate 10 is located in the first opening 33 of the first insulating substrate 31, and the other core layer The circuit substrate 10 is located in the second opening 34 of the second insulating substrate 32. The first dielectric film 41 is located on a side of the core circuit substrate 10 and the first insulating substrate 31 away from the support board 20, and the second dielectric film 42 is disposed. On the side of the other core layer circuit substrate 10 and the second insulating substrate 32 away from the support plate 20, a stacked structure 101 is formed.

In the fourth step, referring to FIG. 14, the stacked structure 101 is pressed such that the first dielectric film 41 is filled into the first opening 33, so that the gap between the core circuit substrate 10 and the first insulating substrate 31 is The first dielectric film 41 is filled so that the first dielectric film 41, the first insulating substrate 31, and the core circuit substrate 10 located in the first opening 33 become a circuit substrate 103. And filling the second dielectric film 42 into the second opening 34, so that the gap between the core circuit substrate 10 and the second insulating substrate 32 is filled by the second dielectric film 42, so that the second dielectric film 42 The second insulating substrate 32 and the core layer circuit substrate 10 located in the second opening 34 become the other circuit substrate 103.

During the press-fitting process, the first dielectric film 41 and the second dielectric film 42 may flow in a high temperature and high pressure state. The material of the first dielectric film 41 and the second dielectric film 42 may be Polyimide (PI), polyethylene terephthalate (PET) or polyethylene naphthalate. Polyethylene naphthalate (PEN), PP (Prepreg) or ABF (Ajinomoto Build-up film) or the like is preferably PP or ABF.

In the fifth step, referring to FIG. 15, the two circuit substrates 103 and the support plate 20 are separated from each other.

Since the surface of the support plate 20 has the release film 201, the circuit substrate 103 can be easily separated from the support plate 20.

Since the subsequent fabrication steps are the same, only the subsequent fabrication of one circuit substrate 103 will be described below as an example.

In the sixth step, referring to FIG. 16, at least one second through hole 311 is formed in the first dielectric film 41 and the first insulating substrate 31 of the circuit substrate 103, and a plurality of the first dielectric film 41 are formed. The second blind via 312 exposes the metal conductive pillars 112 from the corresponding second blind vias 312.

In this step, the second through hole 311 and the second blind hole 312 can be formed by laser ablation. The second through hole 311 extends through the first dielectric film 41 and the first insulating substrate 31 . The second through hole 311 can also be formed by mechanical drilling. The number of the second through holes 311 may be one or plural. In FIG. 4, two second through holes 311 are formed as an example for description. The second blind via 312 extends only through the first dielectric film 41 and exposes the metal conductive pillars 112. The number of the second blind holes 312 may be one or plural, and the two second blind holes 312 are formed as an example in FIG. 4 .

It can be understood that after this step, the step of desmear may be further included to remove the glue inside the second through hole 311 and the second blind hole 312, thereby effectively preventing subsequent processing. When electroplating, the slag affects the conductivity of the formed conductive holes.

In the fifth step, referring to FIG. 17, a first outer conductive layer 410 is formed on the surface of the first insulating substrate 31, and a second outer conductive layer 420 is formed on the surface of the first dielectric film 41. The first outer conductive layer 410 includes a plurality of second electrical contact pads 411 electrically connected to the outside and a plurality of conductive lines (not shown). The second outer conductive layer 420 includes a plurality of third electrical contact pads 421 for electrically connecting to the outside and a plurality of conductive lines.

This step can specifically adopt the following methods:

First, a first conductive seed layer is formed on the surface of the first insulating substrate 31 and the peelable protective layer 13 by electroless copper plating, and the inner wall of the second through hole 311, the inner wall of the second blind hole 312, and the first A second conductive seed layer is formed on the surface of the dielectric film 41.

It can be understood that other methods, such as blackening or chemisorption of conductive particles, etc., on the surface of the first insulating substrate 31, the inner wall of the second through hole 311, the inner wall of the second blind hole 312, and the first dielectric may be employed. The surface of the film 41 forms a first conductive seed layer and a second conductive seed layer.

Next, a photoresist layer is formed on the surfaces of the first conductive seed layer and the second conductive seed layer, respectively, and the portion corresponding to the first outer conductive layer 410 is formed by exposure and development. A photoresist pattern is removed from the portion corresponding to the second outer conductive wiring layer 420 to obtain a second photoresist pattern.

Next, a first plated copper layer is formed on the surface of the first conductive seed layer exposed from the void of the first photoresist pattern, and a second surface is formed on the surface of the second conductive seed layer exposed from the second photoresist pattern Electroplated copper layer.

Finally, the first photoresist pattern and the second photoresist pattern are removed by stripping, and the first conductive seed layer originally covered by the first photoresist pattern is removed by microetching. Removing the second conductive seed layer that was originally covered by the second photoresist pattern. Thus, the first conductive seed layer on the surface of the first insulating substrate 31 and the first electroplated copper layer formed thereon collectively constitute the first outer conductive layer 410. A second conductive seed layer on the surface of the first dielectric film 41 and a second electroplated copper layer formed thereon collectively constitute a second outer conductive layer 420. The second conductive seed layer located in the second through hole 311 and the second electroplated copper layer formed thereon constitute a conductive via 313 penetrating through the first dielectric film 41 and the first insulating substrate 31. The second conductive seed layer located in the second blind via 312 and the second electroplated copper layer formed thereon form a second conductive via 314. The first outer conductive layer 410 and the second outer conductive layer 420 are electrically connected to each other through the conductive via 313. The second outer conductive circuit layer 420 and the metal conductive pillars 112 are electrically connected to each other through the second conductive blind vias 314.

In the seventh step, referring to FIG. 18, the peelable protective layer 13 is removed by stripping to form a receiving groove 102.

In the eighth step, referring to FIG. 19, a first solder resist layer 430 is formed on the surface of the first outer conductive layer 410 and the surface of the first insulating substrate 31 exposed from the first outer conductive layer 410, in the second A surface of the outer conductive wiring layer 420 and a surface of the first dielectric film 41 exposed from the second outer conductive wiring layer 420 form a second solder resist layer 440. The first solder resist layer 430 has a plurality of first openings 431 corresponding to the plurality of second electrical contact pads 411 , and each of the second electrical contact pads 411 is exposed from the corresponding first opening 431 . The second solder resist layer 440 has a plurality of second openings 441 corresponding to the plurality of third electrical contact pads 421 , and each of the third electrical contact pads 421 is exposed from the corresponding second opening 441 .

In the ninth step, a first protective layer 123 is formed on the surface of each of the first electrical contact pads 121 of the first conductive wiring layer 12. A second protective layer 450 is formed on a surface of each of the second electrical contact pads 411 exposed from the first opening 431. A third protective layer 460 is formed on the surface of each of the third electrical contact pads 421 exposed from the second opening 441 to obtain the carrier circuit board 100.

In this embodiment, the first protective layer 123, the second protective layer 450, and the third protective layer 460 may be a single layer structure of a metal such as tin, lead, silver, gold, nickel, palladium or the like, or an alloy thereof. Two or more kinds of multilayer structures of the above metals. The first protective layer 123, the second protective layer 450, and the third protective layer 460 may also be an organic solder resist layer (OSP). When the first protective layer 123 and the second protective layer 450 are metal, the first protective layer 123, the second protective layer 450, and the third protective layer 460 may be formed by electroless plating. When the first protective layer 123, the second protective layer 450, and the third protective layer 460 are organic solder resist layers, the first protective layer 123, the second protective layer 450, and the third protective layer 460 may be formed by a chemical method.

It can be understood that, in the manufacturing method provided by the technical solution, in the third and fourth steps, the core circuit substrate 10, the insulating substrate and the dielectric film may be disposed only on one side of the support board 20, that is, in the fabrication. In the process, only one carrier circuit board 100 is fabricated.

In the carrier circuit board 100, since the peelable protective layer 13 in the previous step is removed, the carrier circuit board 100 has a receiving groove 102 from which the first electrical contact pad 121 is exposed.

Referring to FIG. 19 , the technical solution provides a carrier circuit board 100 fabricated by the above method, including a core circuit substrate 10 , a first insulating substrate 31 , a first dielectric film 41 , a first outer conductive layer 410 , and a first Two outer conductive circuit layers 420.

The first insulating substrate 31 has a first opening 33 corresponding to the core circuit substrate 10, and the first opening 33 has a cross-sectional area larger than that of the core circuit substrate 10. The core layer circuit substrate 10 is received in the first opening 33. The first dielectric film 41 is connected to one side surface of the core circuit substrate 10 and the first insulating substrate 31, and is formed in the first opening 33 to fill the first insulating substrate 31 and the core circuit substrate 10. The gap between the first insulating substrate 31, the core circuit substrate 10, and the first dielectric film 41 is integrated.

The first outer conductive layer 410 is formed on a surface of the first insulating substrate 31 away from the first dielectric film 41. The second outer conductive layer 420 is formed on the surface of the first dielectric film 41. At least one second conductive via 313 is formed in the first insulating substrate 31, and the first outer conductive layer 410 and the second outer conductive layer 420 are electrically connected to each other through the conductive via 313.

The thickness of the first insulating substrate 31 is larger than the thickness of the core circuit substrate 10. On the side of the first outer conductive layer 410, the carrier circuit board 100 has a receiving groove 102. The first electrical contact pads 151 of the core circuit substrate are exposed from the receiving slots 102.

The first outer conductive layer 410 includes a plurality of second electrical contact pads 411. The second outer conductive layer 420 includes a plurality of third electrical contact pads 421.

The carrier circuit board 100 further includes a first solder resist layer 430 and a second solder resist layer 440. The first solder resist layer 430 has a plurality of first openings 431 corresponding to the plurality of second electrical contact pads 411 , and each of the second electrical contact pads 411 is exposed from the corresponding first opening 431 . The second solder resist layer 440 has a plurality of second openings 441 corresponding to the plurality of third electrical contact pads 421 , and each of the third electrical contact pads 421 is exposed from the corresponding second opening 441 .

The carrier circuit board 100 further includes a first protective layer 123, a second protective layer 450, and a third protective layer 460. The first protective layer 123 is formed on the surface of each of the first electrical contact pads 121 of the first conductive wiring layer 12. The second protective layer 450 is formed on a surface of each of the second electrical contact pads 411 exposed from the first opening 431. The third protective layer 460 is formed on a surface of each of the third electrical contact pads 421 exposed from the second opening 441.

Referring to FIG. 20 , the technical solution further provides a package structure 200 including the above-mentioned carrier circuit board 100 .

The package structure 200 includes a carrier circuit board 100, a first wafer 50, a connection substrate 60, and a second wafer 70.

The first wafer 50 is packaged on the carrier circuit board 100. The cross-sectional area of the first wafer 50 is substantially equal to the cross-sectional area of the receiving groove 102. The first wafer 50 has a plurality of fourth electrical contact pads 51 that are in one-to-one correspondence with the plurality of first electrical contact pads 121. Each of the first electrical contact pads 121 and the corresponding fourth electrical contact pads 51 are in communication with each other through the first solder balls 81. The material of the first solder ball 81 may be tin, lead or copper, or an alloy of tin, lead or copper. The receiving circuit board 100 has a receiving groove 102 therein, so that the first solder ball 81 can be received in the receiving groove 102 or some or all of the first wafer 50 can be accommodated in the receiving groove 102.

The connection substrate 60 includes an insulating substrate 61, a first conductive pattern 62 and a second conductive pattern 63 respectively disposed on opposite sides of the insulating substrate 61, and a third solder resist formed on the first conductive pattern 62 and the second conductive pattern 63, respectively. Layer 64 and fourth solder mask 65. A conductive hole is formed in the insulating substrate 61, and the first conductive pattern 62 and the second conductive pattern 63 are electrically connected to each other through the conductive hole. The first conductive pattern 62 includes a plurality of fifth electrical contact pads 621 that are in one-to-one correspondence with the plurality of second electrical contact pads 411 . The second conductive pattern 63 includes a plurality of sixth electrical contact pads 631.

The third solder resist layer 64 has a plurality of third openings, and each of the fifth electrical contact pads 621 is exposed from the corresponding third opening. A plurality of fourth openings are formed in the fourth solder resist layer 65, and each of the sixth electrical contact pads 631 is exposed from the corresponding fourth opening.

The connection substrate 60 is packaged on the carrier circuit board 100. Specifically, each of the fifth electrical contact pads 621 and the corresponding second electrical contact pads 411 are electrically connected to each other through the second solder balls 82.

The second wafer 70 is packaged on the connection substrate 60. In this embodiment, the second wafer 70 is a wire bonding (WB) wafer, and the second wafer 70 is electrically connected to the sixth electrical contact pad 631. Specifically, the second wafer 70 has a plurality of bonding contacts and a plurality of strip bonding wires 71 extending from the plurality of bonding contacts, and the bonding wires 71 are in one-to-one correspondence with the sixth electrical contact pads 631. One end of the plurality of strip bonding wires 71 is electrically connected to the second wafer 70, and the other end is electrically connected to the plurality of sixth electrical contact pads 631, respectively, so that the second wafer 70 is electrically connected to the second conductive pattern 63.

In this embodiment, the surface of the third solder resist 64 and the sixth electrical contact pad 631 exposed by the bonding wires 71, the second wafer 70 and the connecting substrate 60 are encapsulated by the encapsulant 72. In this embodiment, the encapsulant 72 is a black plastic. Of course, the encapsulant 72 can also be encapsulated with other colloidal materials, and is not limited to this embodiment.

The circuit board and the manufacturing method thereof provided by the technical solution first provide a core circuit substrate having a first conductive line pattern and an insulating substrate formed with an opening, and then the core circuit substrate and the insulating substrate are mutually exchanged by using a dielectric film The connection is then made to form an outer conductive layer. Since the conductive lines in the core circuit substrate are separately formed from the conductive lines of the outer layer, the conductive lines of the core circuit substrate can be made thin, and the conductive lines of the outer layer can be relatively thick, not only the thin circuit board is realized. The function, and avoiding the need of forming a thin circuit area, still requires a complicated circuit manufacturing process and forming a conductive circuit, thereby reducing the manufacturing process of the circuit board and reducing the manufacturing cost of the circuit board.

In addition, in the manufacturing process, the thickness of the insulating substrate used is larger than the thickness of the core circuit substrate, and when the core circuit substrate is received in the opening of the insulating substrate, a receiving groove is formed. When the circuit board is packaged, part or all of the wafers packaged thereon can be received in the receiving groove, so that the size of the package structure after packaging can be reduced.

Further, the prior art uses plastic as the substrate of the core layer circuit substrate due to the core circuit substrate, and the wafer is usually made of tantalum. Since the thermal expansion coefficient of the plastic differs greatly from the thermal expansion coefficient of the crucible, when the wafer is packaged, it is easy to cause quality problems due to inconsistent expansion and contraction. In the technical solution, the core circuit substrate is made of a glass substrate, and the thermal expansion coefficient of the glass is less than that of the germanium, so that the quality of the formed package structure can be improved.

However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.

100. . . Bearer board

10. . . Core circuit substrate

11. . . glass substrate

12. . . First conductive circuit layer

13. . . Peelable protective layer

14. . . First insulating layer

15. . . First electrical contact pad

111. . . First through hole

112. . . Metal conductive column

113. . . First surface

114. . . Second surface

115. . . Blocking graphics

1111. . . First blind hole

141. . . Conductive hole

121. . . First electrical contact pad

20. . . Support plate

20a. . . Ontology

31. . . First insulating substrate

33. . . First opening

32. . . Second insulating substrate

34. . . Second opening

201. . . Release film

41. . . First dielectric film

42. . . Second dielectric film

103. . . Circuit substrate

311. . . Second through hole

312. . . Second blind hole

313. . . Conductive through hole

314. . . Conductive blind hole

410. . . First outer conductive layer

420. . . Second outer conductive layer

411. . . Second electrical contact pad

421. . . Third electrical contact pad

101. . . Stack structure

102. . . Storage slot

430. . . First solder mask

431. . . First opening

440. . . Second solder mask

441. . . Second opening

123. . . First protective layer

450. . . Second protective layer

460. . . Third protective layer

200. . . Package structure

50. . . First wafer

51. . . Fourth electrical contact pad

60. . . Connection substrate

61. . . Insulating substrate

62. . . First conductive pattern

63. . . Second conductive pattern

621. . . Fifth electrical contact pad

631. . . Sixth electrical contact pad

64. . . Third solder mask

65. . . Fourth solder mask

70. . . Second chip

71. . . Bond wire

72. . . Encapsulant

81. . . First solder ball

82. . . Second solder ball

1 is a schematic cross-sectional view of a core circuit substrate provided by the present technical solution.

2 to 8 are schematic diagrams showing a manufacturing process of a core layer circuit substrate provided by the technical solution.

9 and 10 are schematic cross-sectional views of an insulating substrate provided by the present technical solution.

Figure 11 is a schematic cross-sectional view of a support plate provided by the present technical solution.

12 is a schematic cross-sectional view of a dielectric film provided by the present technical solution.

FIG. 13 is a cross-sectional view showing the stacking of the core circuit substrate, the insulating substrate, the support plate, and the dielectric film in a stacked structure.

FIG. 14 is a schematic cross-sectional view showing the two circuit boards obtained by pressing the stacked structure.

Fig. 15 is a schematic cross-sectional view showing the separation of two circuit boards from a support plate.

Fig. 16 is a schematic cross-sectional view showing a through hole and a blind hole in a circuit board.

17 is a schematic cross-sectional view showing the first outer conductive layer and the second outer conductive layer formed on opposite surfaces of the circuit substrate.

18 is a schematic cross-sectional view showing the circuit board of FIG. 17 with the peelable protective layer removed.

FIG. 19 is a cross-sectional view of a carrier circuit board provided by the technical solution.

20 is a schematic cross-sectional view of a package structure provided by the present technical solution.

10. . . Core circuit substrate

31. . . First insulating substrate

41. . . First dielectric film

411. . . Second electrical contact pad

421. . . Third electrical contact pad

430. . . First solder mask

431. . . First opening

440. . . Second solder mask

441. . . Second opening

123. . . First protective layer

450. . . Second protective layer

460. . . Third protective layer

100. . . Bearer board

Claims (16)

A method for manufacturing a carrier circuit board, comprising the steps of:
Providing a core circuit substrate, the core circuit substrate includes a glass substrate, a plurality of first electrical contact pads, and a peelable protective layer, wherein the glass substrate is provided with a plurality of metal conductive pillars, and the first electrical contact The pad is electrically connected to the corresponding metal conductive pillar, and the peelable protective layer is formed on the surface of the first electrical contact pad;
Providing a support plate, an insulating substrate, and a dielectric film, wherein the insulating substrate is formed with an opening corresponding to a shape of the core circuit substrate, wherein the opening has a cross-sectional area larger than a cross-sectional area of the core circuit substrate;
The core circuit substrate and the insulating substrate are disposed on one side of the support plate such that the peelable protective layer is in contact with the support plate, the core circuit substrate is received in the opening, and the dielectric film is located in the core a layer circuit substrate and an insulating substrate away from a side of the support plate to form a stacked structure;
Pressing the stacked structure such that a portion of the dielectric film is filled into the opening to connect the core circuit substrate and the insulating substrate, and the dielectric film, the core circuit substrate and the insulating substrate together constitute a circuit substrate;
Separating the support plate from the circuit substrate;
Forming a plurality of second electrical contact pads on a surface of the insulating substrate away from the dielectric film, forming a second outer conductive layer on a surface of the dielectric film away from the insulating substrate; and removing the peelable The protective layer forms a receiving slot, and the first electrical contact pad is exposed from the bottom of the receiving slot to obtain a carrying circuit board. The method of fabricating a carrier circuit board according to claim 1, wherein when the first outer conductive layer and the second outer conductive layer are formed, a conductive via is formed in the dielectric film and the insulating substrate. The first outer conductive layer and the second conductive layer are electrically connected to each other through the conductive via. The method of fabricating a carrier circuit board according to claim 1, wherein, when the first outer conductive layer and the second outer conductive layer are formed, a conductive circuit layer of the conductive core circuit substrate and a second layer are further formed Conductive blind hole of the outer conductive circuit layer. The method of fabricating a carrier circuit board according to claim 1, wherein the thickness of the insulating substrate is greater than the thickness of the core circuit substrate. The method for fabricating a carrier circuit board according to claim 1, further comprising forming a protective layer on the surfaces of the first electrical contact pad and the second electrical contact pad. The method of fabricating a carrier circuit board according to claim 1, wherein the surface of the support plate has a release film. The method of fabricating a carrier circuit board according to claim 1, wherein the core circuit substrate further includes a first insulating layer formed on a surface of the glass substrate and covering the first conductive line The first electrical contact pad is formed on a side surface of the first insulating layer away from the glass substrate, and the first electrical contact pad is electrically connected to the first conductive circuit layer through the first insulating layer. The method of fabricating a carrier circuit board according to claim 7, wherein the fabricating the core circuit substrate comprises the steps of:
Providing a glass substrate having opposite first and second surfaces, and forming a plurality of first blind holes in the glass substrate from the first surface side;
Forming a metal conductive pillar in the plurality of first blind holes;
Forming a first conductive circuit layer on the first surface of the glass substrate, the metal conductive pillar and the first conductive circuit layer being electrically connected to each other;
Forming a first insulating layer on a surface of the first conductive circuit layer, and forming a plurality of openings in the first insulating layer;
Thinning the glass substrate such that the other end of each of the metal conductive pillars is exposed from the second surface side of the glass substrate;
Forming a plurality of first electrical contact pads on a side of the first insulating layer away from the first conductive line layer; and forming a peelable protective layer on a side of the plurality of first electrical contact pads. A method for manufacturing a carrier circuit board, comprising the steps of:
Providing two core circuit substrates, each of the core circuit substrates includes a glass substrate, a plurality of first electrical contact pads, and a peelable protective layer, wherein the glass substrate is provided with a plurality of metal conductive pillars, An electrical contact pad is electrically connected to the corresponding metal conductive pillar, and the peelable protective layer is formed on the surface of the first electrical contact pad;
Providing a support plate, two insulating substrates and two dielectric films, each of the insulating substrates is formed with an opening corresponding to a shape of the core circuit substrate, and the cross-sectional area of the opening is larger than the horizontal of the core circuit substrate Cross-sectional area
One core circuit substrate and one insulating substrate are disposed on one side of the support plate, and the other core circuit substrate and another insulating substrate are disposed on the other side of the support plate such that the peelable protective layer is in contact with the support plate The core circuit substrate is received in the opening, and the dielectric film is located on a side of the core circuit substrate and the insulating substrate away from the support plate to form a stacked structure;
Pressing the stacked structure, a part of the dielectric film is filled into the opening to connect the core circuit substrate and the insulating substrate, and each of the dielectric film, the core circuit substrate and the insulating substrate together form a circuit substrate;
Separating the support plate and the two circuit substrates;
Forming a plurality of second electrical contact pads on the surface of the insulating substrate of the circuit substrate away from the dielectric film, and forming a plurality of two outer conductive layer on the surface of the dielectric film away from the insulating substrate; And removing each of the peelable protective layers to form a receiving slot, the first electrical contact pads being exposed from the bottom of the receiving slot to obtain two carrying circuit boards. A carrier circuit board comprising a core circuit substrate, an insulating substrate, a dielectric film, a first outer conductive layer and a second outer conductive layer, the core circuit substrate comprising a glass substrate and a plurality of first electrical contacts a plurality of metal conductive pillars disposed in the glass substrate, wherein the first electrical contact pads are electrically connected to one end of a corresponding metal conductive pillar, and the insulating substrate has an opening corresponding to the core circuit substrate The cross-sectional area of the first opening is larger than the cross-sectional area of the core circuit substrate, the core circuit substrate is received in the opening, and the dielectric film is connected to the side of the core circuit substrate and the insulating substrate a surface formed in the opening to fill a gap between the insulating substrate and the core circuit substrate, wherein the first outer conductive layer is formed on the surface of the insulating substrate away from the dielectric film, and the second outer conductive layer Formed on the surface of the dielectric film, the carrier circuit board has a receiving groove, and the first electrical contact pad of the core circuit substrate is exposed from the receiving groove. The carrying circuit board of claim 10, wherein the dielectric film is formed with conductive blind holes, and the other end of each of the metal conductive posts is electrically connected to the second outer conductive line through the conductive blind holes. The carrier circuit board of claim 10, wherein a conductive via is formed in the insulating substrate and the dielectric film, and the first outer conductive layer and the second outer conductive layer pass through the conductive The hole is electrically connected. The carrier circuit board of claim 10, wherein the thickness of the insulating substrate is greater than the thickness of the core circuit substrate. The carrier circuit board according to claim 10, wherein the surface of the first electrical contact pad is formed with a protective layer. A package structure comprising a first wafer and a carrier circuit board according to any one of claims 8 to 11, wherein the first wafer is interconnected with a first electrical contact pad in the receiving groove by a first solder ball. The package structure of claim 15, further comprising a connection substrate and a second wafer, wherein the second chip is packaged on the connection substrate, and the connection substrate passes through the second solder ball and the second outer conductive layer layer Electrical connection.