TWI465171B - Package circuit board, method for manufacturing asme, and package structure - Google Patents
Package circuit board, method for manufacturing asme, and package structure Download PDFInfo
- Publication number
- TWI465171B TWI465171B TW101150353A TW101150353A TWI465171B TW I465171 B TWI465171 B TW I465171B TW 101150353 A TW101150353 A TW 101150353A TW 101150353 A TW101150353 A TW 101150353A TW I465171 B TWI465171 B TW I465171B
- Authority
- TW
- Taiwan
- Prior art keywords
- substrate
- layer
- conductive
- electrical contact
- core circuit
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
本發明涉及電路板製作領域,尤其涉及一種承載電路板、承載電路板的製作方法及封裝結構。The present invention relates to the field of circuit board manufacturing, and in particular, to a carrier circuit board, a manufacturing method of the carrier circuit board, and a package structure.
印刷電路板因具有裝配密度高等優點而得到了廣泛的應用。關於電路板的應用請參見文獻Takahashi, A. Ooki, N. Nagai, A. Akahoshi, H. Mukoh, A. Wajima, M. Res. Lab, High density multilayer printed circuit board for HITAC M-880,IEEE Trans. on Components, Packaging, and Manufacturing Technology, 1992, 15(4): 1418-1425。常見的電路板的外層導電線路的焊盤暴露在電路板的同一側,且暴露於同一側的焊盤處於同一平面上。當晶片構裝於暴露在外的焊盤上時,焊盤均位於晶片的下方,從而增加了具有晶片的電路板的高度,擴大了具有晶片的電路板的體積。Printed circuit boards have been widely used due to their high assembly density. For application of the board, please refer to the literature Takahashi, A. Ooki, N. Nagai, A. Akahoshi, H. Mukoh, A. Wajima, M. Res. Lab, High density multilayer printed circuit board for HITAC M-880, IEEE Trans On Components, Packaging, and Manufacturing Technology, 1992, 15(4): 1418-1425. The pads of the outer conductive traces of a common board are exposed on the same side of the board, and the pads exposed on the same side are on the same plane. When the wafer is mounted on the exposed pad, the pad is located below the wafer, thereby increasing the height of the board having the wafer and expanding the volume of the board having the wafer.
有鑑於此,提供一種承載電路板、承載電路板的製作方法及封裝結構,可以得到具有收容槽的電路板,以使得採用所述電路板形成封裝結構時,至少部分晶片收容於所述收容槽中,從而減少封裝結構的厚度,縮小封裝結構的體積實屬必要。In view of the above, a carrier circuit board, a manufacturing method of the carrier circuit board, and a package structure are provided, and a circuit board having a receiving slot can be obtained, so that at least part of the chip is received in the receiving slot when the circuit board is formed into the package structure. Therefore, it is necessary to reduce the thickness of the package structure and reduce the size of the package structure.
一種承載電路板的製作方法,包括步驟:提供芯層電路基板,所述芯層電路基板包括玻璃基底、多個第一電性接觸墊及可剝離保護層,所述玻璃基板內設置有多個金屬導電柱,所述第一電性接觸墊與對應的金屬導電柱相互電連接,所述可剝離保護層形成於第一電性接觸墊表面;提供支撐板、絕緣基板及介電膠片,所述絕緣基板內形成有與芯層電路基板形狀對應的開孔,所述開孔的橫截面積大於芯層電路基板的橫截面積;將芯層電路基板及絕緣基板設置於支撐板的一側,使得所述可剝離保護層與支撐板相接觸,所述芯層電路基板收容於所述開孔內,所述介電膠片位於芯層電路基板及絕緣基板遠離支撐板的一側,形成堆疊結構;壓合所述堆疊結構,使得部分介電膠片填充至開孔內以連接芯層電路基板及絕緣基板,所述介電膠片、芯層電路基板及絕緣基板共同構成電路基板;分離所述支撐板與電路基板;在所述絕緣基板遠離所述介電膠片的表面形成多個第二電性接觸墊,在所述介電膠片遠離所述絕緣基板的表面形成第二外層導電線路層;以及去除所述可剝離保護層,形成一收容槽,所述第一電性接觸墊從所述收容槽底部露出,得到承載電路板。A method for manufacturing a carrier circuit board includes the steps of: providing a core circuit substrate, the core circuit substrate comprising a glass substrate, a plurality of first electrical contact pads, and a peelable protective layer, wherein the plurality of glass substrates are disposed a metal conductive pillar, the first electrical contact pad and the corresponding metal conductive pillar are electrically connected to each other, the peelable protective layer is formed on the surface of the first electrical contact pad; and the support plate, the insulating substrate and the dielectric film are provided; An opening corresponding to the shape of the core circuit substrate is formed in the insulating substrate, the cross-sectional area of the opening is larger than the cross-sectional area of the core circuit substrate; and the core circuit substrate and the insulating substrate are disposed on one side of the support plate The peelable protective layer is in contact with the support plate, the core circuit substrate is received in the opening, and the dielectric film is located on a side of the core circuit substrate and the insulating substrate away from the support plate to form a stack a structure; pressing the stacked structure such that a portion of the dielectric film is filled into the opening to connect the core circuit substrate and the insulating substrate, the dielectric film, the core circuit substrate, and the insulating substrate Forming a circuit substrate together; separating the support plate from the circuit substrate; forming a plurality of second electrical contact pads on a surface of the insulating substrate away from the dielectric film, the surface of the dielectric film being away from the insulating substrate Forming a second outer conductive layer; and removing the peelable protective layer to form a receiving groove, the first electrical contact pad is exposed from the bottom of the receiving groove to obtain a carrying circuit board.
一種承載電路板,其包括芯層電路基板、絕緣基板、介電膠片、第一外層導電線路層及第二外層導電線路層,所述芯層電路基板包括玻璃基底及多個第一電性接觸墊,所述玻璃基板內設置有多個金屬導電柱,所述第一電性接觸墊與對應的金屬導電柱一端相互電連接,所述絕緣基板內具有與芯層電路基板相對應的開孔,第一開孔的橫截面積大於芯層電路基板的橫截面積,所述芯層電路基板收容於所述開孔內,所述介電膠片連接於芯層電路基板及絕緣基板的一側表面,並形成於開孔內,以填充絕緣基板與芯層電路基板之間的空隙,所述第一外層導電線路層形成於絕緣基板遠離介電膠片的表面,所述第二外層導電線路層形成於介電膠片的表面,承載電路板具有收容槽,所述芯層電路基板的第一電性接觸墊從所述收容槽露出。A carrier circuit board comprising a core circuit substrate, an insulating substrate, a dielectric film, a first outer conductive layer and a second outer conductive layer, the core circuit substrate comprising a glass substrate and a plurality of first electrical contacts a plurality of metal conductive pillars disposed in the glass substrate, wherein the first electrical contact pads are electrically connected to one end of a corresponding metal conductive pillar, and the insulating substrate has an opening corresponding to the core circuit substrate The cross-sectional area of the first opening is larger than the cross-sectional area of the core circuit substrate, the core circuit substrate is received in the opening, and the dielectric film is connected to the side of the core circuit substrate and the insulating substrate a surface formed in the opening to fill a gap between the insulating substrate and the core circuit substrate, wherein the first outer conductive layer is formed on the surface of the insulating substrate away from the dielectric film, and the second outer conductive layer Formed on the surface of the dielectric film, the carrier circuit board has a receiving groove, and the first electrical contact pad of the core circuit substrate is exposed from the receiving groove.
一種封裝結構,其包括第一晶片及所述的承載電路板,所述第一晶片通過第一焊球與收容槽內的第一電性接觸墊相互連接。A package structure includes a first wafer and the carrier circuit board, the first wafer being interconnected with a first electrical contact pad in the receiving slot by a first solder ball.
本技術方案提供的電路板及其製作方法,先提供一個具有第一導電線路圖形的芯層電路基板及一個形成有開孔的絕緣基板,然後採用介電膠片將芯層電路基板及絕緣基板相互連接,而後再製作形成外層導電線路層。由於芯層電路基板內的導電線路與外層的導電線路分開製作,可以使得芯層電路基板的導電線路採用細線路,而外層的導電線路可以採用相對較粗的線路,不僅實現了細線路電路板的功能,而且避免了在無需形成細線路區域仍需要技術複雜且制程昂貴的細線路製作技術來形成導電線路的可能,減少了電路板的製作工藝,降低了電路板的製成成本。另外,在製作過程中,採用的絕緣基板的厚度大於芯層電路基板的厚度,當芯層電路基板收容於絕緣基板的開孔後,形成一個收容槽。所述的電路承載板在進行封裝時,可以使得封裝於其上的晶片部分或者全部收容於所述收容槽內,從而可以減小封裝後的封裝結構的尺寸。The circuit board and the manufacturing method thereof provided by the technical solution first provide a core circuit substrate having a first conductive line pattern and an insulating substrate formed with an opening, and then the core circuit substrate and the insulating substrate are mutually exchanged by using a dielectric film The connection is then made to form an outer conductive layer. Since the conductive lines in the core circuit substrate are separately formed from the conductive lines of the outer layer, the conductive lines of the core circuit substrate can be made thin, and the conductive lines of the outer layer can be relatively thick, not only the thin circuit board is realized. The function, and avoiding the need of forming a thin circuit area, still requires a complicated circuit manufacturing process and forming a conductive circuit, thereby reducing the manufacturing process of the circuit board and reducing the manufacturing cost of the circuit board. In addition, in the manufacturing process, the thickness of the insulating substrate used is larger than the thickness of the core circuit substrate, and when the core circuit substrate is received in the opening of the insulating substrate, a receiving groove is formed. When the circuit board is packaged, part or all of the wafers packaged thereon can be received in the receiving groove, so that the size of the package structure after packaging can be reduced.
進一步地,現有技術中採用塑膠作為芯層電路基板的基底由於芯層電路基板,而晶片通常採用矽製成。由於塑膠的熱膨脹係數與矽的熱膨脹係數相差較大,在將晶片封裝時,易於造成由於漲縮不一致而導致的品質問題。本技術方案中,芯層電路基板採用玻璃基底,玻璃的熱膨脹係數與矽相差較小,從而可以提高形成的封裝結構的品質。Further, the prior art uses plastic as the substrate of the core circuit substrate because of the core circuit substrate, and the wafer is usually made of tantalum. Since the thermal expansion coefficient of the plastic differs greatly from the thermal expansion coefficient of the crucible, when the wafer is packaged, it is easy to cause quality problems due to inconsistent expansion and contraction. In the technical solution, the core circuit substrate is made of a glass substrate, and the thermal expansion coefficient of the glass is less than that of the germanium, so that the quality of the formed package structure can be improved.
本技術方案以具體實施例對本技術方案提供的電路板、電路板製作方法及封裝結構進行詳細說明。The technical solution provides a detailed description of the circuit board, the circuit board manufacturing method and the package structure provided by the technical solution according to specific embodiments.
本技術方案提供的電路板的製作方法包括如下步驟:The manufacturing method of the circuit board provided by the technical solution includes the following steps:
第一步,請參閱圖1,提供兩個芯層電路基板10。In the first step, referring to FIG. 1, two core circuit substrates 10 are provided.
所述芯層電路基板10包括玻璃基板11、第一導電線路層12、第一絕緣層14、多個第一電性接觸墊15及可剝離保護層13。The core layer circuit substrate 10 includes a glass substrate 11 , a first conductive wiring layer 12 , a first insulating layer 14 , a plurality of first electrical contact pads 15 , and a peelable protective layer 13 .
玻璃基板11具有相對的第一表面113和第二表面114。所述玻璃基板11的厚度為100微米至500微米。所述第一導電線路層12形成於玻璃基板11的第一表面113。所述玻璃基板11內形成有貫穿玻璃基板11的多個第一通孔111,每個第一通孔111內形成有填充對應第一通孔111的金屬導電柱112。每個金屬導電柱112的一端與第一導電線路層12相互電連接。每個金屬導電柱112的另一端與玻璃基板11的第二表面114平齊。相鄰的金屬導電柱112之間的間距可以為100微米至200微米之間。The glass substrate 11 has opposing first and second surfaces 113, 114. The glass substrate 11 has a thickness of from 100 micrometers to 500 micrometers. The first conductive wiring layer 12 is formed on the first surface 113 of the glass substrate 11. A plurality of first through holes 111 penetrating through the glass substrate 11 are formed in the glass substrate 11 , and a metal conductive pillar 112 filling the corresponding first through holes 111 is formed in each of the first through holes 111 . One end of each of the metal conductive pillars 112 is electrically connected to the first conductive wiring layer 12. The other end of each of the metal conductive pillars 112 is flush with the second surface 114 of the glass substrate 11. The spacing between adjacent metal conductive pillars 112 can be between 100 microns and 200 microns.
所述第一絕緣層14形成於玻璃基板11的第一表面113一側,並覆蓋所述第一導電線路層12。所述第一電性接觸墊15形成於第一絕緣層14遠離玻璃基板11的一側表面。所述第一絕緣層14內形成有多個導電孔141,第一導電線路層12及第一電性接觸墊15通過所述導電孔141相互電導通。相鄰的第一電性接觸墊15之間的間距為50微米至100微米。The first insulating layer 14 is formed on the first surface 113 side of the glass substrate 11 and covers the first conductive wiring layer 12 . The first electrical contact pad 15 is formed on a side surface of the first insulating layer 14 away from the glass substrate 11 . A plurality of conductive holes 141 are formed in the first insulating layer 14 , and the first conductive circuit layer 12 and the first electrical contact pads 15 are electrically connected to each other through the conductive holes 141 . The spacing between adjacent first electrical contact pads 15 is between 50 microns and 100 microns.
所述可剝離保護層13覆蓋所述第一電性接觸墊15,以防止所述第一電性接觸墊15在後續的製作步驟中被損壞。所述可剝離保護層13可以為聚丙烯薄膜、聚乙烯薄膜或者聚對苯二甲酸乙二醇酯等高分子薄膜。優選地,本實施方式中,所述可剝離保護層13為聚對苯二甲酸乙二醇酯薄膜。所述可剝離保護層13也可以為其他業界常用的可剝離膜或者可剝離膠。The peelable protective layer 13 covers the first electrical contact pad 15 to prevent the first electrical contact pad 15 from being damaged in a subsequent fabrication step. The peelable protective layer 13 may be a polymer film such as a polypropylene film, a polyethylene film, or a polyethylene terephthalate. Preferably, in the embodiment, the peelable protective layer 13 is a polyethylene terephthalate film. The peelable protective layer 13 can also be a peelable film or a peelable adhesive commonly used in other industries.
請一併參閱圖1至圖8,所述芯層電路基板10的可以採用如下方法製作:Referring to FIG. 1 to FIG. 8 together, the core circuit substrate 10 can be fabricated as follows:
首先,提供玻璃基板11,並在玻璃基板11內形成多個與第一通孔111一一對應的多個第一盲孔1111。First, a glass substrate 11 is provided, and a plurality of first blind holes 1111 that are in one-to-one correspondence with the first through holes 111 are formed in the glass substrate 11.
本步驟可以採用如下方法實現:先在玻璃基板11的第一表面113印刷形成光阻層,然後經過曝光及顯影形成阻擋圖形115。再採用噴沙、超聲波鑽孔或者濕蝕刻的方式,在未被阻擋圖形115遮蔽的玻璃基板11的第一表面113一側形成多個第一盲孔1111。所述多個第一盲孔1111的孔徑小於50微米。This step can be achieved by first forming a photoresist layer on the first surface 113 of the glass substrate 11, and then forming a barrier pattern 115 by exposure and development. A plurality of first blind holes 1111 are formed on the first surface 113 side of the glass substrate 11 not blocked by the barrier pattern 115 by sandblasting, ultrasonic drilling or wet etching. The plurality of first blind vias 1111 have a pore size of less than 50 microns.
然後,在所述多個第一盲孔1111內形成金屬導電柱112。Then, a metal conductive pillar 112 is formed in the plurality of first blind holes 1111.
本步驟具體為,先採用濺鍍或者蒸鍍的方式,在第一盲孔1111的內壁及第一表面113形成沉積銅層,再採用電鍍的方式,在第一盲孔1111內形成金屬導電柱112,並在第一表面113形成一導電層。之後,採用化學機械平坦化的方式,將第一表面113的第一導電層去除。Specifically, in this step, a copper layer is formed on the inner wall of the first blind via 1111 and the first surface 113 by sputtering or evaporation, and metal conduction is formed in the first blind via 1111 by electroplating. The pillar 112 forms a conductive layer on the first surface 113. Thereafter, the first conductive layer of the first surface 113 is removed by chemical mechanical planarization.
接著,在玻璃基板11的第一表面113形成第一導電線路層12。所述第一導電線路層12可以採用化學鍍然後電鍍的方式形成。第一導電線路層12與金屬導電柱112相互電連接。Next, a first conductive wiring layer 12 is formed on the first surface 113 of the glass substrate 11. The first conductive wiring layer 12 may be formed by electroless plating and then electroplating. The first conductive wiring layer 12 and the metal conductive pillars 112 are electrically connected to each other.
接著,在第一導電線路層12表面形成第一絕緣層14。第一絕緣層14的材料可以為聚醯亞胺。在第一絕緣層14內,形成有多個開口,使得部分第一導電線路層12從開口露出。所述開口的寬度小於或者等於10微米。Next, a first insulating layer 14 is formed on the surface of the first conductive wiring layer 12. The material of the first insulating layer 14 may be polyimide. In the first insulating layer 14, a plurality of openings are formed such that a portion of the first conductive wiring layer 12 is exposed from the opening. The width of the opening is less than or equal to 10 microns.
接著,從第二表面114一側對玻璃基板11進行薄化處理,使得每個金屬導電柱112的另一端從玻璃基板11的第二表面114一側露出。Next, the glass substrate 11 is thinned from the second surface 114 side such that the other end of each of the metal conductive pillars 112 is exposed from the second surface 114 side of the glass substrate 11.
本步驟可以採用打磨的方式,在厚度方向上將部分的玻璃基板11去除。In this step, a part of the glass substrate 11 can be removed in the thickness direction by sanding.
接著,在第一絕緣層14遠離第一導電線路層12一側形成多個第一電性接觸墊15。Next, a plurality of first electrical contact pads 15 are formed on the side of the first insulating layer 14 away from the first conductive wiring layer 12.
所述第一電性接觸墊15的形成包括:先在第一絕緣層14的開口處形成沉積金屬層,所述沉積金屬層可以採用化學沉積的方式形成。所述沉積金屬層可以為鈦、銅或者鎳。然後,在沉積金屬層上形成焊球或者導電膏,從而得到多個第一電性接觸墊15。The forming of the first electrical contact pad 15 includes first forming a deposited metal layer at the opening of the first insulating layer 14, and the deposited metal layer may be formed by chemical deposition. The deposited metal layer may be titanium, copper or nickel. Then, a solder ball or a conductive paste is formed on the deposited metal layer, thereby obtaining a plurality of first electrical contact pads 15.
最後,在多個第一電性接觸墊15一側形成可剝離保護層13。Finally, a peelable protective layer 13 is formed on one side of the plurality of first electrical contact pads 15.
第二步,請一併參閱圖9至圖12,提供第一絕緣基板31、第二絕緣基板32、支撐板20、第一介電膠片41和第二介電膠片42。In the second step, referring to FIG. 9 to FIG. 12, a first insulating substrate 31, a second insulating substrate 32, a support plate 20, a first dielectric film 41, and a second dielectric film 42 are provided.
第一絕緣基板31和第二絕緣基板32採用絕緣材料製作,其可以為硬性材料,也可以為軟性材料製成。The first insulating substrate 31 and the second insulating substrate 32 are made of an insulating material, and may be made of a hard material or a soft material.
第一絕緣基板31內形成有在厚度方向上貫穿第一絕緣基板31的第一開孔33。第一開孔33與芯層電路基板10相對應。第一開孔33的形狀與芯層電路基板10的形狀相同,第一開孔33的橫截面積大於芯層電路基板10的橫截面積。A first opening 33 penetrating the first insulating substrate 31 in the thickness direction is formed in the first insulating substrate 31. The first opening 33 corresponds to the core circuit substrate 10. The shape of the first opening 33 is the same as that of the core circuit substrate 10, and the cross-sectional area of the first opening 33 is larger than the cross-sectional area of the core circuit substrate 10.
第二絕緣基板32內形成有在厚度方向上貫穿第二絕緣基板32的第二開孔34。第二開孔34與芯層電路基板10相對應。第二開孔34的形狀與芯層電路基板10的形狀相同,第二開孔34的橫截面積大於芯層電路基板10的橫截面積。A second opening 34 penetrating the second insulating substrate 32 in the thickness direction is formed in the second insulating substrate 32. The second opening 34 corresponds to the core circuit substrate 10. The shape of the second opening 34 is the same as that of the core circuit substrate 10, and the cross-sectional area of the second opening 34 is larger than the cross-sectional area of the core circuit substrate 10.
優選地,第一絕緣基板31和第二絕緣基板32的厚度與芯層電路基板10的厚度相等。Preferably, the thicknesses of the first insulating substrate 31 and the second insulating substrate 32 are equal to the thickness of the core layer circuit substrate 10.
支撐板20包括本體20a及形成於本體20a相對兩表面的離型膜201。所述離型膜201可以為聚丙烯薄膜、聚乙烯薄膜以及聚對苯二甲酸乙二醇酯等高分子薄膜,優選為聚對苯二甲酸乙二醇酯薄膜,本實施例中即採用聚對苯二甲酸乙二醇酯薄膜作為所述離型膜201。所述離型膜201也可以為其他業界常用的離型紙。The support plate 20 includes a body 20a and a release film 201 formed on opposite surfaces of the body 20a. The release film 201 may be a polymer film such as a polypropylene film, a polyethylene film or a polyethylene terephthalate, and is preferably a polyethylene terephthalate film. In this embodiment, a poly film is used. A polyethylene terephthalate film is used as the release film 201. The release film 201 can also be a release paper commonly used in other industries.
第一介電膠片41和第二介電膠片42可以為本技術領域常見的半固化膠片。The first dielectric film 41 and the second dielectric film 42 may be semi-cured films that are common in the art.
第三步,請參閱圖13,將兩個芯層電路基板10分別設置於支撐板20的相對兩側,芯層電路基板10的可剝離保護層13的一側表面貼於支撐板20表面,並將第一絕緣基板31和第二絕緣基板32分別設置於支撐板20的相對兩側,並使得一個芯層電路基板10位於第一絕緣基板31的第一開孔33內,另一個芯層電路基板10位於第二絕緣基板32的第二開孔34內,第一介電膠片41位於一個芯層電路基板10及第一絕緣基板31遠離支撐板20的一側,第二介電膠片42位於另一芯層電路基板10及第二絕緣基板32遠離支撐板20的一側,形成堆疊結構101。In the third step, referring to FIG. 13 , the two core circuit substrates 10 are respectively disposed on opposite sides of the support board 20 , and one surface of the peelable protective layer 13 of the core circuit substrate 10 is attached to the surface of the support board 20 . The first insulating substrate 31 and the second insulating substrate 32 are respectively disposed on opposite sides of the support board 20, and one core circuit substrate 10 is located in the first opening 33 of the first insulating substrate 31, and the other core layer The circuit substrate 10 is located in the second opening 34 of the second insulating substrate 32. The first dielectric film 41 is located on a side of the core circuit substrate 10 and the first insulating substrate 31 away from the support board 20, and the second dielectric film 42 is disposed. On the side of the other core layer circuit substrate 10 and the second insulating substrate 32 away from the support plate 20, a stacked structure 101 is formed.
第四步,請參閱圖14,壓合所述堆疊結構101,使得第一介電膠片41填充至第一開孔33內,使得芯層電路基板10與第一絕緣基板31之間的空隙被第一介電膠片41填充,從而第一介電膠片41、第一絕緣基板31及位於第一開孔33內的芯層電路基板10成為一個電路基板103。並使得第二介電膠片42填充至第二開孔34內,使得芯層電路基板10與第二絕緣基板32之間的空隙被第二介電膠片42填充,從而第二介電膠片42、第二絕緣基板32及位於第二開孔34內的芯層電路基板10成為另一個電路基板103。In the fourth step, referring to FIG. 14, the stacked structure 101 is pressed such that the first dielectric film 41 is filled into the first opening 33, so that the gap between the core circuit substrate 10 and the first insulating substrate 31 is The first dielectric film 41 is filled so that the first dielectric film 41, the first insulating substrate 31, and the core circuit substrate 10 located in the first opening 33 become a circuit substrate 103. And filling the second dielectric film 42 into the second opening 34, so that the gap between the core circuit substrate 10 and the second insulating substrate 32 is filled by the second dielectric film 42, so that the second dielectric film 42 The second insulating substrate 32 and the core layer circuit substrate 10 located in the second opening 34 become the other circuit substrate 103.
在壓合過程中,在高溫高壓狀態下,第一介電膠片41和第二介電膠片42可以產生流動。第一介電膠片41和第二介電膠片42的材料可以為聚醯亞胺(Polyimide, PI)、聚乙烯對苯二甲酸乙二醇酯(Polyethylene Terephthalate, PET)或聚萘二甲酸乙二醇酯(Polyethylene naphthalate,PEN) 、PP (Prepreg)或ABF (Ajinomoto Build-up film)等,優選為PP或ABF。During the press-fitting process, the first dielectric film 41 and the second dielectric film 42 may flow in a high temperature and high pressure state. The material of the first dielectric film 41 and the second dielectric film 42 may be Polyimide (PI), polyethylene terephthalate (PET) or polyethylene naphthalate. Polyethylene naphthalate (PEN), PP (Prepreg) or ABF (Ajinomoto Build-up film) or the like is preferably PP or ABF.
第五步,請一併參閱圖15,將兩個電路基板103與支撐板20相互分離。In the fifth step, referring to FIG. 15, the two circuit substrates 103 and the support plate 20 are separated from each other.
由於支撐板20表面具有離型膜201,電路基板103可以容易地與支撐板20相互分離。Since the surface of the support plate 20 has the release film 201, the circuit substrate 103 can be easily separated from the support plate 20.
由於後續的製作步驟相同,以下僅以一個電路基板103的後續製作為例來進行說明。Since the subsequent fabrication steps are the same, only the subsequent fabrication of one circuit substrate 103 will be described below as an example.
第六步,請參閱圖16,在電路基板103的所述第一介電膠片41及第一絕緣基板31中形成至少一個第二通孔311,在所述第一介電膠片41形成多個第二盲孔312,使得金屬導電柱112從對應的第二盲孔312露出。In the sixth step, referring to FIG. 16, at least one second through hole 311 is formed in the first dielectric film 41 and the first insulating substrate 31 of the circuit substrate 103, and a plurality of the first dielectric film 41 are formed. The second blind via 312 exposes the metal conductive pillars 112 from the corresponding second blind vias 312.
本步驟中,所述第二通孔311及第二盲孔312均可以採用鐳射燒蝕的方式形成。所述第二通孔311貫穿所述第一介電膠片41及第一絕緣基板31。第二通孔311也可以採用機械鑽孔的方式形成。第二通孔311的個數可以為一個,也可以為多個。圖4中以形成兩個第二通孔311為例進行說明。所述第二盲孔312僅貫穿所述第一介電膠片41,並暴露出金屬導電柱112。第二盲孔312的個數可以為一個,也可以為多個,圖4中以形成兩個第二盲孔312為例進行說明。In this step, the second through hole 311 and the second blind hole 312 can be formed by laser ablation. The second through hole 311 extends through the first dielectric film 41 and the first insulating substrate 31 . The second through hole 311 can also be formed by mechanical drilling. The number of the second through holes 311 may be one or plural. In FIG. 4, two second through holes 311 are formed as an example for description. The second blind via 312 extends only through the first dielectric film 41 and exposes the metal conductive pillars 112. The number of the second blind holes 312 may be one or plural, and the two second blind holes 312 are formed as an example in FIG. 4 .
可以理解的是,在此步驟之後,還可以進一步包括去膠渣(desmear)的步驟,以將第二通孔311及第二盲孔312內部的膠渣去除,從而可以有效地防止在後續進行電鍍時,膠渣影響形成的導電孔的導電性。It can be understood that after this step, the step of desmear may be further included to remove the glue inside the second through hole 311 and the second blind hole 312, thereby effectively preventing subsequent processing. When electroplating, the slag affects the conductivity of the formed conductive holes.
第五步,請一併參閱圖17,在第一絕緣基板31的的表面形成第一外層導電線路層410,在第一介電膠片41的表面形成第二外層導電線路層420。所述第一外層導電線路層410包括多個與外界進行電連接的第二電性接觸墊411及多條導電線路(圖未示)。第二外層導電線路層420包括多個用於與外界進行電連接的第三電性接觸墊421及多條導電線路。In the fifth step, referring to FIG. 17, a first outer conductive layer 410 is formed on the surface of the first insulating substrate 31, and a second outer conductive layer 420 is formed on the surface of the first dielectric film 41. The first outer conductive layer 410 includes a plurality of second electrical contact pads 411 electrically connected to the outside and a plurality of conductive lines (not shown). The second outer conductive layer 420 includes a plurality of third electrical contact pads 421 for electrically connecting to the outside and a plurality of conductive lines.
本步驟具體可採用如下方法:This step can specifically adopt the following methods:
首先,採用化學鍍銅的方式,在第一絕緣基板31的表面及可剝離保護層13上形成第一導電種子層,在第二通孔311內壁、第二盲孔312內壁及第一介電膠片41的表面上形成第二導電種子層。First, a first conductive seed layer is formed on the surface of the first insulating substrate 31 and the peelable protective layer 13 by electroless copper plating, and the inner wall of the second through hole 311, the inner wall of the second blind hole 312, and the first A second conductive seed layer is formed on the surface of the dielectric film 41.
可以理解的是,也可以採用其他方法,如黑化或者化學吸附導電粒子等,在第一絕緣基板31的表面、第二通孔311內壁、第二盲孔312內壁及第一介電膠片41的表面形成第一導電種子層及第二導電種子層。It can be understood that other methods, such as blackening or chemisorption of conductive particles, etc., on the surface of the first insulating substrate 31, the inner wall of the second through hole 311, the inner wall of the second blind hole 312, and the first dielectric may be employed. The surface of the film 41 forms a first conductive seed layer and a second conductive seed layer.
其次,在第一導電種子層和第二導電種子層的表面分別形成光致抗蝕劑層,並採用曝光及顯影的方式,將與欲形成第一外層導電線路層410對應的部分去除得到第一光致抗蝕劑圖形,將與欲形成第二外層導電線路層420對應的部分去除得到第二光致抗蝕劑圖形。Next, a photoresist layer is formed on the surfaces of the first conductive seed layer and the second conductive seed layer, respectively, and the portion corresponding to the first outer conductive layer 410 is formed by exposure and development. A photoresist pattern is removed from the portion corresponding to the second outer conductive wiring layer 420 to obtain a second photoresist pattern.
接著,在從第一光致抗蝕劑圖形的空隙露出的第一導電種子層表面形成第一電鍍銅層,在從第二光致抗蝕劑圖形露出的第二導電種子層表面形成第二電鍍銅層。Next, a first plated copper layer is formed on the surface of the first conductive seed layer exposed from the void of the first photoresist pattern, and a second surface is formed on the surface of the second conductive seed layer exposed from the second photoresist pattern Electroplated copper layer.
最後,採用剝膜的方式去除第一光致抗蝕劑圖形和第二光致抗蝕劑圖形,並採用微蝕的方式去除原被第一光致抗蝕劑圖形覆蓋的第一導電種子層,去除原被第二光致抗蝕劑圖形覆蓋的第二導電種子層。如此,位於第一絕緣基板31表面的第一導電種子層及形成在其上的第一電鍍銅層共同構成第一外層導電線路層410。位於第一介電膠片41表面的第二導電種子層及形成在其上的第二電鍍銅層共同構成第二外層導電線路層420。位於第二通孔311內的第二導電種子層及形成上其上的第二電鍍銅層共同構成貫穿第一介電膠片41及第一絕緣基板31的導電通孔313。位於第二盲孔312內的第二導電種子層及形成上其上的第二電鍍銅層共同構成第二導電盲孔314。所述第一外層導電線路層410及第二外層導電線路層420通過所述導電通孔313相互電連通。第二外層導電線路層420及金屬導電柱112的通過第二導電盲孔314相互電連通。Finally, the first photoresist pattern and the second photoresist pattern are removed by stripping, and the first conductive seed layer originally covered by the first photoresist pattern is removed by microetching. Removing the second conductive seed layer that was originally covered by the second photoresist pattern. Thus, the first conductive seed layer on the surface of the first insulating substrate 31 and the first electroplated copper layer formed thereon collectively constitute the first outer conductive layer 410. A second conductive seed layer on the surface of the first dielectric film 41 and a second electroplated copper layer formed thereon collectively constitute a second outer conductive layer 420. The second conductive seed layer located in the second through hole 311 and the second electroplated copper layer formed thereon constitute a conductive via 313 penetrating through the first dielectric film 41 and the first insulating substrate 31. The second conductive seed layer located in the second blind via 312 and the second electroplated copper layer formed thereon form a second conductive via 314. The first outer conductive layer 410 and the second outer conductive layer 420 are electrically connected to each other through the conductive via 313. The second outer conductive circuit layer 420 and the metal conductive pillars 112 are electrically connected to each other through the second conductive blind vias 314.
第七步,請參閱圖18,採用剝膜的方式去除可剝離保護層13,從而形成一個收容槽102。In the seventh step, referring to FIG. 18, the peelable protective layer 13 is removed by stripping to form a receiving groove 102.
第八步,請參閱圖19,在第一外層導電線路層410的表面及從所述第一外層導電線路層410露出的第一絕緣基板31的表面形成第一防焊層430,在第二外層導電線路層420的表面及從所述第二外層導電線路層420露出的第一介電膠片41的表面形成第二防焊層440。所述第一防焊層430內具有與多個第二電性接觸墊411一一對應的多個第一開口431,每個第二電性接觸墊411從對應的第一開口431露出。所述第二防焊層440內具有與多個第三電性接觸墊421一一對應的多個第二開口441,每個第三電性接觸墊421從對應的第二開口441露出。In the eighth step, referring to FIG. 19, a first solder resist layer 430 is formed on the surface of the first outer conductive layer 410 and the surface of the first insulating substrate 31 exposed from the first outer conductive layer 410, in the second A surface of the outer conductive wiring layer 420 and a surface of the first dielectric film 41 exposed from the second outer conductive wiring layer 420 form a second solder resist layer 440. The first solder resist layer 430 has a plurality of first openings 431 corresponding to the plurality of second electrical contact pads 411 , and each of the second electrical contact pads 411 is exposed from the corresponding first opening 431 . The second solder resist layer 440 has a plurality of second openings 441 corresponding to the plurality of third electrical contact pads 421 , and each of the third electrical contact pads 421 is exposed from the corresponding second opening 441 .
第九步,在第一導電線路層12的每個第一電性接觸墊121的表面形成一個第一保護層123。在每個第二電性接觸墊411從第一開口431露出的表面形成一個第二保護層450。在每個第三電性接觸墊421從第二開口441露出的表面形成一個第三保護層460,得到承載電路板100。In the ninth step, a first protective layer 123 is formed on the surface of each of the first electrical contact pads 121 of the first conductive wiring layer 12. A second protective layer 450 is formed on a surface of each of the second electrical contact pads 411 exposed from the first opening 431. A third protective layer 460 is formed on the surface of each of the third electrical contact pads 421 exposed from the second opening 441 to obtain the carrier circuit board 100.
本實施例中,所述第一保護層123、第二保護層450及第三保護層460可以為錫、鉛、銀、金、鎳、鈀等金屬或其合金的單層結構,也可以為上述金屬中兩種或者兩種以上的多層結構。第一保護層123、第二保護層450及第三保護層460也可以為有機保焊層(OSP)。當第一保護層123及第二保護層450為金屬時,第一保護層123、第二保護層450及第三保護層460可以採用化學鍍的方式形成。當第一保護層123、第二保護層450及第三保護層460為有機保焊層時,第一保護層123、第二保護層450及第三保護層460可以採用化學方法形成。In this embodiment, the first protective layer 123, the second protective layer 450, and the third protective layer 460 may be a single layer structure of a metal such as tin, lead, silver, gold, nickel, palladium or the like, or an alloy thereof. Two or more kinds of multilayer structures of the above metals. The first protective layer 123, the second protective layer 450, and the third protective layer 460 may also be an organic solder resist layer (OSP). When the first protective layer 123 and the second protective layer 450 are metal, the first protective layer 123, the second protective layer 450, and the third protective layer 460 may be formed by electroless plating. When the first protective layer 123, the second protective layer 450, and the third protective layer 460 are organic solder resist layers, the first protective layer 123, the second protective layer 450, and the third protective layer 460 may be formed by a chemical method.
可以理解的是,在本技術方案提供的製作方法中,在第三及第四步中,可以僅在支撐板20的一側設置芯層電路基板10、絕緣基板及介電膠片,即在製作過程中,僅進行一個承載電路板100的製作。It can be understood that, in the manufacturing method provided by the technical solution, in the third and fourth steps, the core circuit substrate 10, the insulating substrate and the dielectric film may be disposed only on one side of the support board 20, that is, in the fabrication. In the process, only one carrier circuit board 100 is fabricated.
在承載電路板100中,由於在前面步驟中的可剝離保護層13被去除,從而承載電路板100具有一個收容槽102,第一電性接觸墊121從所述收容槽102露出。In the carrier circuit board 100, since the peelable protective layer 13 in the previous step is removed, the carrier circuit board 100 has a receiving groove 102 from which the first electrical contact pad 121 is exposed.
請參閱圖19,本技術方案提供一種採用上述方法製作的承載電路板100,其包括芯層電路基板10、第一絕緣基板31、第一介電膠片41、第一外層導電線路層410及第二外層導電線路層420。Referring to FIG. 19 , the technical solution provides a carrier circuit board 100 fabricated by the above method, including a core circuit substrate 10 , a first insulating substrate 31 , a first dielectric film 41 , a first outer conductive layer 410 , and a first Two outer conductive circuit layers 420.
所述第一絕緣基板31內具有與芯層電路基板10相對應的第一開孔33,第一開孔33的橫截面積大於芯層電路基板10的橫截面積。所述芯層電路基板10收容於所述第一開孔33內。所述第一介電膠片41連接於芯層電路基板10及第一絕緣基板31的一側表面,並形成於第一開孔33內,以填充第一絕緣基板31與芯層電路基板10之間的空隙,使得第一絕緣基板31、芯層電路基板10及第一介電膠片41成為一個整體。The first insulating substrate 31 has a first opening 33 corresponding to the core circuit substrate 10, and the first opening 33 has a cross-sectional area larger than that of the core circuit substrate 10. The core layer circuit substrate 10 is received in the first opening 33. The first dielectric film 41 is connected to one side surface of the core circuit substrate 10 and the first insulating substrate 31, and is formed in the first opening 33 to fill the first insulating substrate 31 and the core circuit substrate 10. The gap between the first insulating substrate 31, the core circuit substrate 10, and the first dielectric film 41 is integrated.
所述第一外層導電線路層410形成於第一絕緣基板31遠離第一介電膠片41的表面。所述第二外層導電線路層420形成於第一介電膠片41的表面。第一絕緣基板31內形成有至少一個第二導電通孔313,所述第一外層導電線路層410與第二外層導電線路層420通過所述導電通孔313相互電導通。The first outer conductive layer 410 is formed on a surface of the first insulating substrate 31 away from the first dielectric film 41. The second outer conductive layer 420 is formed on the surface of the first dielectric film 41. At least one second conductive via 313 is formed in the first insulating substrate 31, and the first outer conductive layer 410 and the second outer conductive layer 420 are electrically connected to each other through the conductive via 313.
第一絕緣基板31的厚度大於所述芯層電路基板10的厚度,在第一外層導電線路層410一側,承載電路板100具有收容槽102。所述芯層電路基板的第一電性接觸墊151從所述收容槽102露出。The thickness of the first insulating substrate 31 is larger than the thickness of the core circuit substrate 10. On the side of the first outer conductive layer 410, the carrier circuit board 100 has a receiving groove 102. The first electrical contact pads 151 of the core circuit substrate are exposed from the receiving slots 102.
所述第一外層導電線路層410包括多個第二電性接觸墊411。所述第二外層導電線路層420包括多個第三電性接觸墊421。The first outer conductive layer 410 includes a plurality of second electrical contact pads 411. The second outer conductive layer 420 includes a plurality of third electrical contact pads 421.
所述承載電路板100還包括第一防焊層430和第二防焊層440。所述第一防焊層430內具有與多個第二電性接觸墊411一一對應的多個第一開口431,每個第二電性接觸墊411從對應的第一開口431露出。所述第二防焊層440內具有與多個第三電性接觸墊421一一對應的多個第二開口441,每個第三電性接觸墊421從對應的第二開口441露出。The carrier circuit board 100 further includes a first solder resist layer 430 and a second solder resist layer 440. The first solder resist layer 430 has a plurality of first openings 431 corresponding to the plurality of second electrical contact pads 411 , and each of the second electrical contact pads 411 is exposed from the corresponding first opening 431 . The second solder resist layer 440 has a plurality of second openings 441 corresponding to the plurality of third electrical contact pads 421 , and each of the third electrical contact pads 421 is exposed from the corresponding second opening 441 .
所述承載電路板100還包括第一保護層123、第二保護層450和第三保護層460。第一保護層123形成在第一導電線路層12的每個第一電性接觸墊121的表面。第二保護層450形成在每個第二電性接觸墊411從第一開口431露出的表面。第三保護層460形成在每個第三電性接觸墊421從第二開口441露出的表面。The carrier circuit board 100 further includes a first protective layer 123, a second protective layer 450, and a third protective layer 460. The first protective layer 123 is formed on the surface of each of the first electrical contact pads 121 of the first conductive wiring layer 12. The second protective layer 450 is formed on a surface of each of the second electrical contact pads 411 exposed from the first opening 431. The third protective layer 460 is formed on a surface of each of the third electrical contact pads 421 exposed from the second opening 441.
請參閱圖20,本技術方案還提供一種包括上述承載電路板100的封裝結構200。Referring to FIG. 20 , the technical solution further provides a package structure 200 including the above-mentioned carrier circuit board 100 .
所述封裝結構200包括承載電路板100、第一晶片50、連接基板60及第二晶片70。The package structure 200 includes a carrier circuit board 100, a first wafer 50, a connection substrate 60, and a second wafer 70.
所述第一晶片50封裝於所述承載電路板100。第一晶片50的橫截面積與收容槽102的橫截面積大致相等。所述第一晶片50具有與多個第一電性接觸墊121一一對應的多個第四電性接觸墊51。每個第一電性接觸墊121與對應的第四電性接觸墊51通過第一焊球81相互連通。所述第一焊球81的材質可以為錫、鉛或銅,或者為錫、鉛或銅的合金。由於承載電路板100內具有收容槽102,從而可以使得所述第一焊球81收容於所述收容槽102內,或者將部分或全部的第一晶片50也收容於所述收容槽102內。The first wafer 50 is packaged on the carrier circuit board 100. The cross-sectional area of the first wafer 50 is substantially equal to the cross-sectional area of the receiving groove 102. The first wafer 50 has a plurality of fourth electrical contact pads 51 that are in one-to-one correspondence with the plurality of first electrical contact pads 121. Each of the first electrical contact pads 121 and the corresponding fourth electrical contact pads 51 are in communication with each other through the first solder balls 81. The material of the first solder ball 81 may be tin, lead or copper, or an alloy of tin, lead or copper. The receiving circuit board 100 has a receiving groove 102 therein, so that the first solder ball 81 can be received in the receiving groove 102 or some or all of the first wafer 50 can be accommodated in the receiving groove 102.
連接基板60包括絕緣基底61、分別設置於該絕緣基底61相對兩側的第一導電圖形62和第二導電圖形63以及分別形成於第一導電圖形62和第二導電圖形63的第三防焊層64和第四防焊層65。所述絕緣基底61內形成有導電孔,所述第一導電圖形62和第二導電圖形63通過所述導電孔相互電連通。所述第一導電圖形62包括與多個第二電性接觸墊411一一對應的多個第五電性接觸墊621。所述第二導電圖形63包括多個第六電性接觸墊631。The connection substrate 60 includes an insulating substrate 61, a first conductive pattern 62 and a second conductive pattern 63 respectively disposed on opposite sides of the insulating substrate 61, and a third solder resist formed on the first conductive pattern 62 and the second conductive pattern 63, respectively. Layer 64 and fourth solder mask 65. A conductive hole is formed in the insulating substrate 61, and the first conductive pattern 62 and the second conductive pattern 63 are electrically connected to each other through the conductive hole. The first conductive pattern 62 includes a plurality of fifth electrical contact pads 621 that are in one-to-one correspondence with the plurality of second electrical contact pads 411 . The second conductive pattern 63 includes a plurality of sixth electrical contact pads 631.
第三防焊層64具有多個第三開口,每個第五電性接觸墊621從對應的第三開口露出。第四防焊層65內形成有多個第四開口,每個第六電性接觸墊631從對應的第四開口露出。The third solder resist layer 64 has a plurality of third openings, and each of the fifth electrical contact pads 621 is exposed from the corresponding third opening. A plurality of fourth openings are formed in the fourth solder resist layer 65, and each of the sixth electrical contact pads 631 is exposed from the corresponding fourth opening.
連接基板60封裝於承載電路板100。具體地,每個第五電性接觸墊621與對應的第二電性接觸墊411通過第二焊球82相互電連接。The connection substrate 60 is packaged on the carrier circuit board 100. Specifically, each of the fifth electrical contact pads 621 and the corresponding second electrical contact pads 411 are electrically connected to each other through the second solder balls 82.
第二晶片70封裝於連接基板60。本實施例中,第二晶片70為導線鍵合(wire bonding, WB)晶片,並將第二晶片70與第六電性接觸墊631電性連接。具體的,第二晶片70具有多個鍵合接點以及自多個鍵合接點延伸的多個條鍵合導線71,鍵合導線71與第六電性接觸墊631一一對應。多個條鍵合導線71的一端電性連接該第二晶片70,另一端分別電性連接該多個第六電性接觸墊631,從而使第二晶片70與第二導電圖形63電連接。The second wafer 70 is packaged on the connection substrate 60. In this embodiment, the second wafer 70 is a wire bonding (WB) wafer, and the second wafer 70 is electrically connected to the sixth electrical contact pad 631. Specifically, the second wafer 70 has a plurality of bonding contacts and a plurality of strip bonding wires 71 extending from the plurality of bonding contacts, and the bonding wires 71 are in one-to-one correspondence with the sixth electrical contact pads 631. One end of the plurality of strip bonding wires 71 is electrically connected to the second wafer 70, and the other end is electrically connected to the plurality of sixth electrical contact pads 631, respectively, so that the second wafer 70 is electrically connected to the second conductive pattern 63.
本實施例中,採用封裝膠體72將鍵合導線71、第二晶片70及連接基板60外露的第三防焊層64和第六電性接觸墊631表面進行包覆封裝。本實施例中,該封裝膠體72為黑膠,當然,該封裝膠體72也可以其他封裝膠體材料,並不以本實施例為限。In this embodiment, the surface of the third solder resist 64 and the sixth electrical contact pad 631 exposed by the bonding wires 71, the second wafer 70 and the connecting substrate 60 are encapsulated by the encapsulant 72. In this embodiment, the encapsulant 72 is a black plastic. Of course, the encapsulant 72 can also be encapsulated with other colloidal materials, and is not limited to this embodiment.
本技術方案提供的電路板及其製作方法,先提供一個具有第一導電線路圖形的芯層電路基板及一個形成有開孔的絕緣基板,然後採用介電膠片將芯層電路基板及絕緣基板相互連接,而後再製作形成外層導電線路層。由於芯層電路基板內的導電線路與外層的導電線路分開製作,可以使得芯層電路基板的導電線路採用細線路,而外層的導電線路可以採用相對較粗的線路,不僅實現了細線路電路板的功能,而且避免了在無需形成細線路區域仍需要技術複雜且制程昂貴的細線路製作技術來形成導電線路的可能,減少了電路板的製作工藝,降低了電路板的製成成本。The circuit board and the manufacturing method thereof provided by the technical solution first provide a core circuit substrate having a first conductive line pattern and an insulating substrate formed with an opening, and then the core circuit substrate and the insulating substrate are mutually exchanged by using a dielectric film The connection is then made to form an outer conductive layer. Since the conductive lines in the core circuit substrate are separately formed from the conductive lines of the outer layer, the conductive lines of the core circuit substrate can be made thin, and the conductive lines of the outer layer can be relatively thick, not only the thin circuit board is realized. The function, and avoiding the need of forming a thin circuit area, still requires a complicated circuit manufacturing process and forming a conductive circuit, thereby reducing the manufacturing process of the circuit board and reducing the manufacturing cost of the circuit board.
另外,在製作過程中,採用的絕緣基板的厚度大於芯層電路基板的厚度,當芯層電路基板收容於絕緣基板的開孔後,形成一個收容槽。所述的電路承載板在進行封裝時,可以使得封裝於其上的晶片部分或者全部收容於所述收容槽內,從而可以減小封裝後的封裝結構的尺寸。In addition, in the manufacturing process, the thickness of the insulating substrate used is larger than the thickness of the core circuit substrate, and when the core circuit substrate is received in the opening of the insulating substrate, a receiving groove is formed. When the circuit board is packaged, part or all of the wafers packaged thereon can be received in the receiving groove, so that the size of the package structure after packaging can be reduced.
更進一步地,現有技術中採用塑膠作為芯層電路基板的基底由於芯層電路基板,而晶片通常採用矽製成。由於塑膠的熱膨脹係數與矽的熱膨脹係數相差較大,在將晶片封裝時,易於造成由於漲縮不一致而導致的品質問題。本技術方案中,芯層電路基板採用玻璃基底,玻璃的熱膨脹係數與矽相差較小,從而可以提高形成的封裝結構的品質。Further, the prior art uses plastic as the substrate of the core layer circuit substrate due to the core circuit substrate, and the wafer is usually made of tantalum. Since the thermal expansion coefficient of the plastic differs greatly from the thermal expansion coefficient of the crucible, when the wafer is packaged, it is easy to cause quality problems due to inconsistent expansion and contraction. In the technical solution, the core circuit substrate is made of a glass substrate, and the thermal expansion coefficient of the glass is less than that of the germanium, so that the quality of the formed package structure can be improved.
惟,以上所述者僅為本發明之較佳實施方式,自不能以此限制本案之申請專利範圍。舉凡熟悉本案技藝之人士爰依本發明之精神所作之等效修飾或變化,皆應涵蓋於以下申請專利範圍內。However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.
100...承載電路板100. . . Bearer board
10...芯層電路基板10. . . Core circuit substrate
11...玻璃基板11. . . glass substrate
12...第一導電線路層12. . . First conductive circuit layer
13...可剝離保護層13. . . Peelable protective layer
14...第一絕緣層14. . . First insulating layer
15...第一電性接觸墊15. . . First electrical contact pad
111...第一通孔111. . . First through hole
112...金屬導電柱112. . . Metal conductive column
113...第一表面113. . . First surface
114...第二表面114. . . Second surface
115...阻擋圖形115. . . Blocking graphics
1111...第一盲孔1111. . . First blind hole
141...導電孔141. . . Conductive hole
121...第一電性接觸墊121. . . First electrical contact pad
20...支撐板20. . . Support plate
20a...本體20a. . . Ontology
31...第一絕緣基板31. . . First insulating substrate
33...第一開孔33. . . First opening
32...第二絕緣基板32. . . Second insulating substrate
34...第二開孔34. . . Second opening
201...離型膜201. . . Release film
41...第一介電膠片41. . . First dielectric film
42...第二介電膠片42. . . Second dielectric film
103...電路基板103. . . Circuit substrate
311...第二通孔311. . . Second through hole
312...第二盲孔312. . . Second blind hole
313...導電通孔313. . . Conductive through hole
314...導電盲孔314. . . Conductive blind hole
410...第一外層導電線路層410. . . First outer conductive layer
420...第二外層導電線路層420. . . Second outer conductive layer
411...第二電性接觸墊411. . . Second electrical contact pad
421...第三電性接觸墊421. . . Third electrical contact pad
101...堆疊結構101. . . Stack structure
102...收容槽102. . . Storage slot
430...第一防焊層430. . . First solder mask
431...第一開口431. . . First opening
440...第二防焊層440. . . Second solder mask
441...第二開口441. . . Second opening
123...第一保護層123. . . First protective layer
450...第二保護層450. . . Second protective layer
460...第三保護層460. . . Third protective layer
200...封裝結構200. . . Package structure
50...第一晶片50. . . First wafer
51...第四電性接觸墊51. . . Fourth electrical contact pad
60...連接基板60. . . Connection substrate
61...絕緣基底61. . . Insulating substrate
62...第一導電圖形62. . . First conductive pattern
63...第二導電圖形63. . . Second conductive pattern
621...第五電性接觸墊621. . . Fifth electrical contact pad
631...第六電性接觸墊631. . . Sixth electrical contact pad
64...第三防焊層64. . . Third solder mask
65...第四防焊層65. . . Fourth solder mask
70...第二晶片70. . . Second chip
71...鍵合導線71. . . Bond wire
72...封裝膠體72. . . Encapsulant
81...第一焊球81. . . First solder ball
82...第二焊球82. . . Second solder ball
圖1為本技術方案提供的芯層電路基板的剖面示意圖。1 is a schematic cross-sectional view of a core circuit substrate provided by the present technical solution.
圖2至8為本技術方案提供的芯層電路基板製作過程的示意圖。2 to 8 are schematic diagrams showing a manufacturing process of a core layer circuit substrate provided by the technical solution.
圖9及圖10為本技術方案提供的絕緣基板的剖面示意圖。9 and 10 are schematic cross-sectional views of an insulating substrate provided by the present technical solution.
圖11為本技術方案提供的支撐板的剖面示意圖。Figure 11 is a schematic cross-sectional view of a support plate provided by the present technical solution.
圖12為本技術方案提供的介電膠片的剖面示意圖。12 is a schematic cross-sectional view of a dielectric film provided by the present technical solution.
圖13為堆疊所述芯層電路基板、絕緣基板、支撐板及介電膠片形成堆疊結構後的剖面示意圖。FIG. 13 is a cross-sectional view showing the stacking of the core circuit substrate, the insulating substrate, the support plate, and the dielectric film in a stacked structure.
圖14為壓合所述堆疊結構得到兩個電路基板後的剖面示意圖。FIG. 14 is a schematic cross-sectional view showing the two circuit boards obtained by pressing the stacked structure.
圖15為將兩個電路基板與支撐板分離後的剖面示意圖。Fig. 15 is a schematic cross-sectional view showing the separation of two circuit boards from a support plate.
圖16為在電路基板中型通孔及盲孔後的剖面示意圖。Fig. 16 is a schematic cross-sectional view showing a through hole and a blind hole in a circuit board.
圖17為在電路基板的相對兩表面形成第一外層導電線路層和第二外層導電線路層後的剖面示意圖。17 is a schematic cross-sectional view showing the first outer conductive layer and the second outer conductive layer formed on opposite surfaces of the circuit substrate.
圖18為圖17的電路基板去除可剝離保護層後的剖面示意圖。18 is a schematic cross-sectional view showing the circuit board of FIG. 17 with the peelable protective layer removed.
圖19為本技術方案提供的承載電路板的剖面示意圖。FIG. 19 is a cross-sectional view of a carrier circuit board provided by the technical solution.
圖20為本技術方案提供的封裝結構的剖面示意圖。20 is a schematic cross-sectional view of a package structure provided by the present technical solution.
10...芯層電路基板10. . . Core circuit substrate
31...第一絕緣基板31. . . First insulating substrate
41...第一介電膠片41. . . First dielectric film
411...第二電性接觸墊411. . . Second electrical contact pad
421...第三電性接觸墊421. . . Third electrical contact pad
430...第一防焊層430. . . First solder mask
431...第一開口431. . . First opening
440...第二防焊層440. . . Second solder mask
441...第二開口441. . . Second opening
123...第一保護層123. . . First protective layer
450...第二保護層450. . . Second protective layer
460...第三保護層460. . . Third protective layer
100...承載電路板100. . . Bearer board
Claims (16)
提供芯層電路基板,所述芯層電路基板包括玻璃基底、多個第一電性接觸墊及可剝離保護層,所述玻璃基板內設置有多個金屬導電柱,所述第一電性接觸墊與對應的金屬導電柱相互電連接,所述可剝離保護層形成於第一電性接觸墊表面;
提供支撐板、絕緣基板及介電膠片,所述絕緣基板內形成有與芯層電路基板形狀對應的開孔,所述開孔的橫截面積大於芯層電路基板的橫截面積;
將芯層電路基板及絕緣基板設置於支撐板的一側,使得所述可剝離保護層與支撐板相接觸,所述芯層電路基板收容於所述開孔內,所述介電膠片位於芯層電路基板及絕緣基板遠離支撐板的一側,形成堆疊結構;
壓合所述堆疊結構,使得部分介電膠片填充至開孔內以連接芯層電路基板及絕緣基板,所述介電膠片、芯層電路基板及絕緣基板共同構成電路基板;
分離所述支撐板與電路基板;
在所述絕緣基板遠離所述介電膠片的表面形成多個第二電性接觸墊,在所述介電膠片遠離所述絕緣基板的表面形成第二外層導電線路層;以及
去除所述可剝離保護層,形成一收容槽,所述第一電性接觸墊從所述收容槽底部露出,得到承載電路板。A method for manufacturing a carrier circuit board, comprising the steps of:
Providing a core circuit substrate, the core circuit substrate includes a glass substrate, a plurality of first electrical contact pads, and a peelable protective layer, wherein the glass substrate is provided with a plurality of metal conductive pillars, and the first electrical contact The pad is electrically connected to the corresponding metal conductive pillar, and the peelable protective layer is formed on the surface of the first electrical contact pad;
Providing a support plate, an insulating substrate, and a dielectric film, wherein the insulating substrate is formed with an opening corresponding to a shape of the core circuit substrate, wherein the opening has a cross-sectional area larger than a cross-sectional area of the core circuit substrate;
The core circuit substrate and the insulating substrate are disposed on one side of the support plate such that the peelable protective layer is in contact with the support plate, the core circuit substrate is received in the opening, and the dielectric film is located in the core a layer circuit substrate and an insulating substrate away from a side of the support plate to form a stacked structure;
Pressing the stacked structure such that a portion of the dielectric film is filled into the opening to connect the core circuit substrate and the insulating substrate, and the dielectric film, the core circuit substrate and the insulating substrate together constitute a circuit substrate;
Separating the support plate from the circuit substrate;
Forming a plurality of second electrical contact pads on a surface of the insulating substrate away from the dielectric film, forming a second outer conductive layer on a surface of the dielectric film away from the insulating substrate; and removing the peelable The protective layer forms a receiving slot, and the first electrical contact pad is exposed from the bottom of the receiving slot to obtain a carrying circuit board.
提供玻璃基板,所述玻璃基板具有相對的第一表面和第二表面,並從第一表面一側在玻璃基板內形成多個第一盲孔;
在所述多個第一盲孔內形成金屬導電柱;
在玻璃基板的第一表面形成第一導電線路層,所述金屬導電柱與所述第一導電線路層相互電連接;
在第一導電線路層表面形成第一絕緣層,所述第一絕緣層內,形成有多個開口;
對玻璃基板進行薄化處理,使得每個金屬導電柱的另一端從玻璃基板的第二表面一側露出;
在第一絕緣層遠離第一導電線路層一側形成多個第一電性接觸墊;以及
在多個第一電性接觸墊一側形成可剝離保護層。The method of fabricating a carrier circuit board according to claim 7, wherein the fabricating the core circuit substrate comprises the steps of:
Providing a glass substrate having opposite first and second surfaces, and forming a plurality of first blind holes in the glass substrate from the first surface side;
Forming a metal conductive pillar in the plurality of first blind holes;
Forming a first conductive circuit layer on the first surface of the glass substrate, the metal conductive pillar and the first conductive circuit layer being electrically connected to each other;
Forming a first insulating layer on a surface of the first conductive circuit layer, and forming a plurality of openings in the first insulating layer;
Thinning the glass substrate such that the other end of each of the metal conductive pillars is exposed from the second surface side of the glass substrate;
Forming a plurality of first electrical contact pads on a side of the first insulating layer away from the first conductive line layer; and forming a peelable protective layer on a side of the plurality of first electrical contact pads.
提供兩個芯層電路基板,每個所述芯層電路基板包括玻璃基底、多個第一電性接觸墊及可剝離保護層,所述玻璃基板內設置有多個金屬導電柱,所述第一電性接觸墊與對應的金屬導電柱相互電連接,所述可剝離保護層形成於第一電性接觸墊表面;
提供支撐板、兩個絕緣基板及兩個介電膠片,每個所述絕緣基板內形成有與芯層電路基板形狀對應的開孔,所述開孔的橫截面積大於芯層電路基板的橫截面積;
將一個芯層電路基板及一個絕緣基板設置於支撐板的一側,另一個芯層電路基板及另一個絕緣基板設置於支撐板的另一側,使得所述可剝離保護層與支撐板相接觸,所述芯層電路基板收容於所述開孔內,所述介電膠片位於芯層電路基板及絕緣基板遠離支撐板的一側,形成堆疊結構;
壓合所述堆疊結構,使得部分介電膠片填充至開孔內以連接芯層電路基板及絕緣基板,每個所述介電膠片、芯層電路基板及絕緣基板共同構成一個電路基板;
分離所述支撐板與兩個電路基板;
在每個電路基板的所述絕緣基板遠離所述介電膠片的表面形成多個第二電性接觸墊,在所述介電膠片遠離所述絕緣基板的表面形成多個二外層導電線路層;以及
去除每個所述可剝離保護層,形成一收容槽,所述第一電性接觸墊從所述收容槽底部露出,得到兩個承載電路板。A method for manufacturing a carrier circuit board, comprising the steps of:
Providing two core circuit substrates, each of the core circuit substrates includes a glass substrate, a plurality of first electrical contact pads, and a peelable protective layer, wherein the glass substrate is provided with a plurality of metal conductive pillars, An electrical contact pad is electrically connected to the corresponding metal conductive pillar, and the peelable protective layer is formed on the surface of the first electrical contact pad;
Providing a support plate, two insulating substrates and two dielectric films, each of the insulating substrates is formed with an opening corresponding to a shape of the core circuit substrate, and the cross-sectional area of the opening is larger than the horizontal of the core circuit substrate Cross-sectional area
One core circuit substrate and one insulating substrate are disposed on one side of the support plate, and the other core circuit substrate and another insulating substrate are disposed on the other side of the support plate such that the peelable protective layer is in contact with the support plate The core circuit substrate is received in the opening, and the dielectric film is located on a side of the core circuit substrate and the insulating substrate away from the support plate to form a stacked structure;
Pressing the stacked structure, a part of the dielectric film is filled into the opening to connect the core circuit substrate and the insulating substrate, and each of the dielectric film, the core circuit substrate and the insulating substrate together form a circuit substrate;
Separating the support plate and the two circuit substrates;
Forming a plurality of second electrical contact pads on the surface of the insulating substrate of the circuit substrate away from the dielectric film, and forming a plurality of two outer conductive layer on the surface of the dielectric film away from the insulating substrate; And removing each of the peelable protective layers to form a receiving slot, the first electrical contact pads being exposed from the bottom of the receiving slot to obtain two carrying circuit boards.
The package structure of claim 15, further comprising a connection substrate and a second wafer, wherein the second chip is packaged on the connection substrate, and the connection substrate passes through the second solder ball and the second outer conductive layer layer Electrical connection.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201210559728.9A CN103889168A (en) | 2012-12-21 | 2012-12-21 | Bearing circuit board, manufacturing method of bearing circuit board and packaging structure |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201427522A TW201427522A (en) | 2014-07-01 |
TWI465171B true TWI465171B (en) | 2014-12-11 |
Family
ID=50957826
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW101150353A TWI465171B (en) | 2012-12-21 | 2012-12-27 | Package circuit board, method for manufacturing asme, and package structure |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN103889168A (en) |
TW (1) | TWI465171B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI711133B (en) * | 2019-07-26 | 2020-11-21 | 大陸商上海兆芯集成電路有限公司 | Electronic structure and manufacturing method thereof |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106304611A (en) * | 2015-06-10 | 2017-01-04 | 宏启胜精密电子(秦皇岛)有限公司 | Circuit board and manufacture method thereof, apply the electronic installation of this circuit board |
TWI632647B (en) * | 2016-01-18 | 2018-08-11 | 矽品精密工業股份有限公司 | Packaging process and package substrate for use in the process |
TWI556704B (en) * | 2016-03-03 | 2016-11-01 | Non - welded multilayer circuit board and its manufacturing method | |
TWI613943B (en) * | 2016-07-12 | 2018-02-01 | Method for manufacturing wafer fixed structure | |
TWI577248B (en) * | 2016-07-19 | 2017-04-01 | 欣興電子股份有限公司 | Circuit carrier and manufacturing mtheod thereof |
JP6446155B1 (en) | 2018-07-17 | 2018-12-26 | 株式会社日立パワーソリューションズ | Double-sided circuit non-oxide ceramic substrate and manufacturing method thereof |
CN110859022A (en) * | 2018-08-24 | 2020-03-03 | 三赢科技(深圳)有限公司 | Circuit board and electronic device using same |
TWI691239B (en) * | 2018-08-24 | 2020-04-11 | 鴻海精密工業股份有限公司 | Circuit board and electronic device using the same |
CN113036561A (en) * | 2019-12-24 | 2021-06-25 | 广州方邦电子股份有限公司 | Preparation method of connector, connector and integrated device |
CN115424542B (en) * | 2022-11-03 | 2023-02-28 | 长春希达电子技术有限公司 | Seamless spliced Micro-LED display panel and preparation method thereof |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI266403B (en) * | 2003-12-31 | 2006-11-11 | Phoenix Prec Technology Corp | Method for fabricating semiconductor package substrate with opening penetrating therethrough |
TWI378519B (en) * | 2007-08-24 | 2012-12-01 | Teramikros Inc |
-
2012
- 2012-12-21 CN CN201210559728.9A patent/CN103889168A/en active Pending
- 2012-12-27 TW TW101150353A patent/TWI465171B/en active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI266403B (en) * | 2003-12-31 | 2006-11-11 | Phoenix Prec Technology Corp | Method for fabricating semiconductor package substrate with opening penetrating therethrough |
TWI378519B (en) * | 2007-08-24 | 2012-12-01 | Teramikros Inc |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI711133B (en) * | 2019-07-26 | 2020-11-21 | 大陸商上海兆芯集成電路有限公司 | Electronic structure and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
TW201427522A (en) | 2014-07-01 |
CN103889168A (en) | 2014-06-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI465171B (en) | Package circuit board, method for manufacturing asme, and package structure | |
KR101058621B1 (en) | Semiconductor package and manufacturing method thereof | |
TWI504329B (en) | Package substrate, package structure and method for manufacturing package structure | |
JP4171499B2 (en) | Electronic device substrate and manufacturing method thereof, and electronic device and manufacturing method thereof | |
TWI670814B (en) | Single layer coreless substrate | |
CN107393899B (en) | Chip packaging substrate | |
JPWO2007126090A1 (en) | CIRCUIT BOARD, ELECTRONIC DEVICE DEVICE, AND CIRCUIT BOARD MANUFACTURING METHOD | |
KR102194722B1 (en) | Package board, method for manufacturing the same and package on package having the thereof | |
JP4990826B2 (en) | Multilayer printed circuit board manufacturing method | |
US20210193562A1 (en) | Component Carrier With Embedded Interposer Laterally Between Electrically Conductive Structures of Stack | |
KR20170009128A (en) | Circuit board and manufacturing method of the same | |
TWI772480B (en) | Method of manufacturing semiconductor package substrate and semiconductor package substrate manufactured using the same | |
JP2010171387A (en) | Circuit board structure and production method therefor | |
JP2015225895A (en) | Printed wiring board, semiconductor package and printed wiring board manufacturing method | |
TWI466611B (en) | Printed circuit board having buried component, method for manufacturing same and chip package structure | |
TWI498056B (en) | Printed circuit board with burried element and method for manufacture same and package structure | |
KR20150135046A (en) | Package board, method for manufacturing the same and package on packaage having the thereof | |
TWI585919B (en) | Chip package substrate ,chip packaging structure and manufacturing method of same | |
TWI511628B (en) | Package circuit board, method for manufactuing same and package structure | |
TWI511634B (en) | Method for manufacturing circuit board | |
TW201701419A (en) | Package structure and the manufacture thereof | |
US11923282B2 (en) | Wiring substrate | |
US20210391213A1 (en) | Interposer board without feature layer structure and method for manufacturing the same | |
JP2019067864A (en) | Method for manufacturing printed wiring board | |
KR101015762B1 (en) | Method of manufacturing semiconductor package |