TWI498056B - Printed circuit board with burried element and method for manufacture same and package structure - Google Patents

Description

Circuit board with embedded components, manufacturing method thereof and package structure

The present invention relates to the field of circuit board manufacturing with buried components, and more particularly to a circuit board having buried components having buried electronic components, a method of fabricating a circuit board having embedded components, and a package structure.

Printed circuit boards have been widely used due to their high assembly density. For application of the circuit board, please refer to the literature Takahashi, A.Ooki, N.Nagai, A.Akahoshi, H.Mukoh, A.Wajima,M.Res.Lab,High density multilayer printed circuit board for HITAC M-880,IEEE Trans .on Components, Packaging, and Manufacturing Technology, 1992, 15(4): 418-425. The pads of the outer conductive traces of a common circuit board are exposed on the same side of the board, and the pads exposed on the same side are on the same plane. When the electronic component is mounted on the exposed pad, the pad is located under the electronic component, thereby increasing the height of the circuit board having the electronic component, and enlarging the circuit board with the embedded component encapsulating the chip. The volume of the package structure.

In view of the above, it is necessary to provide a circuit board having a buried component, a manufacturing method of the circuit board having the embedded component, and a package structure having the circuit board having the embedded component, so that the electronic component is buried with the embedded component In the board, thus reducing The thickness of the circuit board of the embedded component reduces the volume of the circuit board having the embedded component with the electronic component, thereby reducing the volume of the circuit board having the embedded component in which the wafer is packaged.

A method of fabricating a circuit board having a buried component, comprising the steps of: providing a circuit substrate, the circuit substrate comprising an electronic component, an insulating substrate and a first dielectric film, the insulating substrate having an opposite first surface And the second surface, the insulating substrate further has a first through hole penetrating the first surface and the second surface, the first through hole having a cross-sectional area larger than a cross-sectional area of the electronic component, The electronic component is received in the first through hole, the first dielectric film covers the second surface of the insulating substrate and the electronic component, and fills a gap between the electronic component and the insulating substrate; Forming a first conductive line pattern on the first surface of the insulating substrate, forming a second conductive line pattern on the surface of the first dielectric film adjacent to the second surface, and electrically connecting the first conductive line a circuit pattern and a second conductive line pattern electrically connecting the second conductive line pattern and the electronic component; pressing a second dielectric film on a side of the first conductive line pattern The second dielectric film covers the first conductive line pattern, the first surface of the insulating substrate exposed from the first conductive line pattern, and the electronic component; and the surface of the second dielectric film away from the first surface a first outer conductive layer, electrically connecting the first outer conductive layer and the electronic component, electrically connecting the first outer conductive layer and the first conductive trace to obtain the circuit board having the embedded component .

A circuit board having a buried component, comprising an insulating substrate, an electronic component, a first dielectric film, a first conductive trace pattern, a second conductive trace pattern, a second dielectric film, and a first outer conductive layer. The insulating substrate has opposing first and second surfaces. The insulating substrate is further provided with a first surface and a second surface The first through hole of the face. The first through hole has a cross sectional area larger than a cross sectional area of the electronic component. The electronic component is received in the first through hole. The first dielectric film covers the second surface of the insulating substrate and the electronic component, and fills a gap between the insulating substrate and the electronic component. The first conductive line pattern is formed on the first surface of the insulating substrate. The first dielectric film covers the second surface of the insulating substrate and the electronic component, and fills a gap between the electronic component and the insulating substrate. The second conductive line pattern is formed on a surface of the first dielectric film adjacent to the second surface, electrically connected to the first conductive line pattern, and disposed in the first dielectric film The conductive blind hole is electrically connected to the electronic component. The second dielectric film covers the first conductive line pattern, the first surface of the insulating substrate exposed from the first conductive line pattern, and the electronic component. The first outer conductive layer is formed on a surface of the second dielectric film adjacent to the first surface, and through the conductive blind hole provided in the second dielectric film and the electronic component A conductive line pattern is electrically connected.

A package structure comprising a wafer and the above-mentioned circuit board having a buried component, the first outer conductive layer of the circuit board having the embedded component comprising a plurality of electrical contact pads, the wafer being soldered The electrical contact pads of the circuit board with embedded components are connected to each other.

Compared with the prior art, the circuit board with embedded components and the manufacturing method thereof are provided in the technical solution, and the electronic components are buried in the insulating substrate, thereby reducing the thickness of the circuit board having the embedded components and reducing the thickness of the circuit board having the embedded components. The volume of the board with embedded components, which in turn reduces the volume of the board with the embedded components encapsulating the wafer.

10‧‧‧Electronic components

11‧‧‧Insert substrate

12‧‧‧Support board

101‧‧‧ Subject

103‧‧‧First electrical connection

105‧‧‧Second electrical connection

11a‧‧‧ first surface

11b‧‧‧ second surface

111‧‧‧First through hole

121‧‧‧ release film

21‧‧‧First dielectric film

100a‧‧‧ circuit board

211‧‧‧Second through hole

213‧‧‧ first blind hole

110‧‧‧First conductive line pattern

120‧‧‧Second conductive line pattern

214‧‧‧ conductive vias

215‧‧‧First conductive blind hole

110a, 120a‧‧‧ conductive lines

22‧‧‧Second dielectric film

23‧‧‧ Third dielectric film

216a, 216b‧‧‧ second blind hole

217‧‧‧ third blind hole

130‧‧‧First outer conductive layer

140‧‧‧Second outer conductive layer

218a, 218b‧‧‧Second conductive blind hole

219‧‧‧3rd conductive blind hole

131‧‧‧First electrical contact pads

141‧‧‧Second electrical contact pads

150‧‧‧First solder mask

160‧‧‧Second solder mask

151‧‧‧ first opening

161‧‧‧ second opening

170‧‧‧First protective layer

100‧‧‧Board with embedded components

200‧‧‧Package structure

300‧‧‧ wafer

301‧‧‧ Third electrical contact pad

303‧‧‧ solder balls

1 is a cross-sectional view showing an electronic component, an insulating substrate, and a support plate provided by the technical solution. It is intended that the insulating substrate and the electronic component are placed on the support plate, and the electronic component is housed in the insulating substrate.

2 is a schematic cross-sectional view showing a first dielectric film bonded to a side of the insulating substrate shown in FIG. 1 away from the support plate.

3 is a schematic cross-sectional view of a circuit substrate obtained by removing the support plate of FIG. 2.

4 is a cross-sectional view showing a through hole formed in the circuit substrate shown in FIG. 3 and a first blind hole formed in the first dielectric film.

5 is a first conductive line pattern formed on the insulating substrate shown in FIG. 4, a second conductive line pattern is formed on the surface of the first dielectric film, and the through hole is made into a conductive via, the first blind hole A schematic cross-sectional view of the first conductive blind via.

FIG. 6 is a cross-sectional view showing a second dielectric film pressed on one side of the first conductive line pattern and a third dielectric film on the side of the second conductive line pattern.

FIG. 7 is a cross-sectional view showing the formation of a second blind via in the second dielectric film shown in FIG. 6 after forming at least one third blind via in the third dielectric film.

8 is a first outer conductive layer formed on the surface of the second dielectric film shown in FIG. 7, a second outer conductive layer on the third dielectric film surface, and the second blind hole and the third A schematic cross-sectional view of the blind vias after the second conductive blind vias and the third conductive blind vias are respectively formed.

FIG. 9 is a schematic cross-sectional view showing the first solder resist layer formed on the surface of the first outer layer conductive layer shown in FIG. 8 and the second solder resist layer formed on the surface of the second outer layer conductive layer.

Figure 10 is a first electrical contact pad of the first outer conductive layer of the layer shown in Figure 9 The surface forms a first protective layer, and a schematic cross-sectional view of the obtained circuit board with buried components after forming a second protective layer on the surface of each of the second electrical contact pads.

FIG. 11 is a schematic view showing a package structure obtained after a wafer is mounted on a circuit board having a buried component shown in FIG.

The circuit board manufacturing method provided by the technical solution includes the following steps:

In the first step, referring to FIG. 1, an electronic component 10, an insulating substrate 11, and a support plate 12 are provided.

The electronic component 10 can be a resistor, a capacitor, a wafer, etc., and includes a main body 101, a first electrical connection end 103, and a second electrical connection end 105. Each of the first electrical connection end 103 and the second electrical connection end 105 is electrically connected to the main body 101. In this embodiment, the electronic component 10 is a multilayer ceramic capacitor known in the art; the main body 101 is a ceramic body in which a plurality of internal electrodes are formed; the first electrical connection end 103 and the second electrical connection The ends 105 are all external electrodes and are located on opposite sides of the body 101, respectively.

The insulating substrate 11 has opposing first and second surfaces 11a, 11b. The insulating substrate 11 is further provided with a first through hole 111 penetrating the first surface 11a and the second surface 11b. The cross-sectional area of the first through hole 111 is larger than the cross-sectional area of the electronic component 10.

Next, the insulating substrate 11 and the electronic component 10 are disposed on the support plate 12 such that the first surface 11a is in contact with the support plate 12, and the electronic component 10 is received in the first through hole. 111 in. That is, the insulating substrate 11 and electronic components 10 is disposed on an upper side of the support plate 12. Preferably, in the embodiment, the surface of the electronic component 10 away from the support board 12 is flush with the second surface 11b of the insulating substrate 11, that is, the thickness of the electronic component 10 is equal to the insulating substrate. The thickness of 11. It will be understood by those skilled in the art that the surface of the electronic component 10 away from the support plate 12 can also protrude from the second surface 11b of the insulating substrate 11, that is, the electronic component 10 is far away. The surface of the support plate 12 is away from the support plate 12 than the second surface 11b of the insulating substrate 11, that is, the thickness of the electronic component 10 is greater than the thickness of the insulating substrate 11; The two surfaces 11b may also protrude from the surface of the electronic component 10 away from the support plate 12, that is, the surface of the electronic component 10 away from the support plate 12 is closer to the second surface 11b of the insulating substrate 11. The support plate 12, that is, the thickness of the electronic component 10 is smaller than the thickness of the insulating substrate 11.

Preferably, in the embodiment, in order to better separate the insulating substrate 11 and the electronic component 10 from the support plate 12 in a subsequent step, the support plate 12 is further disposed on a surface of the insulating substrate 11 A release film 121. That is, the release film 121 is located between the support plate 12 and the insulating substrate 11. The release film 121 may be a polymer film such as a polypropylene film, a polyethylene film, or a polyethylene terephthalate, and is preferably a polyethylene terephthalate film. In this embodiment, a poly film is used. A polyethylene terephthalate film is used as the release film 121. The release film 121 can also be a release paper commonly used in other industries.

In the second step, referring to FIG. 2, the first dielectric film 21 is pressed on the second surface 11b side of the insulating substrate 11 so that the first dielectric film 21 covers the second of the insulating substrate 11. The surface 11b and the electronic component 10 are away from the surface of the support plate 12, and fill a gap between the electronic component 10 and the insulating substrate 11, thereby insulating the substrate. The board 11 and the first dielectric film 21 and the electronic component 10 located in the first through hole 111 are integrally bonded together to form a circuit substrate 100a.

In this step, the first dielectric film 21 is press-fitted to the side of the insulating substrate 11 away from the support plate 12 by thermocompression bonding. The material of the first dielectric film 21 may be Polyimide (PI), Polyethylene Terephthalate (PET) or Polyethylene naphthalate (PEN). PP, Prepreg or ABF (Ajinomoto Build-up film), etc., preferably PP or ABF.

In the third step, referring to FIG. 3 together, the support plate 12 is separated from the circuit substrate 100a to obtain the circuit substrate 100a.

It is understood by those skilled in the art that two insulating substrates 11 and two electronic components 10 can be provided in the first step. In this case, an insulating substrate 11 and an electronic component 10 are disposed in the The upper side of the support plate 12 (as shown in FIG. 1 ), the other insulating substrate 11 and the other electronic component 10 are disposed on the lower side of the support plate 12 , and the other electronic component 10 is received in the other insulating substrate 11 . In a through hole 111, that is, the support plate 12 is interposed between the two insulating substrates 11. In this case, in the second step, while the first dielectric film 21 is pressed on the second surface 11b side of the insulating substrate 11, the other side of the support plate 12 may be pressed against the other side. The first dielectric film 21 covers the gap between the other insulating substrate 11, the other electronic component 10, and the electronic component between the insulating substrates 11. As such, two phase-separated circuit substrates 100a can be obtained after the support plate 12 is removed.

Referring to FIG. 4, at least one of the insulating substrate 11 and the first dielectric film 21 of the circuit substrate 100a corresponding to the insulating substrate 11 is formed. The second through hole 211 forms a first blind hole 213 in a region of the first dielectric film 21 corresponding to the first electrical connection end 103 of the electronic component 10.

In this step, the second through hole 211 and the first blind hole 213 may be formed by laser ablation. The second through hole 211 penetrates a region of the insulating substrate 11 and the first dielectric film 21 corresponding to the insulating substrate 11 . The second through hole 211 can also be formed by mechanical drilling. The number of the second through holes 211 may be one or plural. In FIG. 4, two second through holes 211 are formed as an example for description. The first blind via 213 extends only through the region of the first dielectric film 21 corresponding to the first electrical connection end 103 of the electronic component 10 to expose a portion of the first electrical connection end 103. It can be understood that, after this step, a step of desmear may be further included to remove the slag inside the second through hole 211 and the first blind hole 213, thereby effectively preventing subsequent processing. When electroplating, the slag affects the conductivity of the formed conductive holes.

In the fifth step, referring to FIG. 5, a first conductive line pattern 110 is formed on the first surface 11a of the insulating substrate 11, and a second conductive line is formed on the surface of the first dielectric film 21 near the second surface 11b. The pattern 120 is formed into a conductive via 214, and the first via 213 is formed as a first conductive via 215. The first conductive line pattern 110 includes a plurality of conductive lines 110a. The second conductive line pattern 120 includes a plurality of conductive lines 120a. The conductive via 214 electrically conducts the first conductive trace pattern 110 and the second conductive trace pattern 120. The first conductive via 215 electrically conducts the second conductive trace pattern 120 and the first electrical connection end 103 of the electronic component 10 .

This step can specifically adopt the following methods:

First, the first surface 11a and the first dielectric film 21 are formed by electroless copper plating. Forming a first conductive seed layer on the surface of the first surface 11a and the surface of the electronic component 10 adjacent to the first surface 11a, the inner wall of the second through hole 211, the inner wall of the first blind hole 213, and the dielectric layer A second conductive seed layer is formed on a surface remote from the first surface 11a.

It is to be understood that other methods, such as blackening or chemisorption of conductive particles, may be employed, on the first surface 11a, the surface of the first dielectric film 21 close to the first surface 11a, and the electronic component 10 being close to the first A surface of a surface 11a, an inner wall of the second through hole 211, an inner wall of the first blind hole 213, and a surface of the dielectric layer away from the first surface 11a form a first conductive seed layer and a second conductive seed layer.

Next, a photoresist layer is respectively formed on the surfaces of the first conductive seed layer and the second conductive seed layer, and the portion corresponding to the first conductive line pattern 110 to be formed is removed by exposure and development. The photoresist pattern is removed from the portion corresponding to the second conductive line pattern 120 to form a second photoresist pattern.

Next, a first electroplated copper layer is formed on the surface of the first conductive seed layer exposed from the void of the first photoresist pattern, and a second surface is formed on the surface of the second conductive seed layer exposed from the second photoresist pattern Electroplated copper layer.

Finally, the first photoresist pattern and the second photoresist pattern are removed by stripping, and the first conductive seed layer originally covered by the first photoresist pattern is removed by microetching. Removing the second conductive seed layer that was originally covered by the second photoresist pattern. Thus, the first conductive seed layer on the first surface 11a and the first electroplated copper layer formed thereon together constitute the first conductive line pattern 110; the surface of the first dielectric film 21 away from the first surface 11a The second conductive seed layer on the second conductive copper layer and the second electroplated copper layer formed thereon jointly form the second conductive line pattern 120; The second conductive seed layer in the second through hole 211 and the second electroplated copper layer formed thereon form a conductive via 214 penetrating through the insulating substrate 11 and the first dielectric film 21; The second conductive seed layer formed on the second conductive seed layer together constitutes the first conductive blind via 215. The first conductive line pattern 110 and the second conductive line pattern 120 are electrically connected to each other through the conductive vias 214. The second conductive line pattern 120 and the first electrical connection end 103 are electrically connected to each other through the first conductive blind via 215.

It will be understood by those of ordinary skill in the art that the conductive vias 214 can also be formed by means of resin plug holes. That is, in the step of forming a second electroplated copper layer on the surface of the second conductive seed layer exposed from the second photoresist pattern, the second electroplated copper layer in the second via hole 211 does not need to be filled with electroplated copper. After the plating is completed, a resin plug hole may be formed in the second through hole 211 to fill the void in the second through hole 211.

In the sixth step, referring to FIG. 6, a second dielectric film 22 is pressed on the side of the first conductive line pattern 110, and a third dielectric film 23 is pressed on the side of the second conductive line pattern 120. The second dielectric film 22 covers the first conductive trace pattern 110, the first surface of the insulating substrate 11 exposed from the first conductive trace pattern 110, and the surface of the electronic component 10 adjacent to the first surface 11a. The third dielectric film 23 covers the second conductive line pattern 120 and the first dielectric film 21 exposed from the second conductive line pattern 120 is adjacent to the surface of the second surface 11b.

In this step, the second dielectric film 22 and the third dielectric film 23 are respectively pressed into the first conductive line pattern 110 and the second conductive line pattern 120 by thermocompression bonding. The second dielectric film 22 and the third dielectric film 23 may each be a polyimide (PI) or a polyethylene terephthalate (Polyethylene). Terephthalate (PET) or polyethylene naphthalate (PEN), PP (Prepreg) or ABF (Ajinomoto Build-up film), etc., preferably PP or ABF.

It will be understood by those skilled in the art that if the second conductive trace pattern 120 includes a plurality of electrical contact pads for electrically connecting to the outside, the second conductive trace pattern 120 can be an outer conductive trace layer. At this time, the third dielectric film 23 can also be omitted.

In the seventh step, referring to FIG. 7, a second blind hole 216a is formed in a region of the second dielectric film 22 corresponding to the second electrical connection end 105, and the second dielectric film 22 is formed on the second dielectric film 22. At least one second blind via 216b is formed in a region other than the region corresponding to the second electrical connection terminal 105, and at least one third blind via 217 is formed in the third dielectric film 23.

In this step, the second blind hole 216a, the second blind hole 216b, the second blind hole 216b, and the third blind hole 217 may be formed by laser ablation. The second blind via 216a extends only through the area of the second dielectric film 22 corresponding to the second electrical connection end 105 to expose a portion of the second electrical connection end 105. The second blind via 216b extends only through the second dielectric film 22 except for the region corresponding to the region of the second electrical connection 105 to expose a portion of the first conductive trace pattern 110. The third blind via 217 extends only through the third dielectric film 23 to expose a portion of the second conductive trace pattern 120. The number of the third blind holes 217 may be one or plural, and FIG. 7 is formed to form a third blind only through the third dielectric film 23 corresponding to the first electrical connection end 103 region. The hole 217 will be described as an example.

It can be understood that, after this step, a step of desmear may be further included to remove the second blind hole 216a, the second blind hole 216b, and the third blind. The slag inside the hole 217 is removed, so that it is possible to effectively prevent the slag from affecting the conductivity of the formed conductive hole during subsequent plating.

The eighth step, referring to FIG. 8, the first outer conductive layer 130 is formed on the surface of the second dielectric film 22 away from the insulating substrate 11, and the third dielectric film 23 is formed away from the surface of the insulating substrate 11. The second outer conductive layer 140, and the second blind hole 216a, the second blind hole 216b and the third blind hole 217 are respectively formed into a second conductive blind hole 218a, a second conductive blind hole 218b and a third conductive blind hole. 219. The first outer conductive layer 130 includes a plurality of first electrical contact pads 131 and a plurality of conductive traces (not shown). The second outer conductive layer 140 includes a plurality of second electrical contact pads 141 for electrically connecting to the outside and a plurality of conductive lines (not shown). The second conductive via 218a electrically connects the first outer conductive layer 130 and the second electrical connection end 105. The second conductive via 218b electrically connects the first outer conductive layer 130 and the first conductive trace pattern 110. The third conductive via 219 electrically connects the second conductive trace pattern 120 and the second outer conductive trace layer 140.

This step can be completed by using steps similar to the fifth step, and details are not described herein again.

The ninth step, referring to FIG. 9, forming a first solder resist layer 150 on the surface of the first outer conductive layer 130 and the surface of the second dielectric film 22 exposed from the first outer conductive layer 130, The surface of the outer conductive layer 140 and the surface of the third dielectric film 23 exposed from the second outer conductive layer 140 form a second solder resist layer 160. The first solder resist layer 150 has a plurality of first openings 151 corresponding to the plurality of first electrical contact pads 131 , and each of the first electrical contact pads 131 is exposed from the corresponding first opening 151 . The second solder resist layer 160 has a plurality of second openings 161 corresponding to the plurality of second electrical contact pads 141 , and each of the second electrical contact pads 141 is exposed from the corresponding second opening 161 .

In the tenth step, referring to FIG. 10, a first protective layer 170 is formed on a surface of each of the first electrical contact pads 131 exposed from the first opening 151; and each second electrical property is formed. The contact pad 141 forms a second protective layer 180 from the surface exposed by the second opening 161. Thus, a circuit board 100 having buried components embedded with electronic components 10 is obtained.

In this embodiment, the first protective layer 170 and the second protective layer 180 may be a single layer structure of a metal such as tin, lead, silver, gold, nickel, palladium or the like, or an alloy thereof, or may be two of the above metals or Two or more multilayer structures. The first protective layer 170 and the second protective layer 180 may also be an organic solder resist layer (OSP). When the first protective layer 170 and the second protective layer 180 are metal, the first protective layer 170 and the second protective layer 180 may be formed by electroless plating. When the first protective layer 170 and the second protective layer 180 are organic solder resist layers, the first protective layer 170 and the second protective layer 180 may be formed by a chemical method.

It should be understood by those skilled in the art that the number of electrical connection ends of the electronic component 10 is not limited to two in the embodiment, and may be three, four or more, and should be according to actual needs. set. It is also understood by those skilled in the art that the number of conductive vias of the conductive electronic component 10 and the conduction line pattern or the conductive circuit layer is not limited to two in the embodiment, and may also be Three, four or more should be set according to the number of electrical terminals of the electronic component 10.

Referring to FIG. 10 , the technical solution provides a circuit board 100 with embedded components embedded with an electronic component 10 , which includes the electronic component 10 , the insulating substrate 11 , the first dielectric film 21 , and the first Conductive line pattern 110, second conductive line pattern 120, second dielectric film 22, and first outer conductive layer layer 130. Said The insulating substrate 11 has opposing first and second surfaces 11a, 11b. The insulating substrate 11 is further provided with a first through hole 111 penetrating the first surface 11a and the second surface 11b. The cross-sectional area of the first through hole 111 is larger than the cross-sectional area of the electronic component 10. The electronic component 10 is received in the first through hole 111. The first dielectric film 21 covers the second surface 11b of the insulating substrate 11 and the electronic component 10, and fills a gap between the insulating substrate 11 and the electronic component 10. The first conductive line pattern 110 is formed on the first surface 11a of the insulating substrate 11. The second conductive line pattern 120 is formed on the surface of the first dielectric film 21 adjacent to the second surface 11b, electrically connected to the first conductive line pattern 110, and is disposed on the first The electronic component 10 of the first conductive blind via 215 in the dielectric film 21 is electrically connected. The second dielectric film 22 covers the first conductive line pattern 110, the first surface 11a of the insulating substrate 11 exposed from the first conductive line pattern 110, and the electronic component 10. The first outer conductive layer 130 is formed on a surface of the second dielectric film 22 adjacent to the first surface 11a. The first outer conductive layer 130 is electrically connected to the electronic component 10 through a second conductive via 218a disposed in the second dielectric film 22, and is disposed on the second dielectric film 22 The second conductive blind via 218b is electrically connected to the first conductive trace pattern 110.

According to the present invention, a circuit board having a buried component and a method of fabricating the same, the electronic component 10 is buried in the insulating substrate 11, thereby reducing the thickness of the circuit board 100 having the embedded component, and reducing the inner portion of the electronic component 10 The volume of the circuit board 100 in which the components are buried. In addition, since the electronic component 10 and the insulating substrate 11 are bonded together through the first dielectric film 21, the electronic component 10 is not easily moved relative to the first dielectric film 21 when the blind via hole forming the conductive blind hole is formed, which is improved. The alignment accuracy between the electronic component 10 and the blind via to be formed, thereby increasing the fabrication efficiency of the circuit board 100 having the embedded component.

Referring to FIG. 11, the present technical solution provides a package structure 200 including the above-described circuit board 100 having buried components. The package structure 200 includes a circuit board 100 having a buried component and a wafer 300.

The circuit board 100 having the embedded component is as described above, and details are not described herein again.

The wafer 300 is packaged in the circuit board 100 having embedded components. The wafer 300 has a plurality of third electrical contact pads 301 that are in one-to-one correspondence with the plurality of first electrical contact pads 131. Each of the first electrical contact pads 131 and the corresponding third electrical contact pads 301 are in electrical communication with one another via a solder ball 303. As such, a package structure 200 incorporating the wafer 300 can be obtained. The material of the solder ball 303 may be tin, lead or copper, or an alloy of tin, lead or copper. It is understood by those skilled in the art that the wafer 300 and the plurality of first electrical contact pads 131 can also be connected by wire bonding.

In the package structure 200 provided by the present technical solution, the electronic component 10 is buried in the insulating substrate 11, thereby reducing the thickness of the circuit board 100 having the embedded component, and reducing the circuit board 100 having the embedded component with the electronic component 10. The volume, in turn, reduces the volume of the package structure 200 having the wafer 300.

However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.

131‧‧‧First electrical contact pads

100‧‧‧Board with embedded components

200‧‧‧Package structure

300‧‧‧ wafer

301‧‧‧ Third electrical contact pad

303‧‧‧ solder balls

Claims (7)

A method of fabricating a circuit board having a buried component, comprising the steps of: providing a circuit substrate, the circuit substrate comprising an electronic component, an insulating substrate and a first dielectric film, the insulating substrate having an opposite first surface And the second surface, the insulating substrate further has a first through hole penetrating the first surface and the second surface, the first through hole having a cross-sectional area larger than a cross-sectional area of the electronic component, The electronic component is received in the first through hole, the first dielectric film covers the second surface of the insulating substrate and the electronic component, and fills a gap between the electronic component and the insulating substrate; Forming a first conductive line pattern on the first surface of the insulating substrate, forming a second conductive line pattern on the surface of the first dielectric film adjacent to the second surface, and electrically connecting the first conductive line a circuit pattern and a second conductive line pattern electrically connecting the second conductive line pattern and the electronic component; pressing a second dielectric film on a side of the first conductive line pattern The second dielectric film covers the first conductive line pattern, the first surface of the insulating substrate exposed from the first conductive line pattern, and the electronic component; and the surface of the second dielectric film away from the first surface a first outer conductive layer, electrically connecting the first outer conductive layer and the electronic component, electrically connecting the first outer conductive layer and the first conductive trace to obtain the circuit board having the embedded component . The method for fabricating a circuit board having a buried component according to claim 1, wherein the method of fabricating the circuit substrate comprises the steps of: providing the electronic component, an insulating substrate, and a support plate; The insulating substrate and the electronic component are disposed on the support plate such that the first surface is in contact with the support plate, and the electronic component is received in the first through hole; Pressing the first dielectric film on a side of the second surface of the insulating substrate such that the first dielectric film covers the second surface of the insulating substrate and the surface of the electronic component is away from the support plate And filling a gap between the electronic component and the insulating substrate; removing the support plate to obtain the circuit substrate. The method of manufacturing a circuit board having a buried component according to claim 2, wherein the support plate is further provided with a release film adjacent to a surface of the insulating substrate. The method for fabricating a circuit board having a buried component according to claim 1, wherein when the first conductive line pattern and the second conductive line pattern are formed, electrically forming the first conductive line is further formed The pattern and the second conductive line pattern conductive via form a first conductive blind via that electrically conducts the second conductive trace pattern and the electronic component. The method of manufacturing a circuit board with embedded components according to claim 1, wherein the electronic component comprises a first electrical connection end and a second electrical connection end, the first of the insulating substrate Forming a first conductive line pattern on the surface, forming a second conductive line pattern on the surface of the first dielectric film adjacent to the second surface, and electrically connecting the first conductive line pattern and the second conductive line pattern Electrically connecting the second conductive line pattern and the electronic component, comprising the steps of: forming at least one second on the insulating substrate of the circuit substrate and the region of the first dielectric film corresponding to the insulating substrate a through hole, a first blind hole is formed in a region of the first dielectric film corresponding to the first electrical connection end of the electronic component; and the first surface, the first dielectric film is adjacent to the first surface Forming a first conductive seed layer on the surface of the surface and the electronic component adjacent to the first surface, an inner wall of each of the through holes of the at least one second through hole, an inner wall of the first blind hole, and First Forming a second conductive seed layer on the surface of the dielectric film away from the first surface; forming a photoresist layer on the surfaces of the first conductive seed layer and the second conductive seed layer, respectively, and adopting exposure and development a manner corresponding to the pattern of the first conductive line to be formed Partially removing a first photoresist pattern, removing a portion corresponding to the second conductive line pattern to form a second photoresist pattern; and forming a second photoresist pattern from the first photoresist pattern Forming a first electroplated copper layer on the surface of the first conductive seed layer exposed by the void, forming a second electroplated copper layer on the surface of the second conductive seed layer exposed from the second photoresist pattern; removing the film by stripping Depicting the first photoresist pattern and the second photoresist pattern, and removing the first conductive seed layer originally covered by the first photoresist pattern by microetching to remove the original coating a second conductive seed layer covered by the second photoresist pattern, such that the first conductive seed layer on the first surface and the first electroplated copper layer formed thereon together constitute a first conductive line pattern, a second conductive seed layer on the surface of the first dielectric film away from the first surface and a second electroplated copper layer formed thereon to form a second conductive line pattern, located in the second through hole Second conductive seed layer and formation The second electroplated copper layer thereon constitutes a conductive through hole penetrating the insulating substrate and the first dielectric film, and the second electroplated copper layer located in the first blind hole forms a second electroplated copper layer thereon to form a first a conductive via hole electrically connecting the first conductive line pattern and the second conductive line pattern, wherein the first conductive blind hole electrically connects the second conductive line pattern and the first electrical connection end. The method of manufacturing a circuit board with embedded components according to claim 1, wherein the electronic component is a multilayer ceramic capacitor, and the first electrical connection end and the second electrical connection end are external electrode. The method for fabricating a circuit board having a buried component according to claim 1, wherein when the second conductive film is pressed on one side of the first conductive line pattern, the second conductive film is further Pressing a third dielectric film on one side of the line pattern, the third dielectric film covering the second conductive line pattern and the first dielectric film exposed from the second conductive line pattern are adjacent to the first a surface of the second surface; a surface of the second dielectric film away from the insulating substrate Forming a first outer conductive layer, forming a second outer conductive layer on the surface of the third dielectric film away from the insulating substrate, and electrically connecting the second outer conductive layer and the second conductive line A pattern is obtained to obtain the circuit board having the embedded component.