TWI566355B - Printed circuit board with electronic component and method for manufacturing same - Google Patents

Description

Electronic component packaging structure and manufacturing method

The present invention relates to the field of circuit board manufacturing, and in particular, to an electronic component package structure and a manufacturing method thereof.

The electronic component package structure can provide electrical connection, protection, support, heat dissipation, assembly and other functions for the electronic component, thereby achieving multi-pinning, reducing the package product volume, improving electrical performance and heat dissipation, ultra-high density or multi-electronic component module. Purpose.

Therefore, it is necessary to provide an electronic component package structure and a manufacturing method thereof.

A method for fabricating an electronic component package structure, comprising the steps of: providing a copper foil, forming a first conductive circuit layer on a surface of the copper foil, the first conductive circuit layer comprising a plurality of electrical contact pads and a plurality of first pads Forming a plurality of conductive pillars on the surface of the plurality of electrical contact pads, the plurality of conductive pillars being electrically connected to the plurality of electrical contact pads; soldering the first electrons on the surfaces of the plurality of first solder pads a first dielectric layer is formed in a gap between the first conductive circuit layer and the conductive pillar, and the first dielectric layer is coated on the first electronic component; the copper foil is removed; Forming a second dielectric layer and a second conductive circuit layer on the first electronic component side of the core package substrate, a first conductive blind via is formed in the second dielectric layer, and the first conductive via is electrically connected The second conductive circuit layer and the conductive pillar; and forming a first side on the second conductive circuit layer side a solder resist layer, wherein a thermal expansion coefficient of the first dielectric layer is between a thermal expansion coefficient of the first electronic component and a thermal expansion coefficient of the first solder resist layer, thereby forming the electronic component package structure.

An electronic component package structure includes a first dielectric layer, a first conductive circuit layer embedded on one side of the first dielectric layer, and the other side of the first dielectric layer and the first conductive circuit layer An electrically connected conductive pillar, a first electronic component embedded in the first dielectric layer, a second dielectric layer formed on the side of the first conductive layer from the first conductive layer, and formed in the second dielectric layer a second conductive circuit layer of the electrical layer remote from the surface of the first dielectric layer, a first conductive blind via penetrating the second dielectric layer and electrically connecting the conductive pillar and the second conductive wiring layer, and formed in the second a first solder resist layer on the side of the conductive circuit layer; the first conductive circuit layer includes a plurality of electrical contact pads and a plurality of first pads, the conductive pillars are formed on the surface of the plurality of electrical contact pads and electrically Connecting the plurality of electrical contact pads, the first electronic component being soldered to the plurality of first pads; a coefficient of thermal expansion of the first dielectric layer being between a coefficient of thermal expansion of the first electronic component and a first Between the thermal expansion coefficients of a solder mask.

Compared with the prior art, the first electronic component of the present invention is formed inside the electronic component package structure, so that the total thickness of the electronic component package structure can be reduced, which is advantageous for thinning and thinning of the electronic component package structure.

11‧‧‧Loading board

12‧‧‧ copper foil

13‧‧‧thermoplastic colloid layer

14‧‧‧First conductive circuit layer

141‧‧‧Electrical contact pads

142‧‧‧First pad

15‧‧‧First photoresist layer

16‧‧‧conductive column

17‧‧‧Second photoresist layer

18‧‧‧First electronic components

200‧‧‧First board intermediate

19‧‧‧ solder paste

20‧‧‧First dielectric layer

220‧‧‧Second circuit board intermediate

240‧‧‧ core package substrate

21‧‧‧Second dielectric layer

22‧‧‧Second conductive circuit layer

23‧‧‧ Third dielectric layer

24‧‧‧ Third conductive circuit layer

25‧‧‧First conductive blind hole

26‧‧‧Second conductive blind hole

27‧‧‧First solder mask

271‧‧‧First solder mask opening

28‧‧‧Second solder mask

281‧‧‧Second solder mask opening

221,221'‧‧‧second solder pad

241,241'‧‧‧ Third pad

260‧‧‧First electronic component package structure

29,29’‧‧‧First Tin Ball

30‧‧‧Second electronic components

31,31’‧‧‧Second Tin Ball

280‧‧‧Second electronic component package structure

32‧‧‧Another electronic component package structure

300‧‧‧ Third electronic component package structure

1 is a cross-sectional view of a carrier sheet provided with an embodiment of the present invention.

2 is a cross-sectional view showing a patterned first photoresist layer formed on the surface of the copper foil of FIG. 1.

Figure 3 is a cross-sectional view showing the surface of the copper foil of Figure 2 after the first conductive wiring layer is formed.

4 is a view showing the formation of a patterned second photoresist layer on the surface of the first conductive wiring layer of FIG. Cutaway view.

5 is a cross-sectional view of the patterned second photoresist layer gap of FIG. 4 after forming a conductive pillar.

Figure 6 is a cross-sectional view showing the first and second photoresist layers in Figure 5 removed.

Figure 7 is a cross-sectional view showing a first electronic component soldered to the surface of the first conductive wiring layer of Figure 6.

8 is a cross-sectional view showing the first conductive wiring layer, the conductive pillar gap of FIG. 7, forming a dielectric layer, and covering the first electronic component with a dielectric layer.

FIG. 9 is a schematic view showing the carrier plate and the thermoplastic colloid layer of FIG. 8 separated and separated to obtain two second circuit board intermediates.

Figure 10 is a cross-sectional view showing a core package substrate obtained by removing the copper foil of the second circuit board intermediate of Figure 9.

FIG. 11 is a schematic view showing the second and second conductive circuit layers being layered on both sides of the second circuit board intermediate body of FIG. 10.

Figure 12 is a cross-sectional view showing the formation of a solder resist layer on the surfaces of the second and third conductive wiring layers of Figure 11 .

Figure 13 is a cross-sectional view showing the formation of solder balls on the surfaces of the second and third conductive wiring layers exposed from the solder resist layer in Fig. 12 and the soldering of the second electronic component on the surface of the second conductive wiring layer.

FIG. 14 is a cross-sectional view showing another embodiment of the second and third conductive wiring layers exposed from the solder resist layer of FIG. 12, and after soldering another electronic component package structure on the surface of the second conductive wiring layer.

Referring to FIG. 1-14, an embodiment of the present invention provides a method for fabricating an electronic component package structure 100, including the following steps: First, referring to FIG. 1, a carrier board 11 is provided, and the carrier board 11 is opposite. A copper foil 12 is attached to both sides.

The carrier plate 11 has a flat shape. The carrier plate 11 may be a rigid support material such as a resin plate, a ceramic plate, or a metal plate.

In this embodiment, the two copper foils 12 are respectively attached to opposite sides of the carrier plate 11 through a thermoplastic colloid layer 13 . Among them, the reason why the thermoplastic colloid is used to laminate the copper foil is to facilitate removal of the carrier sheet 11 in a subsequent step.

In other embodiments, the two copper foils 12 may also be edge-bonded only to the carrier plate 11, and the portion to be bonded to the carrier plate 11 may be cut and removed when the carrier plate 11 is removed, thereby separating the Carrying board 11.

In the second step, referring to FIG. 2-3, the first conductive circuit layer 14 is formed on the surface of the copper foil 12 on both sides.

The first conductive circuit layer 14 includes a plurality of electrical contact pads 141 and a plurality of first pads 142 . In the present embodiment, the first conductive wiring layer 14 is formed by selective plating. Specifically, first, referring to FIG. 2, a patterned first photoresist layer 15 is formed on the surface of the copper foil 12 on both sides, so that a portion of the copper foil 12 is removed from the patterned first photoresist layer 15 Exposed; thereafter, please refer to FIG. 3, electroplating, thereby exposing the surface of the copper foil 12 from the patterned first photoresist layer 15, that is, the patterned first photoresist layer The gap of 15 forms the first conductive wiring layer 14.

In other embodiments, the forming of the first conductive circuit layer 14 may further include removing The step of patterning the first photoresist layer 15.

In the third step, referring to FIG. 4-6, conductive pillars 16 are formed on the surface of the first conductive circuit layer 14 on both sides.

In this embodiment, the conductive pillars 16 are substantially cylindrical, and the conductive pillars 16 are formed on the surface of the plurality of electrical contact pads 141 and electrically connected to the plurality of electrical contact pads 141 through selective plating. The conductive pillars 16 are formed in a manner. Specifically, first, referring to FIG. 4, a patterned second photoresist layer 17 is formed on a surface of a portion of the first conductive circuit layer 14 and the surface of the first photoresist layer 15, the patterned second light. a resist layer 17 covering the plurality of first pads 142; thereafter, referring to 5, electroplating, thereby exposing the surface of the first conductive wiring layer 14 from the patterned second photoresist layer 17, That is, the gap of the patterned second photoresist layer 17 forms a conductive pillar 16; then, referring to FIG. 6, the patterned first photoresist layer 15 and the second photoresist layer 17 are removed.

In a fourth step, referring to FIG. 7, a first electronic component 18 is provided. The first electronic component 18 is electrically connected to the plurality of first pads 142 to form a first circuit board intermediate body 200.

In this embodiment, the first electronic component 18 is soldered to the surface of the plurality of first pads 142 by solder paste 19. The thickness of the first electronic component 18 is smaller than the height of the conductive pillar 16 protruding from the first conductive wiring layer 14 , thereby moving the first electronic component 18 away from the surface of the first conductive wiring layer 14 . Lower than the surface of the conductive pillar 16 away from the first conductive wiring layer 14 or substantially flush with the surface of the conductive pillar 16 away from the first conductive wiring layer 14.

In the fifth step, referring to FIG. 8, the first conductive circuit layer 14 and the conductive pillar 16 are The gap forms a first dielectric layer 20 such that the first dielectric layer 20 encapsulates the first electronic component 18.

In this embodiment, the first dielectric layer 20 is formed by injection molding, and the surface of the conductive pillar 16 away from the first conductive wiring layer 14 is flush with the surface of the first dielectric layer 20. Thereby, the surface of the conductive pillar 16 away from the first conductive wiring layer 14 is exposed to the first dielectric layer 20. Specifically, firstly, a mold (not shown) is provided, the mold includes a cavity and a glue injection passage, and the first circuit board intermediate body 200 is received in the cavity; and then The glue injection channel injects a colloid into the cavity, so that the colloid fills the gap between the first conductive circuit layer 14 and the conductive pillar 16 and covers the first electronic component 18; then, the colloid is cured The first dielectric layer 20 is formed; thereafter, the first circuit board intermediate body 200 on which the first dielectric layer 20 is formed is taken out of the cavity.

In this embodiment, the coefficient of thermal expansion (CTE) of the first electronic component 18 is close to the coefficient of thermal expansion of the first dielectric layer 20. The material of the first dielectric layer 20 may be a commonly used injection molding material. The amount of the injected colloid is controlled such that the surface of the conductive pillar 16 away from the first conductive wiring layer 14 is flush with the surface of the first dielectric layer 20.

In other embodiments, an excess of colloid may also be injected to cause the colloid to cover the conductive pillar 16 away from the surface of the first conductive wiring layer 14, and then the conductive pillar 16 is moved away from the surface by molding. The surface of the first conductive wiring layer 14 is exposed to the first dielectric layer 20.

In the sixth step, referring to FIG. 9, the carrier board 11 and the two thermoplastic colloid layers 13 are separated and removed, thereby obtaining two second circuit board intermediate bodies 220.

In this embodiment, heating causes the thermoplastic colloid layer 13 to lose its viscosity, thereby separating the carrier sheet 11 and the two thermoplastic colloid layers 13 apart.

In the seventh step, referring to FIG. 10, the copper foil 12 of each of the second circuit board intermediate bodies 220 is removed, thereby obtaining a core package substrate 240.

In this embodiment, the copper foil 12 is removed by rapid etching, that is, the concentration of the etching liquid and the etching time are controlled, so that the copper foil 12 is etched away, but the first conductive wiring layer 14 is not removed by etching. .

The core package substrate 240 includes a first dielectric layer 20 , a first conductive circuit layer 14 embedded on one side of the first dielectric layer 20 , and a conductive pillar 16 electrically connected to the first conductive circuit layer 14 . The first electronic component 18 is buried inside the first dielectric layer 20. The first conductive circuit layer 14 includes a plurality of electrical contact pads 141 and a plurality of first pads 142 . The surface of the first conductive circuit layer 14 away from the conductive pillar 16 is flush with the surface of the first dielectric layer 20 side. The conductive pillars 16 are formed on the surface of the plurality of electrical contact pads 141 and electrically connected to the plurality of electrical contact pads 141. The conductive pillar 16 is exposed to the first dielectric layer 20 away from the surface of the first conductive wiring layer 14. The first electronic component 18 is soldered to the surfaces of the plurality of first pads 142 by solder paste 19.

The eighth step, referring to FIG. 11 , is layered on both sides of the core package substrate 240 to form a second dielectric layer 21 and a second conductive layer on the first electronic component 18 side of the core package substrate 240. The circuit layer 22 and the third dielectric layer 23 and the third conductive wiring layer 24 are sequentially formed on the first conductive wiring layer 14 side of the core package substrate 240.

A first conductive blind via 25 is formed in the second dielectric layer 21, the first conductive via 25 has a substantially trapezoidal cross section, and the first conductive via 25 is electrically connected to the second conductive trace layer. 22 and the conductive column 16. a second conductive layer is also formed in the third dielectric layer 23 The second conductive blind via 26 has a substantially trapezoidal cross section, and the second conductive via 26 is electrically connected to the third conductive trace layer 24 and the first conductive trace layer 14 .

In this embodiment, first, two prepregs are provided, and the two prepregs are respectively laminated on both sides of the core package substrate 240, and pressed to form the second dielectric layer 21 and the third dielectric layer. The second layer and the second conductive layer 25 are formed on the second and third dielectric layers 21 and 23 respectively; and then the second and second conductive vias 25 are respectively formed by plating in the blind holes. And 26, wherein the blind via is formed to form a conductive blind via, and the second and third conductive traces are formed on the surfaces of the second and third dielectric layers 21 and 23 by a semi-additive method or an additive method, respectively. Layers 22, 24. The two prepregs may be a toughening-containing resin such as a glass cloth-based epoxy resin.

In other embodiments, the second and second conductive vias 25, 26 may also be formed by filling a conductive paste.

In a ninth step, referring to FIG. 12, a first solder resist layer 27 is formed on the second conductive wiring layer 22 side, and a second solder resist layer 28 is formed on the third conductive wiring layer 24 side, thereby obtaining the first Electronic component package structure 260.

A plurality of first solder mask openings 271 are formed in the first solder resist layer 27, and a portion of the second conductive trace layer 22 is exposed from the plurality of first solder mask openings 271 to form a second solder. a second solder resist layer opening 281 is formed in the second solder resist layer 28, and a portion of the third conductive trace layer 24 is exposed from the plurality of second solder mask openings 281 to form The third pad 241.

Preferably, the thermal expansion coefficient of the first dielectric layer 20 is between the thermal expansion coefficients of the first electronic component 18 and the first solder resist layer 27 to reduce the bending of the plate caused by the difference in thermal expansion coefficient of the material. Bad, etc.

In the tenth step, referring to FIG. 13, a first solder ball 29 is formed on the surface of the second pad 221, and a second electronic component 30 is soldered to the second pad 221, in the third A second solder ball 31 is formed on the surface of the pad 241 to form a second electronic component package structure 280.

In this embodiment, the first solder ball 29 is formed on a portion of the surface of the second solder pad 221, and the second solder pad 221 soldering the second electronic component 30 is arranged to have a lower density than the second solder. The second pad 221 of the component has a high density of arrangement. The second solder ball 31 can be used for electrically connecting an electronic component, an electronic component package structure similar to the present invention, or a circuit board containing no electronic component, or the like.

The second electronic component package structure 280 includes a first dielectric layer 20, a first conductive circuit layer 14 embedded on one side of the first dielectric layer 20, and is embedded on the other side of the first dielectric layer 20 and The conductive pillars 16 electrically connected to the first conductive circuit layer 14 , the first electronic component 18 embedded in the first dielectric layer 20 , and the first dielectric layer 20 are separated from the first conductive trace layer 14 . a second dielectric layer 21 on the side, a second conductive circuit layer 22 formed on the surface of the second dielectric layer 21 away from the first dielectric layer 20, and a second dielectric layer 21 and electrically connected to the conductive pillars 16 A first conductive blind via with the second conductive trace layer 22. The first conductive circuit layer 14 includes a plurality of electrical contact pads 141 and a plurality of first pads 142 . The surface of the first conductive circuit layer 14 away from the conductive pillar 16 is flush with the surface of the first dielectric layer 20 side. The conductive pillars 16 are formed on the surface of the plurality of electrical contact pads 141 and electrically connected to the plurality of electrical contact pads 141. The conductive pillar 16 is exposed to the first dielectric layer 20 away from the surface of the first conductive wiring layer 14. The first electronic component 18 is soldered to the surfaces of the plurality of first pads 142 by solder paste 19.

The second electronic component package structure 280 further includes sequentially formed on the first conductive A third dielectric layer 23 and a third conductive circuit layer 24 are sequentially formed on the side of the circuit layer 14 , and a second conductive blind via 26 is formed in the third dielectric layer 23 , and the second conductive blind via 26 is electrically connected The third conductive circuit layer 24 and the first conductive circuit layer 14 are described.

The second electronic component package structure 280 further includes a first solder resist layer 27 formed on the second conductive wiring layer 22 side, and a second solder resist layer 28 formed on the third conductive wiring layer 24 side. A plurality of first solder mask openings 271 are formed in the first solder resist layer 27, and a portion of the second conductive trace layer 22 is exposed from the plurality of first solder mask openings 271 to form a second solder. a second solder resist layer opening 281 is formed in the second solder resist layer 28, and a portion of the third conductive trace layer 24 is exposed from the plurality of second solder mask openings 281 to form The third pad 241. A portion of the second pad 221 is formed with a first solder ball 29 on the surface thereof, and a second electronic component 30 is soldered to the second pad 221 . A second solder ball 31 is formed on the surface of the third pad 241.

In other embodiments, after the second electronic component 30 is soldered, an encapsulant is also implanted on the sides and bottom of the second electronic component 30 to fix the second electronic component 30.

In another embodiment, referring to FIG. 14, a plurality of first solder balls 29' are formed on the surface of the plurality of second pads 221', and another electronic component package structure 32 is soldered to the plurality of second A second solder ball 31' is formed on the pad 221' and a surface of the third pad 241' is formed, thereby forming a third electronic component package structure 300. The second solder ball 31' may be used for electrically connecting an electronic component, an electronic component package structure similar to the present invention, or a circuit board containing no electronic component, or the like. After the other electronic component package structure 32 is soldered, an encapsulant may be injected on the side and bottom of the other electronic component package structure 32 to fix the other electronic component package structure 32.

The electronic component package structure of the present invention may include more conductive circuit layers and dielectric layers, and the method of layering may refer to the method of the above eighth step.

The prior art needs to cover the electronic component with the underfill to fill the gap between the electronic component and the substrate, and often the filling is incomplete; compared to the prior art, the electronic component packaging structure and the manufacturing method of the embodiment of the present invention are formed by injection molding. The first dielectric layer 20 can make the first dielectric layer 20 completely cover the first electronic component 18 without forming a void, and can also not use an underfill, thereby simplifying the manufacturing process; The thermal expansion coefficient of an electronic component 18 is close to the thermal expansion coefficient of the first dielectric layer 20, thereby reducing defects such as bending, cracking, etc. caused by a large difference in thermal expansion coefficient of the material; further, the first electronic component 18 of the present invention is formed in the electron The inside of the component package structure can reduce the total thickness of the electronic component package structure, which is beneficial to the thinning of the electronic component package structure. In addition, the conductive pillar 16 is formed by the second photoresist layer 17 in the present case, and the conductive pillar 16 is directly plated. Formed on the surface of the first conductive circuit layer 14, so that electrical contact with the first conductive circuit layer 14 is relatively stable.

However, the above description is only a preferred embodiment of the present invention, and the claim of the present invention cannot be limited thereby. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included in the following claims.

14‧‧‧First conductive circuit layer

16‧‧‧conductive column

18‧‧‧First electronic components

19‧‧‧ solder paste

20‧‧‧First dielectric layer

21‧‧‧Second dielectric layer

22‧‧‧Second conductive circuit layer

23‧‧‧ Third dielectric layer

24‧‧‧ Third conductive circuit layer

25‧‧‧First conductive blind hole

26‧‧‧Second conductive blind hole

27‧‧‧First solder mask

271‧‧‧First solder mask opening

28‧‧‧Second solder mask

221‧‧‧Second pad

241‧‧‧ Third pad

29‧‧‧First Tin Ball

30‧‧‧Second electronic components

31‧‧‧ Second Tin Ball

280‧‧‧Second electronic component package structure

Claims (11)

A method for fabricating an electronic component package structure, comprising the steps of: providing a copper foil, forming a first conductive circuit layer on a surface of the copper foil, the first conductive circuit layer comprising a plurality of electrical contact pads and a plurality of first pads Forming a plurality of conductive pillars on the surface of the plurality of electrical contact pads, the plurality of conductive pillars being electrically connected to the plurality of electrical contact pads; soldering the first electrons on the surfaces of the plurality of first solder pads a first dielectric layer is formed in a gap between the first conductive circuit layer and the conductive pillar, and the first dielectric layer is coated on the first electronic component; the copper foil is removed to obtain a core Forming a substrate; forming a second dielectric layer and a second conductive circuit layer on the first electronic component side of the core package substrate, and forming a first conductive blind via in the second dielectric layer, a conductive via hole electrically connecting the second conductive circuit layer and the conductive pillar; and forming a first solder resist layer on the second conductive trace layer side, wherein a thermal expansion coefficient of the first dielectric layer is between Thermal expansion coefficient of the first electronic component and heat of the first solder resist layer Between the expansion coefficient, to thereby form the electronic device package structure. The method for fabricating an electronic component package structure according to claim 1, wherein the copper foil is supported on a carrier plate, and the carrier plate is removed before the copper foil is removed. The method for fabricating an electronic component package structure according to claim 2, wherein the copper foil is attached to the surface of the carrier plate through a thermoplastic colloid layer; in the step of removing the carrier plate, by heating The thermoplastic colloid layer is rendered viscous, and the carrier sheet is separated from the copper foil to remove the carrier sheet. The method of fabricating an electronic component package structure according to claim 1, wherein the The method for forming a first conductive circuit layer includes: forming a patterned first photoresist layer on a surface of the copper foil, exposing a portion of the copper foil from the patterned first photoresist layer; and thereafter, plating Thereby, the surface of the copper foil exposed from the patterned first photoresist layer forms a first conductive wiring layer. The method for fabricating an electronic component package structure according to claim 4, wherein the method of forming the conductive pillar comprises: patterning a portion of the surface of the first conductive wiring layer and the surface of the first photoresist layer a second photoresist layer, the patterned second photoresist layer covers the plurality of first pads; thereafter, electroplating to expose the first layer from the patterned second photoresist layer The surface of the conductive circuit layer forms a conductive pillar; then, the patterned first photoresist layer and the second photoresist layer are removed. The manufacturing method of the electronic component package structure of claim 1, wherein the thickness of the first electronic component is smaller than a height of the conductive pillar protruding from the first conductive circuit layer, thereby a surface of the first electronic component away from the first conductive wiring layer is lower than a surface of the conductive pillar away from the first conductive wiring layer, or substantially flush with a surface of the conductive pillar away from the first conductive wiring layer level. The method for fabricating an electronic component package structure according to claim 1, wherein the second dielectric layer is formed by injection molding; the conductive pillar is away from a surface and a surface of the first conductive wiring layer. The surface of the first dielectric layer is flush, such that the conductive pillars are exposed to the first dielectric layer away from the surface of the first conductive wiring layer. The method for fabricating an electronic component package structure according to claim 1, wherein after forming the second dielectric layer and the second conductive wiring layer and before forming the first solder resist layer, the method further comprises the step of: a third dielectric layer and a third conductive circuit layer are sequentially formed on the first conductive circuit layer side of the layer package substrate, and a second conductive blind hole is formed in the third dielectric layer, and the second conductive blind via is electrically connected The third conductive circuit layer and the first conductive circuit layer. The method for fabricating an electronic component package structure according to claim 8, wherein the forming method Forming a second solder resist layer on the side of the third conductive circuit layer simultaneously with the first solder resist layer; forming a plurality of first solder resist layer openings in the first solder resist layer, and partially forming the second a conductive circuit layer is exposed from the plurality of first solder mask openings to form a second solder pad; a plurality of second solder mask openings are formed in the second solder resist layer, and the third conductive trace is formed A layer is exposed from the plurality of second solder mask openings to form a third pad. The method of fabricating an electronic component package structure according to claim 9, wherein a first solder ball is formed on a portion of the surface of the second pad, and a second electronic component is soldered to the second pad. A second solder ball is formed on the surface of the third pad. The method of fabricating an electronic component package structure according to claim 9, wherein a first solder ball is formed on the surface of the plurality of second pads, and another electronic component package structure is soldered to the second solder On the pad, a second solder ball is formed on the surface of the third pad.