CN111354687B - Packaging structure and preparation method thereof - Google Patents
Packaging structure and preparation method thereof Download PDFInfo
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- CN111354687B CN111354687B CN201811571228.0A CN201811571228A CN111354687B CN 111354687 B CN111354687 B CN 111354687B CN 201811571228 A CN201811571228 A CN 201811571228A CN 111354687 B CN111354687 B CN 111354687B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 68
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 239000010410 layer Substances 0.000 claims description 194
- 238000000034 method Methods 0.000 claims description 44
- 239000000463 material Substances 0.000 claims description 21
- 238000003825 pressing Methods 0.000 claims description 21
- 239000004020 conductor Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 17
- 238000004080 punching Methods 0.000 claims description 12
- 238000009826 distribution Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 239000012790 adhesive layer Substances 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 6
- 239000000945 filler Substances 0.000 claims 3
- 239000003292 glue Substances 0.000 claims 1
- 239000000853 adhesive Substances 0.000 description 17
- 230000001070 adhesive effect Effects 0.000 description 17
- 238000010586 diagram Methods 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000013007 heat curing Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229910052755 nonmetal Inorganic materials 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
The application discloses a packaging structure and a preparation method of the packaging structure, wherein the packaging structure comprises the following components: a circuit layer; the pattern layer is fixedly arranged on the circuit layer; at least one electronic component disposed on the circuit layer and electrically connected to the circuit layer; the packaging body is arranged on the circuit layer and is used for embedding and packaging the pattern layer and at least one electronic element; the pattern layer is provided with a target pattern for positioning at least one electronic element. Through the mode, the quality of the packaging structure can be improved.
Description
Technical Field
The present application relates to the field of electronic device packaging technology, and in particular, to a packaging structure and a method for manufacturing the packaging structure.
Background
Along with the continuous development of technology, miniaturization of electronic equipment becomes an industry development trend, and the electronic element is packaged by adopting a buried packaging method, so that the size of the electronic equipment can be effectively reduced, the service life of the electronic element is prevented from being influenced by external environment, and the product quality is more reliable.
In the prior art, in the process of pressing and packaging the embedded electronic component by adopting the semi-cured material, the distribution condition of pressure in the pressing process cannot be determined, so that the quality problems of infirm packaging, electronic component damage and the like of the packaging structure are often caused by unreasonable pressure respectively.
The inventor of the application finds that the existing packaging structure has poor product quality and high rejection rate in the long-term research and development process.
Disclosure of Invention
The application mainly solves the technical problem of providing a packaging structure and a preparation method of the packaging structure, which can improve the quality of the packaging structure.
In order to solve the technical problems, the application adopts a technical scheme that: a package structure is provided.
Wherein, this packaging structure includes:
a circuit layer;
the pattern layer is fixedly arranged on the circuit layer;
at least one electronic component disposed on the circuit layer and electrically connected to the circuit layer;
the packaging body is arranged on the circuit layer and is used for embedding and packaging the pattern layer and at least one electronic element;
the pattern layer is provided with a target pattern for positioning at least one electronic element.
In order to solve the technical problems, the application adopts another technical scheme that: a method for manufacturing a package structure is provided.
Wherein the method comprises the following steps:
providing a substrate and fixing the circuit layer on the substrate;
a pattern layer is fixedly arranged on the circuit layer, and a target pattern for positioning at least one electronic element is arranged on the pattern layer;
at least one electronic element is arranged on the circuit layer and is electrically connected with the circuit layer;
sleeving the packaging shell on the circuit layer and filling the packaging shell with the filling material to obtain a filled packaging shell;
and carrying out blind holes on the filled packaging shell to expose the target patterns, and pressing the filling material according to the target patterns so that the filling material and the packaging shell embed and package the pattern layer and at least one electronic element to obtain a packaging structure.
The beneficial effects of the application are as follows: compared with the prior art, the application has the advantages that the pattern layer is arranged in the packaging structure, the target pattern arranged on the pattern layer can be used for positioning at least one electronic element, and the pressure distribution on the pressing plate is determined according to the distribution of the electronic elements in the packaging structure, so that the packaging structure can be tightly pressed in the pressing process, the electronic elements are prevented from being damaged, and the product quality is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:
FIG. 1 is a schematic diagram of a package structure according to an embodiment of the present application;
FIG. 2 is a schematic diagram of an embodiment of the patterning layer 200;
FIG. 3 is a schematic view of another embodiment of a package structure according to the present application;
FIG. 4 is a schematic diagram of a package structure according to a third embodiment of the present application;
FIG. 5 is a schematic flow chart of an embodiment of a method for manufacturing a package structure according to the present application;
FIG. 6 is a flowchart illustrating an embodiment of step S500 in FIG. 5;
FIG. 7 is a flowchart illustrating the step S300 in FIG. 5;
FIG. 8 is a flowchart illustrating an embodiment of step S320 in FIG. 7;
fig. 9 is a flowchart illustrating another embodiment of step S300 in fig. 5.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Referring to fig. 1 and 2, fig. 1 is a schematic structural diagram of an embodiment of a package structure according to the present application, and fig. 2 is a schematic structural diagram of an embodiment of the pattern layer 200, where the package structure includes:
a wiring layer 100; a pattern layer 200, wherein the pattern layer 200 is fixedly arranged on the circuit layer 100; at least one electronic component 300 disposed on the circuit layer 100 and electrically connected to the circuit layer 100; a package 400 disposed on the circuit layer 100 and embedding and packaging the pattern layer 200 and at least one of the electronic components 300; wherein the pattern layer 200 is provided with a target pattern 210 for positioning at least one of the electronic components.
In this embodiment, the pattern layer 200 is disposed in the package structure, and the pattern layer 200 is provided with the target pattern 210, so that at least one electronic component 300 can be positioned by the target pattern 210, and the pressure distribution on the pressing plate can be determined according to the distribution of the electronic components 300 in the package structure, so that the package structure can be pressed tightly in the pressing process, damage to the electronic components is avoided, and the product quality is improved.
Further, the pattern layer 200 is disposed between the circuit layer 100 and at least one of the electronic components 300, and at least one of the electronic components 300 is electrically connected to the circuit layer 100 through the pattern layer 200. In this embodiment, the pattern layer 200 is made of a conductive material, and when only one electronic component 300 is embedded and only one pin is provided in the electronic component 300, the pattern layer 200 can be used as a pin, so that the electronic component 300 and the circuit layer 100 are electrically connected through the pattern layer 200, the package structure can be effectively simplified, and the miniaturization of the package structure can be further realized.
Referring to fig. 3, fig. 3 is a schematic structural diagram of another embodiment of a package structure according to the present application, in this embodiment, a pattern layer conductive pillar 220 penetrating through the pattern layer 200 is further disposed on the pattern layer 200, and one end of the pattern layer conductive pillar 220 is connected to the electronic component 300, and the other end is connected to the circuit layer 100, so that at least one electronic component 300 is electrically connected to the circuit layer 100. Of course, the pattern layer 200 may be a whole solid structure, or may have a via structure, and the electronic device 300 is located on the solid structure that is alternately arranged. In addition, the material of the patterned conductive pillars 220 may be a conductive metal, such as copper; a composite material, such as a ceramic column with a conductive material coated on the outer periphery, may be used, so long as the electrical connection between the electronic component 300 and the circuit layer 100 is achieved.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a third embodiment of a package structure according to the present application, in this embodiment, at least one through hole (not shown) is disposed on the pattern layer 200, and at least one electronic component 300 is accommodated in the through hole. The number of the through holes can be one or more, and the through holes can be any shape; the shape of each through hole is the same or different, and the number of the electronic components 300 accommodated in each through hole is the same or different. In one embodiment, the through holes are rectangular holes, which not only facilitates the molding of the through holes, but also facilitates the distribution of the electronic components 300 within the through holes. In addition, the electronic component 300 is accommodated in the through hole, so that the height of the packaging structure can be effectively reduced, and further miniaturization of the packaging structure is promoted.
Of course, the electronic component 300 is fixedly disposed on the circuit layer 100, and the fixing manner can be various. In one embodiment, the electronic component 300 is fixed and disposed at a preset position of the pattern layer 100 by using an adhesive, and the method of fixing by using the adhesive is not only firm and reliable, but also convenient to operate, and can improve the production efficiency and reduce the cost. Further, for the electronic component 300 having only one pin, the electronic component 300 may be fixed by using a conductive adhesive, and at this time, the conductive adhesive may simultaneously function as a pin. The electronic component 300 having one or more pins may be connected to the circuit layer by an electrode led out from a side of the electronic component 300 away from the adhesive, or may be electrically connected to the circuit layer 100 by punching a hole in the adhesive layer and injecting a conductive material into the hole to form a conductive structure, so that the side of the electronic component 300 close to the adhesive is connected to the conductive structure.
Further, the target pattern 210 may be disposed at any position of the pattern layer 200, for example, at an end portion or a middle portion of the pattern layer 200; the shape of the target pattern 210 may be any shape such as a circle, an ellipse, or a rectangle; the number of the target patterns 210 may be one or more, and in any case, the target patterns 210 may be capable of positioning the electronic component 300. In one embodiment, only one of the electronic components 300 is provided, and at least one of the target patterns 210 is distributed on the outer circumference of the electronic component 300. In another embodiment, there are at least two electronic components 300, and the target pattern 210 is disposed between adjacent electronic components 300.
Further, the pattern layer 200 includes a first surface (not shown) far from the circuit layer 100 and a second surface (not shown) near to the circuit layer 100, and the pattern layer 200 is rectangular, and the target pattern 210 is disposed at a right angle to the first surface. The target pattern 210 is disposed at four right angles of the pattern layer 200, and the position of the electronic component 300 can be determined by a plurality of the target patterns 210, so that the positioning accuracy of the electronic component 300 can be further improved.
Further, the package body is a heat-cured package body, and the heat-cured package body can cover the electronic component 300, the pattern layer 200 and the circuit layer 100 in a surrounding manner in the heating and pressing process, and fill the cavity, so as to realize the embedded package of the electronic component 300. Further, the electronic component 300 may be an active device or a passive device, or a circuit board may be embedded in the package, and the number of the electronic components 300 may be one or more, and in one embodiment, the electronic components are chips.
In order to solve the technical problems, the application adopts another technical scheme that: a method for manufacturing a package structure is provided.
Referring to fig. 5, fig. 5 is a flow chart of an embodiment of a method for manufacturing a package structure according to the present application, the method includes the steps of:
s100, providing a substrate and fixing the circuit layer on the substrate.
In the step S100, the substrate is a non-metal substrate, and further the non-metal substrate is an organic substrate. The circuit layer is made of metal, conductive circuits are arranged on the circuit layer, and the electronic element is arranged at a preset position of the circuit layer so as to realize the corresponding function of the electronic element. The circuit layer is fixed on the substrate so that the position of the circuit layer is determined, and the position of the electronic component to be mounted is determined conveniently.
S200, a pattern layer is fixedly arranged on the circuit layer, and a target pattern for positioning at least one electronic element is arranged on the pattern layer.
In the step S200, the pattern layer is fixedly disposed on the circuit layer, and the position of the target pattern on the circuit layer is determined, for example, a coordinate system is established with a certain target pattern of the pattern layer as a coordinate origin, and the position coordinates of other target patterns are determined. By detecting the relative distance between the electronic element and the origin of coordinates, the position coordinates of the electronic element can be determined, and the position of the electronic element can be accurately determined.
S300, at least one electronic element is arranged on the circuit layer and is electrically connected with the circuit layer.
In the step S300, at least one electronic component is disposed on the circuit layer and electrically connected to the circuit layer, so that the electronic component in the package structure can be connected to an external circuit to realize the function of the electronic component.
S400, sleeving the packaging shell on the circuit layer and filling the packaging shell with the filling material to obtain the filled packaging shell.
In the step S400, the encapsulation material is injected into the space inside the encapsulation to fill, and then the filled encapsulation is obtained. The package housing may be any shape, and the shape of the package housing has a significant impact on the shape of the package structure, and the package housing is cubic in order to improve filling efficiency and facilitate subsequent use of the package structure. Of course, the shape of the package housing may also be selected according to the requirements of the actual production process.
S500, carrying out blind holes on the filled packaging shell to expose the target patterns, and carrying out lamination on the filling material according to the target patterns so as to enable the filling material and the packaging shell to embed and package the pattern layer and at least one electronic element, thereby obtaining a packaging structure.
In the step S500, the filling material injected is allowed to flow by heat or pressure during the pressing process, and fills the inside of the package case.
In this embodiment, the target pattern that this pattern layer was equipped with, can fix a position at least one this electronic component through this target pattern to confirm the pressure distribution on the clamp plate according to the distribution condition of electronic component in the packaging structure, make the pressfitting in-process can be tight with this packaging structure pressfitting, avoid damaging electronic component again, be favorable to improving product quality.
Further, referring to fig. 6, fig. 6 is a flowchart illustrating an embodiment of step S500 in fig. 5, and the method includes the steps of:
s510, blind holes are formed in the filled packaging shell, and the target pattern is exposed.
In this step S510, the target pattern is exposed by means of laser blind vias.
S520, determining the position of the at least one electronic component through the target pattern so as to determine the pressure distribution on the pressing plate in the pressing process.
In the step 520, the position of the at least one electronic component is determined by the target pattern, and different pressures are applied on the platen according to different substances (e.g., electronic components, filling materials, etc.) accommodated in the region of the filled package housing corresponding to the platen.
And S530, pressing the filled packaging shell through the pressing plate.
In the step 530, the pressing plate is pressed onto the filled package housing, and the filling material is in a state of flowing enough by applying pressure and increasing temperature, so as to fill the interior of the package housing, and simultaneously make the package structure more firm and reliable.
In one embodiment, the method of fixing a wiring layer on the substrate includes: a release layer is provided on the substrate, and the wiring layer is provided on the release layer. The stripping layer is used for realizing the separation of the packaging structure and the substrate, the stripping layer is made of metal, in one embodiment, the stripping layer is a copper foil layer with the thickness of 3 micrometers, and the copper foil with the smaller thickness is adopted, so that the preparation and the molding are convenient, and the production cost is reduced. Further, the release layer is connected to the circuit layer in various manners, such as press-fit connection and adhesive connection, and in one embodiment, the release layer is connected to the circuit layer by using an adhesive, so that the connection is firm and the operation is convenient. Furthermore, the stripping layer is connected with the circuit layer through the de-bonding adhesive, and the de-bonding adhesive can be contacted with water under the external action, so that the structure of the de-bonding adhesive is changed, and the stripping process of the packaging structure and the substrate is more convenient.
In another embodiment, after obtaining the package structure, the method further includes: and stripping the stripping layer from the circuit layer in the packaging structure to expose the circuit layer, so that the packaging structure is connected with an external circuit through the exposed conductive pattern of the circuit layer.
Further, referring to fig. 7, fig. 7 is a flowchart of an embodiment of step S300 in fig. 5, and the method includes the steps of:
and S310, punching the pattern layer to obtain a through hole penetrating through the pattern layer.
In the step S310, the punching method may be punching or laser punching, and in one embodiment, the laser punching is performed, so that the punching process is efficient, and the obtained through hole is accurate in position.
S320, at least one electronic component is arranged in the through hole, so that the at least one electronic component is electrically connected with the circuit layer.
In the step S320, the number of the through holes may be one or more, and the through holes may be any shape; the shape of each through hole is the same or different, and the number of the electronic components accommodated in each through hole is the same or different. In one embodiment, the through holes are rectangular holes, which not only facilitates the shaping of the through holes, but also facilitates the distribution of the electronic components in the through holes. In addition, the electronic element is accommodated in the through hole, so that the height of the packaging structure can be effectively reduced, and further the miniaturization of the packaging structure is promoted.
Further, referring to fig. 8, fig. 8 is a flowchart of an embodiment of step S320 in fig. 7, and the method includes the steps of:
s321, an adhesive layer is further arranged between at least one electronic element and the circuit layer in the through hole of the pattern layer.
In the step S321, the electronic component 300 is fixedly disposed on the circuit layer 100 in a plurality of fixing manners, and in this embodiment, the electronic component is accommodated in the through hole by using an adhesive and is fixedly disposed at a predetermined position of the pattern layer, and the fixing manner by using the adhesive is not only firm and reliable, but also convenient to operate, and can improve the production efficiency and reduce the cost.
S322, a conductive through hole filled with a conductive material is arranged at a preset position of the adhesive layer, and at least one electronic element is electrically connected with the circuit layer through the conductive through hole filled with the conductive material.
In the step S322, for the electronic component having only one pin, the electronic component may be fixed by using a conductive adhesive, and at this time, the conductive adhesive may simultaneously function as a pin. The electronic component with one or more pins can be connected with the circuit layer through an electrode led out from one side of the electronic component far away from the adhesive, or can be electrically connected with the circuit layer through a conductive through hole filled with a conductive material formed by punching the adhesive layer and injecting the conductive material into the hole, so that one side of the electronic component close to the adhesive is connected with the conductive through hole filled with the conductive material.
In another embodiment, the pattern layer is disposed between the circuit layer and at least one of the electronic components, and at least one of the electronic components is electrically connected to the circuit layer through the pattern layer. When the electronic component is embedded with only one pin, the pattern layer can be used as the pin, so that the electronic component and the circuit layer 100 are electrically connected through the pattern layer, the packaging structure can be effectively simplified, and the miniaturization of the packaging structure can be further realized.
Further, referring to fig. 9, fig. 9 is a flowchart of another embodiment of step S300 in fig. 5, and the method includes the steps of:
s31, punching the pattern layer to obtain at least two pattern layer through holes penetrating through the pattern layer.
In the step S31, when at least one of the electronic components needs to be provided with one or more pins, two pattern layer through holes penetrating the pattern layer are obtained by punching the pattern layer, and the electronic component is electrically connected with the circuit layer through the two pattern layer through holes.
And S32, filling a conductive material in the pattern layer to form a pattern layer conductive column.
In this step S32, the conductive material may be a metallic conductive material or a non-metallic conductive material, and in one embodiment, the conductive material is copper. In another embodiment, a pre-prepared pattern layer conductive post is inserted into the pattern layer through hole, and the pattern layer conductive post may be made of a metal material, such as copper, or a composite material, such as a ceramic post with a periphery coated with a conductive material, so long as the electrical connection between the electronic component and the circuit layer can be achieved.
S33, at least one electronic element is arranged on the pattern layer and is electrically connected with the circuit layer through the pattern layer conductive post.
In the step S33, one end of the pattern layer conductive column is connected with the electronic component, and the other end is connected with the circuit layer, so that at least one of the electronic components is electrically connected with the circuit layer
Further, the target pattern may be disposed at any position of the pattern layer, for example, at an end portion or a middle portion of the pattern layer; the shape of the target pattern can be any shape such as a circle, an ellipse or a rectangle; the number of the target patterns may be one or more, and in any case, the target patterns may be capable of positioning the electronic component. In one embodiment, when there is only one of the electronic components, at least one of the target patterns is distributed on the outer periphery of the electronic component. When the number of the electronic components is at least two, the target pattern is arranged between the adjacent electronic components.
Further, the pattern layer includes a first surface (not shown) far from the circuit layer and a second surface (not shown) near the circuit layer, and the pattern layer is rectangular, and the target pattern is disposed at a right angle to the first surface. The target patterns are arranged at four right angles of the pattern layer, and the positions of the electronic elements can be determined through a plurality of target patterns, so that the positioning accuracy of the electronic elements can be further improved.
Further, the package body is a heat-curing package body, and the heat-curing package body can cover the electronic element, the pattern layer and the circuit layer in a surrounding manner in the heating and pressing process, and fills the hollow cavity, so that the embedded package of the electronic element is realized. In addition, the material of the packaging shell is the same as that of the filling material, so that the filling material and the packaging shell are integrated in the pressing process, and the packaging structure is firmer and more reliable. Furthermore, the electronic component may be an active device or a passive device, or of course, the circuit board may be embedded in the package, and the number of the electronic components may be one or more, and in an embodiment, the electronic component is a chip.
In summary, the application discloses a packaging structure and a method for manufacturing the packaging structure, wherein the packaging structure comprises: a circuit layer; the pattern layer is fixedly arranged on the circuit layer; at least one electronic component disposed on the circuit layer and electrically connected to the circuit layer; the packaging body is arranged on the circuit layer and is used for embedding and packaging the pattern layer and at least one electronic element; the pattern layer is provided with a target pattern for positioning at least one electronic element. Through the mode, the quality of the packaging structure can be improved.
The foregoing description is only of embodiments of the present application, and is not intended to limit the scope of the application, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present application or directly or indirectly applied to other related technical fields are included in the scope of the present application.
Claims (11)
1. A method of manufacturing a package structure, the method comprising:
providing a substrate and fixing a circuit layer on the substrate;
a pattern layer is fixedly arranged on the circuit layer, and a target pattern for positioning at least one electronic element is arranged on the pattern layer;
disposing at least one of the electronic components on the wiring layer and electrically connecting with the wiring layer;
sleeving the packaging shell on the circuit layer and filling the packaging shell with a filling material to obtain a filled packaging shell;
blind holes are formed in the filled packaging shell, so that the target patterns are exposed;
determining the position of the at least one electronic component through the target pattern to determine pressure distribution on the pressing plate in the pressing process;
and pressing the filled packaging shell through the pressing plate, so that the filling material and the packaging shell embed and package the pattern layer and at least one electronic element, and a packaging structure is obtained.
2. The method of claim 1, wherein the method of securing a wiring layer to the substrate comprises:
and arranging a stripping layer on the substrate, and arranging the circuit layer on the stripping layer.
3. The method of claim 2, wherein the obtaining the package structure further comprises:
and stripping the stripping layer from the pattern layer in the packaging structure to expose the circuit layer.
4. The method of claim 2, wherein the release layer is connected to the circuit layer by means of a debonding glue or by means of a press fit.
5. The method of claim 1, wherein the disposing at least one of the electronic components on the wiring layer and electrically connecting with the wiring layer comprises:
punching the pattern layer to obtain a through hole penetrating through the pattern layer;
at least one of the electronic components is disposed in the via such that the at least one electronic component is electrically connected with the wiring layer.
6. The method of claim 5, wherein the disposing at least one of the electronic components in the via such that at least one of the electronic components is electrically connected to the wiring layer comprises:
an adhesive layer is arranged between at least one electronic element and the circuit layer in the through hole of the pattern layer;
and the preset position of the adhesive layer is provided with a conductive through hole filled with a conductive material, and at least one electronic element is electrically connected with the circuit layer through the conductive through hole filled with the conductive material.
7. The method of claim 1, wherein the disposing at least one of the electronic components on the wiring layer and electrically connecting with the wiring layer comprises:
punching the pattern layer to obtain at least two pattern layer through holes penetrating through the pattern layer;
filling conductive materials in the pattern layer to form pattern layer conductive columns;
and arranging at least one electronic element on the pattern layer and electrically connecting the electronic element with the circuit layer through the pattern layer conductive posts.
8. The method of any one of claims 1-7, wherein the target pattern is disposed at an end of the pattern layer.
9. The method of any one of claims 1-7, wherein the target pattern is disposed between adjacent ones of the electronic components.
10. The method of any of claims 1-7, wherein the pattern layer comprises a first surface distal to the wiring layer and a second surface proximal to the wiring layer, and the pattern layer is rectangular, the target pattern being disposed at a right angle to the first surface.
11. The method of any one of claims 1-7, wherein the filler material is a thermally cured filler material, and the package housing and the filler material are the same material; the electronic component is a chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811571228.0A CN111354687B (en) | 2018-12-21 | 2018-12-21 | Packaging structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811571228.0A CN111354687B (en) | 2018-12-21 | 2018-12-21 | Packaging structure and preparation method thereof |
Publications (2)
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| TW201121019A (en) * | 2009-12-01 | 2011-06-16 | Unimicron Technology Corp | Package structure having electronic components embedded therein |
| CN103906372A (en) * | 2012-12-27 | 2014-07-02 | 富葵精密组件(深圳)有限公司 | Circuit board having embedded components and manufacturing method thereof |
| CN103906370A (en) * | 2012-12-27 | 2014-07-02 | 宏启胜精密电子(秦皇岛)有限公司 | Chip packaging structure, circuit board having embedded component and manufacturing method thereof |
| CN105590914A (en) * | 2014-10-24 | 2016-05-18 | 宏启胜精密电子(秦皇岛)有限公司 | Electronic component packaging structure and manufacturing method |
| CN108922853A (en) * | 2018-07-09 | 2018-11-30 | 中国电子科技集团公司第五十八研究所 | A kind of three-dimensional structure production method based on Fan-out technique |
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| TW201121019A (en) * | 2009-12-01 | 2011-06-16 | Unimicron Technology Corp | Package structure having electronic components embedded therein |
| CN103906372A (en) * | 2012-12-27 | 2014-07-02 | 富葵精密组件(深圳)有限公司 | Circuit board having embedded components and manufacturing method thereof |
| CN103906370A (en) * | 2012-12-27 | 2014-07-02 | 宏启胜精密电子(秦皇岛)有限公司 | Chip packaging structure, circuit board having embedded component and manufacturing method thereof |
| CN105590914A (en) * | 2014-10-24 | 2016-05-18 | 宏启胜精密电子(秦皇岛)有限公司 | Electronic component packaging structure and manufacturing method |
| CN108922853A (en) * | 2018-07-09 | 2018-11-30 | 中国电子科技集团公司第五十八研究所 | A kind of three-dimensional structure production method based on Fan-out technique |
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