CN108922853A - A kind of three-dimensional structure production method based on Fan-out technique - Google Patents
A kind of three-dimensional structure production method based on Fan-out technique Download PDFInfo
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- CN108922853A CN108922853A CN201810745186.1A CN201810745186A CN108922853A CN 108922853 A CN108922853 A CN 108922853A CN 201810745186 A CN201810745186 A CN 201810745186A CN 108922853 A CN108922853 A CN 108922853A
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- 238000000034 method Methods 0.000 title claims abstract description 62
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 239000002184 metal Substances 0.000 claims abstract description 39
- 229910052751 metal Inorganic materials 0.000 claims abstract description 39
- 239000000853 adhesive Substances 0.000 claims abstract description 20
- 230000001070 adhesive effect Effects 0.000 claims abstract description 20
- 238000005516 engineering process Methods 0.000 claims abstract description 15
- 238000007517 polishing process Methods 0.000 claims abstract description 12
- 238000009713 electroplating Methods 0.000 claims abstract description 8
- 238000000227 grinding Methods 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 15
- 239000011241 protective layer Substances 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- 229910001316 Ag alloy Inorganic materials 0.000 claims description 3
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- 238000001746 injection moulding Methods 0.000 claims description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 3
- 229920000052 poly(p-xylylene) Polymers 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 229910000969 tin-silver-copper Inorganic materials 0.000 claims description 3
- 229910001074 Lay pewter Inorganic materials 0.000 claims description 2
- 239000004642 Polyimide Substances 0.000 claims description 2
- 229920001721 polyimide Polymers 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000004952 Polyamide Substances 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 208000020442 loss of weight Diseases 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06506—Wire or wire-like electrical connections between devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The present invention provides a kind of three-dimensional structure production methods based on Fan-out technique, belong to integrated antenna package technical field.It makes load label and perpendicular interconnection metal respectively on support plate disk first, makes groove in the region of load label, adhesives, and the chip on adhesives are filled into groove；Encapsulated layer is made on support plate disk, then the encapsulated layer is thinned using mechanical polishing process；Then wiring layer again and enclosure cavity are made；Using mechanical grinding and polishing process removal support plate disk and adhesives, until the exposed chip back side and perpendicular interconnection metal；Signal exit is made on the perpendicular interconnection metal of exposing using plant ball technique or electroplating technology；The product that above-mentioned steps are completed in cutting obtains individual devices unit, and individual devices unit is carried out three-dimensional stacked interconnection by three-dimensional stacked and underfill process, obtains three-dimensional structure.
Description
Technical field
The present invention relates to integrated antenna package technical field, in particular to a kind of three-dimensional structure based on Fan-out technique
Production method.
Background technique
As electronic product develops to the directions such as miniaturization, high-performance, highly reliable, level of integrated system is also increasingly improved.?
In this case, the characteristic size and the line width of interconnection line by further reducing integrated circuit propose high performance mode by material
Expect the limitation of physical characteristic and apparatus and process, traditional Moore's Law has been difficult to continue to develop.Based on fan-out-type wafer
Grade packaging technology（Fan-out technique）Technology it is three-dimensionally integrated as realize electronic system component high integration, miniaturization and
The effective way of low cost application, currently develops into the high main Advanced Packaging of integrated flexibility.It is typical brilliant
Grade is three-dimensionally integrated passes through chip and resin through-hole for circle（TMV）Fan-out package realizes that two dimension is integrated, then real by three-dimensional micro-group dress
Existing three-dimensional perpendicular interconnection, it has many advantages, such as that at low cost, with short production cycle, integration density is high, can be used for high performance system encapsulation.
Wherein Fan-out technology and TMV technology are to realize two three-dimensionally integrated key process technologies.
Fan-out technology is not necessarily to LTCC support plate, can be with loss of weight about 40% or more；And the integrated achievable micron of wafer scale
The accuracy of manufacture of grade scale, improves production efficiency, meets hyundai electronics change system and minimizes, is inexpensive, high integration urgent
It is essential and asks, the challenge that current tradition Fan-out technique encounters mainly has：Disk warpage, chip offset and chip protuberance.TMV
Technology is a key technology that Fan-out device realizes three dimensional signal interconnection, but the mode of production resin through-hole at present
The problems such as main to be punched by laser ablation, the roughness of through-hole surfaces and side wall is larger, easily causes filling metal empty.Due to
The presence of these problems significantly limits Fan-out technique in the application in the system-level fields such as integrated, three-dimensionally integrated.So being
Satisfaction current microelectronics system low cost, high density, miniaturization growth requirement, need to develop a kind of based on Fan-out work
The three-dimension packaging construction manufacturing method of skill.
Summary of the invention
It is existing to solve the purpose of the present invention is to provide a kind of three-dimensional structure production method based on Fan-out technique
Technique the problem of being easy to produce coarse through-hole pattern, metal filling cavity and disk warpage.
In order to solve the above technical problems, the present invention provides a kind of three-dimensional structure production method based on Fan-out technique, packet
Include following steps：
Step 1 makes load label and perpendicular interconnection metal respectively on support plate disk；
Step 2 makes groove in the region that load marks using etching technics；
Step 3 fills adhesives, and the chip on adhesives into groove；
Step 4 makes encapsulated layer on support plate disk, then the encapsulated layer is thinned using mechanical polishing process；
Step 5, the product surface after completing step 4 make wiring layer and enclosure cavity again；
Step 6 removes support plate disk and adhesives using mechanical grinding and polishing process, up to the exposed chip back side and vertically
Interconnect metal；
Step 7 makes signal exit using plant ball technique or electroplating technology on the perpendicular interconnection metal of exposing；
Step 8 cuts the product after completion step 7, obtains multiple individual devices units, passes through three-dimensional stacked and bottom
Individual devices unit is carried out three-dimensional stacked interconnection by fill process, obtains three-dimensional structure.
Optionally, the method for production perpendicular interconnection metal is specially in the step 1：Using electroplating technology in support plate disk
On grow perpendicular interconnection metal, or perpendicular interconnection metal ball/column and support plate disk are welded using ball/plant column technique is planted, or
Perpendicular interconnection metal lead wire is made on support plate disk using lead key closing process.
Optionally, chip is specially on adhesives：The active area of chip is completed to pacify upward, by adhesives
Dress makes protective layer on chip active area surface after being installed.
Optionally, encapsulated layer is made on support plate disk using wafer scale injection molding process.
Optionally, the thickness of the encapsulated layer is not less than the height of perpendicular interconnection metal.
Optionally, the encapsulated layer is thinned using mechanical polishing process in the step 4, up to exposing protective layer and vertically
Metal is interconnected, then removes the protective layer, the active area of exposed chip.
Optionally, the material of the protective layer includes polyimides, Parylene.
Optionally, wiring layer again and the method for enclosure cavity are made in the step 5 includes photoetching process.
Optionally, the material of the support plate disk includes silicon and glass, and the material of the signal exit includes that tin-lead is closed
Gold, sn-ag alloy and Tin Silver Copper Alloy.
The present invention also provides a kind of three produced according to the above-mentioned three-dimensional structure production method based on Fan-out technique
Tie up structure.
Beneficial effects of the present invention
（1）It is prefabricated vertical on support plate disk in the three-dimensional structure production method provided by the invention based on Fan-out technique
Metal is interconnected, then stacked interconnected is carried out by three-dimensional stacked and underfill process and realizes vertical interconnecting structure, solves tradition
TMV technique makes the problems such as coarse vertical interconnecting structure bring through-hole pattern, metal filling cavity, greatly improves encapsulation
Yield；
（2）Filling adhesives can be effectively improved chip offset problem in a groove, while support plate disk is in Fan-out processing procedure
Disk warpage issues caused by thermal expansion coefficient mismatch between chip and encapsulated layer can be effectively improved as structured substrate；
（3）Three-dimensional structure production method provided by the invention based on Fan-out technique can realize low cost, high density, small-sized
The more device three-dimensional Manufacturing resources changed.
Detailed description of the invention
Fig. 1 is the three-dimensional structure production method flow diagram based on Fan-out technique；
Fig. 2（a）~ Fig. 2（j）It is each step schematic diagram based on Fan-out technique production three-dimensional structure.
Specific embodiment
Below in conjunction with the drawings and specific embodiments to a kind of three-dimensional structure system based on Fan-out technique proposed by the present invention
It is described in further detail as method.According to following explanation and claims, advantages and features of the invention will be become apparent from.It needs
Illustrate, attached drawing is all made of very simplified form and using non-accurate ratio, only to convenient, lucidly auxiliary is said
The purpose of the bright embodiment of the present invention.
Embodiment one
The present invention provides a kind of three-dimensional structure production method based on Fan-out technique, flow diagram is as shown in Figure 1.Institute
The three-dimensional structure production method based on Fan-out technique is stated to include the following steps：
Step S11, load label and perpendicular interconnection metal are made respectively on support plate disk；
Step S12, groove is made in the region that load marks using etching technics；
Step S13, adhesives, and the chip on adhesives are filled into groove；
Step S14, encapsulated layer is made on support plate disk, then the encapsulated layer is thinned using mechanical polishing process；
Step S15, the product surface after completing step S14 makes wiring layer and enclosure cavity again；
Step S16, it using mechanical grinding and polishing process removal support plate disk and adhesives, up to the exposed chip back side and hangs down
Straight interconnection metal；
Step S17, signal exit is made on the perpendicular interconnection metal of exposing using plant ball technique or electroplating technology；
Step S18, cut to completing the product after step S17, obtain multiple individual devices units, by three-dimensional stacked and
Individual devices unit is carried out three-dimensional stacked interconnection by underfill process, obtains three-dimensional structure.
Specifically, Fig. 2（a）It is the schematic diagram of support plate disk 1, the material of the support plate disk 1 can be silicon and glass.?
Load label 2 and perpendicular interconnection metal 3 are made respectively on the support plate disk 1, such as Fig. 2（b）It is shown.Specifically, the load
Label 2 is used for chip positioning, can be made and be realized by photoetching process；The method for making the perpendicular interconnection metal 3 is specially：It adopts
Perpendicular interconnection metal is grown on support plate disk 1 with electroplating technology, or is used and planted ball/plant column technique for perpendicular interconnection metal
Ball/column and support plate disk 1 weld, or perpendicular interconnection metal lead wire is made on support plate disk 1 using lead key closing process.
Then, groove 4 is made in 2 region of load label of etching technics, such as Fig. 2（c）It is shown.The groove 4
For size depending on specific product, depth is no more than the thickness of the subsequent chip installed.
Such as Fig. 2（d）It is shown, adhesives 5 is filled into the groove 4, the adhesives 5 is generally glue material, closes
The materials such as gold plaque；Then, upward by the active area of chip 6, the chip 6 is mounted on by the adhesives using load technique
On 5, protective layer 7 is made in the surfaces of active regions of the chip 6 after being installed.The material of the protective layer 7 includes polyamides Asia
Amine, Parylene.
Then encapsulated layer 8 is made on the support plate disk 1 using wafer scale injection molding process, the encapsulated layer 8
Thickness is not less than the height of the perpendicular interconnection metal 3, such as Fig. 2（e）It is shown.The encapsulating is thinned using mechanical polishing process again
Layer 8 until exposing the protective layer 7 and the perpendicular interconnection metal 3, then removes the active area of 7 exposed chip of protective layer,
Such as Fig. 2（f）It is shown.
The surface of product after completing the procedure, by metallizing under photoetching process production again wiring layer 9 and salient point
Layer 10, realize chip 6 between and the signal interconnection between chip 6 and perpendicular interconnection metal 3, such as Fig. 2（g）.
The support plate disk 1 and the adhesives 5 are removed using mechanical grinding and polishing process, until exposed chip 6
The back side and perpendicular interconnection metal 3, such as Fig. 2（h）It is shown.Referring next to Fig. 2（i）, revealed using plant ball technique or electroplating technology
Signal exit 11 is made on perpendicular interconnection metal 3 out, realizes that chip signal is drawn.Specifically, the signal exit 11
Material include the materials such as leypewter, sn-ag alloy and Tin Silver Copper Alloy.
Finally the product for completing above-mentioned steps is cut using standard scribing process, obtains multiple individual devices lists
Individual devices unit is carried out three-dimensional stacked interconnection by three-dimensional stacked and underfill process by member, and obtained three-dimensional structure is such as
Fig. 2（j）It is shown.The three-dimensional transmission of device cell signal is realized by signal exit 11 and perpendicular interconnection metal 3.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (10)
1. a kind of three-dimensional structure production method based on Fan-out technique, which is characterized in that include the following steps：
Step 1 makes load label and perpendicular interconnection metal respectively on support plate disk；
Step 2 makes groove in the region that load marks using etching technics；
Step 3 fills adhesives, and the chip on adhesives into groove；
Step 4 makes encapsulated layer on support plate disk, then the encapsulated layer is thinned using mechanical polishing process；
Step 5, the product surface after completing step 4 make wiring layer and enclosure cavity again；
Step 6 removes support plate disk and adhesives using mechanical grinding and polishing process, up to the exposed chip back side and vertically
Interconnect metal；
Step 7 makes signal exit using plant ball technique or electroplating technology on the perpendicular interconnection metal of exposing；
Step 8 cuts the product after completion step 7, obtains multiple individual devices units, passes through three-dimensional stacked and bottom
Individual devices unit is carried out three-dimensional stacked interconnection by fill process, obtains three-dimensional structure.
2. as described in claim 1 based on the three-dimensional structure production method of Fan-out technique, which is characterized in that the step 1
It is middle production perpendicular interconnection metal method be specially：Perpendicular interconnection metal is grown on support plate disk using electroplating technology, or
Perpendicular interconnection metal ball/column and support plate disk are welded using ball/plant column technique is planted, or using lead key closing process in support plate circle
On piece makes perpendicular interconnection metal lead wire.
3. as described in claim 1 based on the three-dimensional structure production method of Fan-out technique, which is characterized in that in bonding material
Chip is specially on material：The active area of chip is completed to install upward, by adhesives, in chip active after being installed
Area surface makes protective layer.
4. as described in claim 1 based on the three-dimensional structure production method of Fan-out technique, which is characterized in that use wafer
Grade injection molding process makes encapsulated layer on support plate disk.
5. as claimed in claim 4 based on the three-dimensional structure production method of Fan-out technique, which is characterized in that the encapsulating
The thickness of layer is not less than the height of perpendicular interconnection metal.
6. as described in claim 1 based on the three-dimensional structure production method of Fan-out technique, which is characterized in that the step 4
It is middle that the encapsulated layer is thinned using mechanical polishing process, until exposing protective layer and perpendicular interconnection metal, then remove the protection
Layer, the active area of exposed chip.
7. as claimed in claim 3 based on the three-dimensional structure production method of Fan-out technique, which is characterized in that the protection
The material of layer includes polyimides, Parylene.
8. as described in claim 1 based on the three-dimensional structure production method of Fan-out technique, which is characterized in that the step 5
The method of wiring layer and enclosure cavity includes photoetching process again for middle production.
9. as described in claim 1 based on the three-dimensional structure production method of Fan-out technique, which is characterized in that the support plate
The material of disk includes silicon and glass, and the material of the signal exit includes leypewter, sn-ag alloy and Tin Silver Copper Alloy.
What 10. a kind of -9 any three-dimensional structure production methods based on Fan-out technique according to claim 1 were produced
Three-dimensional structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810745186.1A CN108922853A (en) | 2018-07-09 | 2018-07-09 | A kind of three-dimensional structure production method based on Fan-out technique |
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|---|---|---|---|
| CN201810745186.1A CN108922853A (en) | 2018-07-09 | 2018-07-09 | A kind of three-dimensional structure production method based on Fan-out technique |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111354687A (en) * | 2018-12-21 | 2020-06-30 | 深南电路股份有限公司 | Packaging structure and preparation method thereof |
| CN115621134A (en) * | 2022-12-16 | 2023-01-17 | 山东虹芯电子科技有限公司 | Wafer-level stacked multi-chip packaging method |
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| US20090008762A1 (en) * | 2007-07-02 | 2009-01-08 | Nepes Corporation | Ultra slim semiconductor package and method of fabricating the same |
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| CN111354687A (en) * | 2018-12-21 | 2020-06-30 | 深南电路股份有限公司 | Packaging structure and preparation method thereof |
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| CN115621134A (en) * | 2022-12-16 | 2023-01-17 | 山东虹芯电子科技有限公司 | Wafer-level stacked multi-chip packaging method |
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Application publication date: 20181130 |
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