CN106658964A - Circuit board and production method thereof - Google Patents
Circuit board and production method thereof Download PDFInfo
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- CN106658964A CN106658964A CN201510709855.6A CN201510709855A CN106658964A CN 106658964 A CN106658964 A CN 106658964A CN 201510709855 A CN201510709855 A CN 201510709855A CN 106658964 A CN106658964 A CN 106658964A
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/421—Blind plated via connections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
- H05K2201/09518—Deep blind vias, i.e. blind vias connecting the surface circuit to circuit layers deeper than the first buried circuit layer
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Abstract
The invention discloses a production method of a circuit board. The production method comprises steps that a capacitive substrate is provided, and the two opposite sides of the capacitive substrate are provided with a first copper foil layer and a second copper foil layer; the first copper foil layer and the second copper foil layer are etched to form a first capacitive line layer and a second capacitive line layer to acquire a capacitive unit; the upper part of the first capacitive line layer is sequentially provided with a first insulation layer, a resistive substrate, and a third copper foil layer, and the lower part of the second capacitive line layer is provided with a second insulation layer and a fourth copper foil layer to acquire the substrate provided with the capacitive unit in an embedded manner; blind holes are formed in the substrate, and are electroplated to form conductive columns, and the third copper foil layer and the fourth copper foil layer are conducted with the first capacitive line layer and the second capacitive line layer respectively by the conductive columns; the third copper foil layer, the fourth copper foil layer, and the resistive substrate are etched to form a first conductive line layer, a second conductive line layer, and a resistive line layer. The invention provides a circuit board produced by using the method.
Description
Technical field
The present invention relates to a kind of circuit board and preparation method thereof.
Background technology
In existing circuit board technology, the circuit board for being wherein embedded with resistance and electric capacity has been developed.Circuit board capacitance-resistance with embedded-type electric can be obtained by installing the passive component of such as resistance or electric capacity on the outer surface of circuit board or in the internal layer of circuit board.This circuit board with embedded capacitance resistive element, it is only necessary to assemble small number of capacitance resistance element, and be conducive to reducing the size of circuit board.
But, in such circuit board with embedded capacitor and resistive element, generally turned on using through hole, because the operation capacitor and resistance of chip can produce heat, via design is difficult thermal conductivity to motherboard, can affect the function of circuit board, and shortens the service life of circuit board.Also, the wiring density of circuit board is limited using through hole, is unfavorable for further reducing the size of element.
The content of the invention
In view of this, the invention provides the preparation method of a kind of good heat dissipation effect and the less circuit board of size and the circuit board.
A kind of preparation method of circuit board, it includes following operation：
A capacity substrate is provided, the opposite sides of capacity substrate has the first copper foil layer and the second copper foil layer；
Etch the first copper foil layer and the second copper foil layer forms the first capacitor lines layer and the second capacitor lines layer, obtain capacitor cell；
The first insulating barrier, resistance substrate and the 3rd copper foil layer are sequentially formed above the first capacitor lines layer, in the second capacitor lines layer the second insulating barrier formed below, the 4th copper foil layer, obtains being embedded with the substrate of capacitor cell；
Blind hole is formed on substrate, and blind hole is electroplated, form conductive pole, the 3rd copper foil layer and the 4th copper foil layer are respectively by conductive pole and the first capacitor lines layer and the conducting of the second capacitor lines layer；
The 3rd copper foil layer, the 4th copper foil layer and resistance substrate are etched, the first conductive circuit layer and the second wire circuit layer and resistive circuit layer is formed.
The present invention also provides the circuit board that a kind of use said method makes, it includes capacitor cell, the first insulating barrier and the second insulating barrier that are formed at capacitor cell opposite sides, the resistive circuit layer being formed above the first insulating barrier, the first conductive circuit layer for being formed at resistive circuit layer surface, the second conductive circuit layer for being formed at below the second insulating barrier, and the first conductive circuit layer and the second conductive circuit layer are turned on by conductive pole with capacitor cell.
Compared to prior art, the present invention forms the capacitor cell with capacitor lines layer using the upper and lower copper foil layer of etching capacitance material.Using the capacitor cell as substrate Jing pressing laminating insulating barriers, resistance substrate and copper foil layer, developed, etching forms resistive circuit layer and outer circuit layer.Blind hole is formed by laser boring and metal is electroplated to blind hole and form conductive pole to turn on electric capacity line layer and outer-layer circuit layer, obtain the circuit board with embedded capacitance and resistance.One side capacitor lines layer and outer circuit are respectively turned on using conductive pole, the thermal diffusivity of circuit board assemblies can be improved, do not thickened in the case that circuit board also do not increase the circuit board number of plies, reduce wiring density, reduce component size.In addition, being also avoided that the electroplates in hole filling perforation high aspect ratio causes Lou to fill in abnormal quality.
Description of the drawings
Fig. 1 is the generalized section of the capacity substrate that first embodiment of the invention is provided.
Fig. 2 is the generalized section that the first dry film and the second dry film are formed on the capacity substrate of Fig. 1.
Fig. 3 is the generalized section of the capacity substrate formation capacitor cell for etching Fig. 1.
Fig. 4 is the generalized section that substrate is formed on the basis of the capacitor cell of Fig. 3.
Fig. 5 is in the generalized section that blind hole is formed on the substrate of Fig. 4.
Fig. 6 is to electroplate blind hole in Figure 5 and form the generalized section of the 3rd dry film and the 4th dry film.
Fig. 7 is the generalized section for forming the first conductive line pattern, the second conductive circuit layer and resistive circuit layer in figure 6.
Fig. 8 is the generalized section for forming the 5th dry film and the 6th dry film in the figure 7.
Fig. 9 is the generalized section for forming the first conductive circuit layer and the 3rd conductive circuit layer in fig. 8.
Figure 10 is the generalized section for forming the first welding resisting layer, the second welding resisting layer, first surface process layer and second surface process layer in fig .9.
Figure 11 is to electroplate blind hole in Figure 5 and form the 7th dry film, the generalized section of the 8th dry film.
Figure 12 is the generalized section for forming the first conductive circuit layer, the second conductive circuit layer and the 3rd conductive circuit layer in fig. 11.
Figure 13 is the generalized section for forming the 9th dry film and the tenth dry film in fig. 12.
Figure 14 is the generalized section of the etched resistor substrate formation resistive circuit layer in Figure 13.
Main element symbol description
| Circuit board | 10 |
| Capacity substrate | 100 |
| Capacitor cell | 100a |
| Dielectric layer | 110 |
| First copper foil layer | 120 |
| Second copper foil layer | 122 |
| First capacitor lines layer | 1202 |
| Second capacitor lines layer | 1222 |
| First dry film | 130 |
| Second dry film | 132 |
| First insulating barrier | 140 |
| Second insulating barrier | 142 |
| Resistance substrate | 150 |
| Resistive circuit layer | 152 |
| 3rd copper foil layer | 160 |
| 4th copper foil layer | 162 |
| 3rd dry film | 170 |
| 4th dry film | 172 |
| 7th dry film | 174 |
| 8th dry film | 176 |
| First conductive pattern | 180 |
| First conductive circuit layer | 181 |
| Second conductive circuit layer | 182 |
| 3rd conductive circuit layer | 183 |
| 5th dry film | 190 |
| 6th dry film | 192 |
| 9th dry film | 194 |
| Tenth dry film | 196 |
| Substrate | 200 |
| First blind hole | 201 |
| Second blind hole | 202 |
| 3rd blind hole | 203 |
| 4th blind hole | 204 |
| First conductive pole | 201a |
| Second conductive pole | 202a |
| 3rd conductive pole | 203a |
| 4th conductive pole | 204a |
| First welding resisting layer | 210 |
| Second welding resisting layer | 212 |
| First surface process layer | 220 |
| Second surface process layer | 222 |
Following specific embodiment will further illustrate the present invention with reference to above-mentioned accompanying drawing.
Specific embodiment
First embodiment of the invention provides a kind of preparation method of circuit board 10, and it includes following operation:
First operation, refers to Fig. 1, there is provided a capacity substrate 100, and the capacity substrate 100 includes dielectric layer 110 and is respectively formed in first copper foil layer 120 and the second copper foil layer 122 of the opposite sides of the dielectric layer 110.
Second operation, refers to Fig. 2 and Fig. 3, etches capacity substrate 100, forms capacitor cell 100a.
As shown in Fig. 2 the concrete preparation method of capacitor cell 100a is：First, the first dry film 130 and the second dry film 132 are covered each by the first copper foil layer 120 and the second copper foil layer 122, the first dry film 130 and the second dry film 132 are patterned by exposure, development.Secondly, as shown in figure 3, being etched respectively to form the first capacitor lines layer 1202 and the second capacitor lines layer 1222 to the first copper foil layer 120 and the second copper foil layer 122.Finally, the first dry film 130 and the second dry film 132 are removed, obtains capacitor cell 100a.
3rd operation, refers to Fig. 4, presses respectively to form the first insulating barrier 140 and the second insulating barrier 142 in the both sides up and down of capacitor cell 100a, and forms resistance substrate 150 on the surface of the first insulating barrier 140.Afterwards, the 3rd copper foil layer 160 and the 4th copper foil layer 162 are formed respectively on the surface on the surface of resistance substrate 150 and the second insulating barrier 142, so as to obtain being embedded with the substrate 200 of capacitor cell 100a.
4th operation, refers to Fig. 5, and multiple blind holes are formed on the substrate 200, to expose the first capacitor lines layer 1202 and the second capacitor lines layer 1222.
Specifically, from the 3rd copper foil layer 160 and the 4th copper foil layer 162 open up to form a pair first blind holes 201 and the second blind hole 202 towards the first capacitor lines layer 1202 respectively by way of laser boring, while opening up to form a pair the 3rd blind holes 203 and the 4th blind hole 204 towards the second capacitor lines layer 1222 from the 3rd copper foil layer 160 and the 4th copper foil layer 162 respectively.First blind hole 201 and the second blind hole 202 are used to expose the first capacitor lines layer 1202, and the 3rd blind hole 203 and the 4th blind hole 204 are used to expose the second capacitor lines layer 1222.Specifically, the first blind hole 201 sequentially passes through the 3rd copper foil layer 160, the insulating barrier 140 of resistance substrate 150 and first from the top of substrate 200, with exposed portion the first capacitor lines layer 1202.Second blind hole 202 is oppositely arranged with the first blind hole 201, and sequentially passes through the 4th copper foil layer 162, the second insulating barrier 142, the second capacitor lines layer 1222 and dielectric layer 110 from the lower section of substrate 200, with exposed portion the first capacitor lines layer 1202.Similarly, the 3rd blind hole 203 sequentially passes through the 3rd copper foil layer 160, resistance substrate 150, the first insulating barrier 140, the first capacitor lines layer 1202 and dielectric layer 110 from the top of substrate 200, with exposed portion the second capacitor lines layer 1222.4th blind hole 204 is corresponding with the 3rd blind hole 203, and sequentially passes through the 4th copper foil layer 162 and the second insulating barrier 142 from the lower section of substrate 200, with exposed portion the second capacitor lines layer 1222.
In the present embodiment, as shown in Figure 5, the depth of the first blind hole 201 is less than the depth of the second blind hole 202, and the depth of the 3rd blind hole 203 is more than the depth of the 4th blind hole 204.
5th operation, refer to Fig. 6 and Fig. 7, the filling copper in first blind hole 201, the second blind hole 202, the 3rd blind hole 203 and the 4th blind hole 204, so as to form the first conductive pole 201a, the second conductive pole 202a, the 3rd conductive pole 203a and the 4th conductive pole 204a；And the 3rd copper foil layer 160 and the 4th copper foil layer 162 are etched, so as to form the first conductive pattern 180 and the second conductive circuit layer 182, while etched resistor substrate 150 is forming resistive circuit layer 152.
Specifically, first, refer to Fig. 6, by plating mode, respectively in first blind hole 201, second blind hole 202, copper is filled in 3rd blind hole 203 and the 4th blind hole 204, form the first conductive pole 201a, second conductive pole 202a, 3rd conductive pole 203a and the 4th conductive pole 204a, the first conductive pole 201a is set to turn on the first capacitor lines layer 1202 and the 3rd copper foil layer 160, the second conductive pole 202a is set to turn on the first capacitor lines layer 1202 and the 4th copper foil layer 162, the 3rd conductive pole 203a is set to turn on the second capacitor lines layer 1222 and the 3rd copper foil layer 160, the 4th conductive pole 204a is set to turn on the second capacitor lines layer 1222 and the 4th copper foil layer 162.Secondly, in surface the 3rd dry film 170 of formation and the 4th dry film 172 of the 3rd copper foil layer 160 and the 4th copper foil layer 162 the 3rd dry film 170 and the 4th dry film 172 are patterned by exposure, development respectively.Afterwards, as shown in fig. 7, the 3rd copper foil layer 160 of etching and the 4th copper foil layer 162, obtain the first conductive pattern 180 and the second conductive circuit layer 182.Meanwhile, etched resistor substrate 150 obtains resistive circuit layer 152, finally removes the 3rd dry film 170 and the 4th dry film 172.
6th operation, refers to Fig. 8 ~ 9, the first conductive pattern 180 is etched, to form the first conductive circuit layer 181 at least one the 3rd conductive circuit layer 183.
The forming method of the first conductive circuit layer 181 and the 3rd conductive circuit layer 183 specifically includes following operation：First, by dry film, exposure, development etc. the first conductive pattern 180 and the surface of the second conductive circuit layer 182 respectively on form the 5th dry film 190 and the 6th dry film 192.The 5th dry film 190 and the 6th dry film 192 are patterned by exposure, development.Afterwards, as shown in figure 9, etching the first conductive pattern 180, to form the first conductive circuit layer 181 and the 3rd conductive circuit layer 183.Finally, the 5th dry film 190 and the 6th dry film 192 are removed.
Now, first capacitor lines layer 1202 is turned on respectively by the first conductive pole 201a, the second conductive pole 202a with the first conductive circuit layer 181, the second conductive circuit layer 182, and the second capacitor lines layer 1222 is turned on respectively by the 3rd conductive pole 203a and the 4th conductive pole 204a with the first conductive circuit layer 181, the second conductive circuit layer 182.
7th operation, refer to Figure 10, the first welding resisting layer 210 is formed in the first conductive circuit layer 181 and the 3rd conductive circuit layer 183, on the surface of the second conductive circuit layer 182 the second welding resisting layer 212 is formed, on the first welding resisting layer 210 and the second welding resisting layer 212 at least one pair of welding resisting layer opening is respectively formed with.Part the first conductive circuit layer 181 and the 3rd conductive circuit layer 183 come out from the welding resisting layer opening of the first welding resisting layer 210；The second conductive circuit layer of part 182 comes out from the welding resisting layer opening of the second welding resisting layer 212.Afterwards, first surface process layer 220 is formed in part the first conductive circuit layer 181 and the 3rd conductive circuit layer 183 for coming out, second surface process layer 222 is formed in the second conductive circuit layer 182, first surface process layer 220 and second surface process layer 222 are used to weld external chip（It is not shown）.The first surface process layer 220 and second surface process layer 222 can be organic guarantor's welding machine or coat of metal.
By above operation, the circuit board 10 of the present invention is defined.
The preparation method of the circuit board 10 in the preparation method of the circuit board 10 of the second embodiment of the present invention and first embodiment is substantially the same, and its difference is following operation.
5th operation, refer to Figure 11 and Figure 12, copper is filled in first blind hole 201, the second blind hole 202, the 3rd blind hole 203 and the 4th blind hole 204, so as to form the first conductive pole 201a, the second conductive pole 202a, the 3rd conductive pole 203a and the 4th conductive pole 204a, the etching copper foil layer 160 of substrate the 3rd and the 4th copper foil layer 162, so as to form the first conductive circuit layer 181, the second conductive circuit layer 182 and the 3rd conductive circuit layer 183.
Refer to Figure 11, first, by plating mode, in first blind hole 201, second blind hole 202, copper is filled in 3rd blind hole 203 and the 4th blind hole 204 and forms the first conductive pole 201a, second conductive pole 202a, 3rd conductive pole 203a and the 4th conductive pole 204a, the first conductive pole 201a is set to turn on the first capacitor lines layer 1202 and the 3rd copper foil layer 160, the second conductive pole 202a is set to turn on the first capacitor lines layer 1202 and the 4th copper foil layer 162, the 3rd conductive pole 203a is set to turn on the second capacitor lines layer 1222 and the 3rd copper foil layer 160, the 4th conductive pole 204a is set to turn on the second capacitor lines layer 1222 and the 4th copper foil layer 162.Secondly, in the 3rd copper foil layer 160 and the surface of the 4th copper foil layer 162 the 7th dry film 174 of covering and the 8th dry film 176 the 7th dry film 174 and the 8th dry film 176 are patterned by exposure, development respectively.Afterwards, Figure 12, the 3rd copper foil layer 160 of etching and the 4th copper foil layer 162 are referred to, to obtain the first conductive circuit layer 181, the second conductive circuit layer 182 and the 3rd conductive circuit layer 183.Finally, the 7th dry film 174 and the 8th dry film 176 are removed.Wherein, first capacitor lines layer 1202 is turned on respectively by the first conductive pole 201a, the second conductive pole 202a with the first conductive circuit layer 181, the second conductive circuit layer 182, and the second capacitor lines layer 1222 is turned on respectively by the 3rd conductive pole 203a, the 4th conductive pole 204a with the first conductive circuit layer 181, the second conductive circuit layer 182.
6th operation, refers to Figure 13 and Figure 14, etched resistor substrate 150, so as to form resistive circuit layer 152.
Refer to Figure 13, the 9th dry film 194 is covered on resistance substrate 150, the first conductive circuit layer 181 and the surface of the 3rd conductive circuit layer 183, and the tenth dry film 196 is covered on the surface of the second conductive circuit layer 182, the 9th dry film 194 and the tenth dry film 196 are patterned by exposure, development.Afterwards, Figure 14, etched resistor substrate 150, to obtain resistive circuit layer 152 are referred to.Finally, the 9th dry film 194 and the tenth dry film 196 are removed.
Refer to Figure 10，The present invention also provides a kind of circuit board 10，The circuit board 10 includes by dielectric layer 110 and is formed at the dielectric layer capacitor cell 100a that the first capacitor lines layer 1202 and the second capacitor lines layer 1222 of both sides are constituted about 110、Fit in first insulating barrier 140 and the second insulating barrier 142 of the upper and lower both sides of capacitor cell 100a、It is formed at the resistive circuit layer 152 on the surface of the first insulating barrier 140、It is formed at first conductive circuit layer 181 on the surface of resistive circuit layer 152、It is formed at second conductive circuit layer 182 on the surface of the second insulating barrier 142、It is respectively formed in first welding resisting layer 210 and the second welding resisting layer 212 on the first conductive circuit layer 181 and the surface of the second conductive circuit layer 182、The first surface process layer 220 formed at least one pair of the anti-welding opening being opened in respectively on the first welding resisting layer 210 and the second welding resisting layer 212 and anti-welding opening and second surface process layer 222.
The circuit board 10 that the present invention is provided also includes the first conductive pole 201a, the second conductive pole 202a, the 3rd conductive pole 203a and the 4th conductive pole 204a.First capacitor lines layer 1202 is turned on respectively by the first conductive pole 201a, the second conductive pole 202a with the first conductive circuit layer 181, the second conductive circuit layer 182, and the second capacitor lines layer 1222 is turned on respectively by the 3rd conductive pole 203a, the 4th conductive pole 204a with the first conductive circuit layer 181, the second conductive circuit layer 182.
Specifically, the first conductive pole 201a is located at the top of capacitor cell 100a, and it is sequentially connected the first conductive circuit layer 181, through the insulating barrier 140 of resistive circuit layer 152 and first, and is connected to the first capacitor lines layer 1202.Second conductive pole 202a is located at the lower section of capacitor cell 100a, and it is sequentially connected the second conductive circuit layer 182, through the second insulating barrier 142, the second capacitor lines layer 1222 and dielectric layer 110, and is connected to the first capacitor lines layer 1202.3rd conductive pole 203a is located at the top of capacitor cell 100a, is sequentially connected the first conductive circuit layer 181, through the insulating barrier 140 of resistive circuit layer 152 and first, the first capacitor lines layer 1202 and dielectric layer 110, and is connected to the second capacitor lines layer 1222.4th conductive pole 204a is located at the lower section of capacitor cell 100a, and it is sequentially connected the second conductive circuit layer 182, through the second insulating barrier 142, and is connected to the second capacitor lines layer 1222.
The circuit board 10 of the present invention also includes at least one the 3rd conductive circuit layer 183, and it is used to be connected with other electronic components.In the present embodiment, the 3rd conductive circuit layer 183 is connected by resistive circuit layer 152 with the first conductive circuit layer 181.
Compared to prior art, the present invention forms the capacitor cell with capacitor lines layer using the upper and lower copper foil layer of etching capacitance material.Using the capacitor cell as substrate Jing pressing laminating insulating barriers, resistance substrate and copper foil layer, developed, etching forms resistive circuit layer and outer circuit layer.Blind hole is formed by laser boring and metal is electroplated to blind hole and form conductive pole to turn on electric capacity line layer and outer-layer circuit layer, obtain the circuit board with embedded capacitance and resistance.One side capacitor lines layer and outer circuit are respectively turned on using conductive pole, the thermal diffusivity of circuit board assemblies can be improved, do not thickened in the case that circuit board also do not increase the circuit board number of plies, reduce wiring density, reduce component size.In addition, being also avoided that the electroplates in hole filling perforation high aspect ratio causes Lou to fill in abnormal quality.
Claims (13)
1. a kind of circuit board manufacturing method, it is characterised in that including following operation：
A capacity substrate is provided, the opposite sides of the capacity substrate has the first copper foil layer and the second copper foil layer；
Etch first copper foil layer and second copper foil layer forms the first capacitor lines layer and the second capacitor lines layer, obtain capacitor cell；
The first insulating barrier, resistance substrate and the 3rd copper foil layer are sequentially formed above the first capacitor lines layer, in the second capacitor lines layer the second insulating barrier formed below, the 4th copper foil layer, obtains being embedded with the substrate of capacitor cell；
Blind hole being formed on the substrate, and the blind hole being electroplated, form conductive pole, the 3rd copper foil layer and the 4th copper foil layer are turned on respectively by the conductive pole with the first capacitor lines layer and the second capacitor lines layer；
The 3rd copper foil layer, the 4th copper foil layer and the resistance substrate are etched, the first conductive circuit layer and the second wire circuit layer and resistive circuit layer is formed.
2. circuit board manufacturing method as claimed in claim 1, it is characterized in that, the blind hole includes the first blind hole, the second blind hole, the 3rd blind hole, the 4th blind hole, first blind hole is from surface, the 3rd copper foil layer, the resistance substrate and first insulating barrier are sequentially passed through, exposes the first capacitor lines layer；Second blind hole sequentially passes through the 4th copper foil layer, second insulating barrier, the second capacitor lines layer and the dielectric layer from below the substrate, to expose the first capacitor lines layer；3rd blind hole sequentially passes through the 3rd copper foil layer, the resistance substrate and first insulating barrier, the first capacitor lines layer and the dielectric layer from above the substrate, to expose the second capacitor lines layer；4th blind hole sequentially passes through the 4th copper foil layer and second insulating barrier from below the substrate, to expose the second capacitor lines layer.
3. circuit board manufacturing method as claimed in claim 2, it is characterized in that, first blind hole, second blind hole, copper is filled by plating mode in 3rd blind hole and the 4th blind hole, the first conductive pole is formed respectively, second conductive pole, 3rd conductive pole and the 4th conductive pole, first conductive pole is set to turn on the first capacitor lines layer and the 3rd copper foil layer, second conductive pole is set to turn on the first capacitor lines layer and the 4th copper foil layer, the 3rd conductive pole is set to turn on the second capacitor lines layer and the 3rd copper foil layer, make the 4th conductive pole turn on the second capacitor lines layer to turn on the 4th copper foil layer.
4. circuit board manufacturing method as claimed in claim 1, it is characterised in that etching the 3rd copper foil layer is also formed with least one the 3rd conductive circuit layer, and the 3rd conductive circuit layer is connected by the resistive circuit layer with first conductive circuit layer.
5. circuit board manufacturing method as claimed in claim 4, it is characterized in that, the 3rd copper foil layer and the resistance substrate are etched, the first conducting wire pattern and resistive circuit layer is formed, first conductive line pattern is etched and is formed first conductive circuit layer and the 3rd conductive circuit layer.
6. circuit board manufacturing method as claimed in claim 4, it is characterised in that etch the 3rd copper foil layer first and form first conductive circuit layer and the 3rd conductive circuit layer, secondly the described resistance substrate of etching, forms resistive circuit layer.
7. circuit board manufacturing method as claimed in claim 1, it is characterized in that, it is additionally included in first conductive circuit layer and forms the first welding resisting layer, the second welding resisting layer is formed in second conductive circuit layer, at least one pair of welding resisting layer opening is respectively formed in first welding resisting layer and the second welding resisting layer, makes first conductive circuit layer and the second conductive circuit layer be exposed to the welding resisting layer opening.
8. a kind of circuit board, it includes capacitor cell, be formed at the first insulating barrier of the capacitor cell opposite sides and the second insulating barrier, be formed above first insulating barrier resistive circuit layer, be formed at the first conductive circuit layer of the resistive circuit layer surface, the second conductive circuit layer being formed at below second insulating barrier, it is characterised in that：First conductive circuit layer and second conductive circuit layer are turned on by conductive pole with the capacitor cell.
9. circuit board as claimed in claim 8, it is characterised in that the capacitor cell includes a dielectric layer and is formed at the first capacitor lines layer and the second capacitor lines layer of the upper and lower both sides of the dielectric layer.
10. circuit board as claimed in claim 9, it is characterised in that the conductive pole includes the first conductive pole, the second conductive pole, the 3rd conductive pole and the 4th conductive pole；The first capacitor lines layer is turned on respectively by first conductive pole, second conductive pole with first conducting wire, second conducting wire, and the second capacitor lines layer is turned on respectively by the 3rd conductive pole, the 4th conductive pole with first conducting wire, second conducting wire.
11. circuit boards as claimed in claim 10, characterized in that, first conductive pole is located at capacitor cell top, it is sequentially connected first conductive circuit layer, through the resistive circuit layer and first insulating barrier, the first capacitor lines layer is connected to；Second conductive pole is located at capacitor cell lower section, and it is sequentially connected second conductive circuit layer, through second insulating barrier, the second capacitor lines layer and dielectric layer, is connected to the first capacitor lines layer；3rd conductive pole is located at capacitor cell top, and it is sequentially connected first conductive circuit layer, through the resistive circuit layer, first insulating barrier, the first capacitor lines layer and the dielectric layer, is connected to the second capacitor lines layer；4th conductive pole is located at the lower section of the capacitor cell, and it is sequentially connected second conductive circuit layer, through second insulating barrier, is connected to the second capacitor lines layer.
12. circuit boards as claimed in claim 8, it is characterised in that the circuit board also includes at least one the 3rd conductive circuit layer, the 3rd conductive circuit layer is connected by the resistive circuit layer with first conductive circuit layer.
13. circuit boards as claimed in claim 8, it is characterized in that, the circuit board also includes the first welding resisting layer, second welding resisting layer, first surface process layer and second surface process layer, first welding resisting layer is formed at first conductive circuit layer and the 3rd conducting wire layer surface, second welding resisting layer is formed at the second conducting wire layer surface, first welding resisting layer and the second welding resisting layer include an at least welding resisting layer opening, first conductive circuit layer, 3rd conductive circuit layer and the second conductive circuit layer are exposed to the welding resisting layer opening, the first surface process layer is formed in the first conductive circuit layer and the 3rd conductive circuit layer exposed from the welding resisting layer opening, the second surface process layer is formed in the second conductive circuit layer exposed from the welding resisting layer opening.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510709855.6A CN106658964A (en) | 2015-10-28 | 2015-10-28 | Circuit board and production method thereof |
| TW104138649A TWI599281B (en) | 2015-10-28 | 2015-11-20 | Package carrier and method for manufacturing same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510709855.6A CN106658964A (en) | 2015-10-28 | 2015-10-28 | Circuit board and production method thereof |
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| CN106658964A true CN106658964A (en) | 2017-05-10 |
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| CN201510709855.6A Pending CN106658964A (en) | 2015-10-28 | 2015-10-28 | Circuit board and production method thereof |
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| TW (1) | TWI599281B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107683032A (en) * | 2017-08-31 | 2018-02-09 | 江苏普诺威电子股份有限公司 | Two-sided etching burying capacitance circuit board manufacture craft |
| CN113133202A (en) * | 2020-01-15 | 2021-07-16 | 碁鼎科技秦皇岛有限公司 | Embedded capacitor circuit board and manufacturing method thereof |
| CN114286540A (en) * | 2020-09-28 | 2022-04-05 | 宏启胜精密电子(秦皇岛)有限公司 | Circuit board manufacturing method and circuit board |
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Also Published As
| Publication number | Publication date |
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| TW201720250A (en) | 2017-06-01 |
| TWI599281B (en) | 2017-09-11 |
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Application publication date: 20170510 |