CN104254191A - Coreless layer packaging substrate and manufacturing method thereof - Google Patents
Coreless layer packaging substrate and manufacturing method thereof Download PDFInfo
- Publication number
- CN104254191A CN104254191A CN201310265770.4A CN201310265770A CN104254191A CN 104254191 A CN104254191 A CN 104254191A CN 201310265770 A CN201310265770 A CN 201310265770A CN 104254191 A CN104254191 A CN 104254191A
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- layer
- conducting wire
- copper foil
- external conducting
- hole
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- 239000000758 substrate Substances 0.000 title claims abstract description 97
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000004806 packaging method and process Methods 0.000 title abstract description 10
- 239000010410 layer Substances 0.000 claims description 167
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 94
- 239000011889 copper foil Substances 0.000 claims description 84
- 238000000034 method Methods 0.000 claims description 21
- 238000003466 welding Methods 0.000 claims description 19
- 239000011241 protective layer Substances 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims 1
- 229910052802 copper Inorganic materials 0.000 description 10
- 239000010949 copper Substances 0.000 description 10
- 238000009713 electroplating Methods 0.000 description 5
- 238000002360 preparation method Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 239000000654 additive Substances 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 2
- 238000003825 pressing Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
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- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
The invention relates to a coreless layer packaging substrate. The coreless layer packaging substrate comprises a dielectric layer, an inner layer conductive circuit graph, a first outer layer conductive circuit graph and a second outer layer conductive circuit graph, wherein the inner layer conductive circuit graph is buried in the dielectric layer; the first outer layer conductive circuit graph and the second outer layer conductive circuit graph are respectively positioned on two opposite sides of the dielectric layer; and the inner layer conductive circuit graph, the first outer layer conductive circuit graph and the second outer layer conductive circuit graph are electrically connected to one another via conductive through holes in the dielectric layer. The invention also relates to a manufacturing method of the coreless layer packaging substrate.
Description
Technical field
The present invention relates to circuit board making technical field, particularly relate to one and there is centreless layer package substrate and preparation method thereof.
Background technology
Along with electronic product is toward development that is miniaturized, high speed direction, for carrying the base plate for packaging of chip also from one side base plate for packaging (namely one side has the substrate of conducting wire), double-sided packaging substrate (i.e. the two-sided substrate with conducting wire) toward layer multilayer packaging substrate (namely there is the substrate of multilayer conductive circuit) future development.The layer multilayer packaging substrate with sandwich layer (core) has more wiring area, higher interconnect density, is thus widely used.But, just because of the existence of sandwich layer, make the base plate for packaging thickness with sandwich layer thicker.
Summary of the invention
In view of this, be necessary to provide a kind of centreless layer package substrate solved the problem and preparation method thereof, to reduce the thickness of centreless layer package substrate.
A kind of centreless layer package substrate, it comprises dielectric layer, inner layer conductive line pattern, the first external conducting wire figure and the second external conducting wire figure.Described inner layer conductive line pattern is embedded in described dielectric layer.Described first external conducting wire figure and the second external conducting wire figure lay respectively at the relative both sides of described dielectric layer.Described inner layer conductive line pattern, the first external conducting wire figure and the second external conducting wire figure are electrical connected by the conductive through hole in described dielectric layer.
A kind of manufacture method of centreless layer package substrate, it comprises: provide a loading plate, described loading plate comprises relative first surface and second surface, superimposed first Copper Foil successively on the first surface of described loading plate, first film and second Copper Foil, another first Copper Foil superimposed successively on described second surface, another first film and another the second Copper Foil, and the second Copper Foil on first surface described in one step press, the second Copper Foil on described loading plate and described second surface, to obtain first solderless substrate, described first solderless substrate comprises a processing district and the first garbage area around described processing district, each second Copper Foil is all made and forms inner layer conductive line pattern, superimposed second film and the 3rd Copper Foil successively on each described inner layer conductive line pattern, and described second film on the upside of the first solderless substrate described in one step press and the second film on the downside of the 3rd Copper Foil, described first solderless substrate and the first solderless substrate and the 3rd Copper Foil, obtain the second solderless substrate, in described second solderless substrate, be positioned at the first film on the upside of described first surface and the second film forms a dielectric layer jointly, the first film on the downside of described first surface and the second film form a dielectric layer jointly, remove described first garbage area, and remove described loading plate, obtain two circuit substrates be separated from each other, each circuit substrate all has product zone and the second garbage area around described product zone, each circuit substrate includes a described dielectric layer, described first Copper Foil, described 3rd Copper Foil and a described inner layer conductive line pattern, described first Copper Foil and the 3rd Copper Foil lay respectively at the relative both sides of described dielectric layer, and described inner layer conductive line pattern is embedded in described dielectric layer, in the product zone of described circuit substrate, form multiple through hole, each described through hole all runs through described circuit substrate, and each through hole is all made conductive through hole, and described conductive through hole is electrically connected described first Copper Foil, inner layer conductive line pattern and the 3rd Copper Foil, on the surface of described first Copper Foil, the first external conducting wire figure is formed at described dielectric layer, on the surface of described 3rd Copper Foil, form the second external conducting wire figure at described dielectric layer, described first external conducting wire figure, the second external conducting wire figure and inner layer conductive line pattern are electrical connected by described conductive through hole, and remove described second garbage area, obtain centreless layer package substrate.
In centreless layer package substrate that the technical program provides and preparation method thereof, described inner layer conductive line pattern is embedded in described dielectric layer, described first external conducting wire figure and the second external conducting wire figure lay respectively at the relative both sides of described dielectric layer, described inner layer conductive line pattern, the first external conducting wire figure and the second external conducting wire figure are electrical connected by the conductive through hole in described dielectric layer, compared to existing technology, do not have sandwich layer in centreless layer package substrate in the technical program, thickness reduces greatly.
Accompanying drawing explanation
Fig. 1 is the cutaway view with the first solderless substrate of loading plate that the technical program embodiment provides.
Fig. 2 is the generalized section form multiple first tooling hole in the first garbage area of the first solderless substrate shown in Fig. 1 after.
The second Copper Foil in the first solderless substrate in Fig. 2 is made the generalized section after inner layer conductive line pattern by Fig. 3.
Fig. 4 is superimposed second film and the 3rd Copper Foil the generalized section of the second solderless substrate formed after pressing successively on each inner layer conductive line pattern in figure 3.
Fig. 5 is the generalized section after the described loading plate removed in Fig. 4 obtains two circuit substrates be separated from each other.
Fig. 6 forms multiple second tooling hole in the second garbage area of the circuit substrate shown in Fig. 5, forms the generalized section after multiple through hole in the product zone of described circuit substrate.
Each through hole in Fig. 6 is all made the generalized section after conductive through hole by Fig. 7.
The first Copper Foil in Fig. 7 and the 3rd Copper Foil are made the generalized section after the first external conducting wire figure and the second external conducting wire figure by Fig. 8 respectively.
Fig. 9 is the generalized section after forming welding resisting layer on the first external conducting wire figure in fig. 8, on the second external conducting wire figure and in each conductive through hole.
Golden finger end in fig .9 forms first protective layer to Figure 10, and each weld pad is all formed the generalized section after second protective layer.
Figure 11 is the second garbage area of removing in Figure 10 thus obtains the generalized section of circuit board.
Main element symbol description
| Loading plate | 10 |
| First surface | 101 |
| Second surface | 102 |
| First Copper Foil | 11 |
| First film | 13 |
| Second Copper Foil | 15 |
| First solderless substrate | 20 |
| Processing district | 21 |
| First garbage area | 23 |
| Product zone | 211 |
| Second garbage area | 213 |
| First tooling hole | 25 |
| Inner layer conductive line pattern | 30 |
| Second film | 16 |
| 3rd Copper Foil | 17 |
| Second solderless substrate | 40 |
| Dielectric layer | 50 |
| Circuit substrate | 60 |
| Second tooling hole | 215 |
| Conductive through hole | 218 |
| First external conducting wire figure | 111 |
| Second external conducting wire figure | 117 |
| Welding resisting layer | 70 |
| First opening | 71 |
| Second opening | 73 |
| Golden finger end | 113 |
| Weld pad | 118 |
| First protective layer | 114 |
| Second protective layer | 119 |
| Centreless layer package substrate | 100 |
Following embodiment will further illustrate the present invention in conjunction with above-mentioned accompanying drawing.
Embodiment
Below in conjunction with drawings and Examples, the manufacture method of the centreless layer package substrate that the technical program provides and the centreless layer package substrate obtained by this manufacture method are described in further detail.
The technical program embodiment provides centreless layer package substrate to comprise the following steps:
The first step, refers to Fig. 1, provides a loading plate 10.Described loading plate 10 comprises relative first surface 101 and second surface 102.
Superimposed first Copper Foil 11, first film 13 and second Copper Foil 15 successively on the first surface 101 of described loading plate 10, superimposed first Copper Foil 11, first film 13 and second Copper Foil 15 successively on second surface 102.In the present embodiment, the thickness of described first Copper Foil 11 is less than the thickness of described second Copper Foil 15.
Then, the second Copper Foil 15 on first surface 101 described in one step press and the second Copper Foil 15 and the first film 13 on the first film 13, loading plate 10 and described second surface 102, to obtain first solderless substrate 20.Described first solderless substrate 20 comprises a processing district 21 and the first garbage area 23 around described processing district 21.
Second step, refers to Fig. 2, forms multiple first tooling hole 25 by digital control hole drilling technique in the first garbage area 23 of described first solderless substrate 20.Each first tooling hole 25 all runs through described first solderless substrate 20.
3rd step, refers to Fig. 3, the layers of copper that each second Copper Foil 15 corresponds to described processing district 21 is all made and forms inner layer conductive line pattern 30, and removes the layers of copper that each second Copper Foil 15 corresponds to described first garbage area 23.In present embodiment, by image transfer technique and etch process, the layers of copper that each second Copper Foil 15 corresponds to described processing district 21 is all made formation inner layer conductive line pattern 30, and while the layers of copper that each second Copper Foil 15 is corresponded to described processing district 21 is etched to inner layer conductive line pattern 30, remove by etch process the layers of copper that each second Copper Foil 15 corresponds to described first garbage area 23.
4th step, refers to Fig. 4, superimposed second film 16 and the 3rd Copper Foil 17 successively on each inner layer conductive line pattern 30.In the present embodiment, the thickness of described 3rd Copper Foil 17 is less than the thickness of described second Copper Foil 15, and the thickness of described 3rd Copper Foil 17 equals the thickness of described first Copper Foil 11.
Then, the second film 16 on the downside of described second film 16 on the upside of one step press first solderless substrate 20 and the 3rd Copper Foil 17, described first solderless substrate 20 and the first solderless substrate 20 and the 3rd Copper Foil 17, make described second film 16 fill up described first tooling hole 25, obtain the second solderless substrate 40.
In described second solderless substrate 40, be positioned at first film 13 on the upside of described first surface 101 and a second film 16 formation dielectric layer 50 jointly; Be positioned at first film 13 on the downside of described first surface 101 and second film 16 also forms a dielectric layer 50 jointly.Be positioned at the relative both sides that the first Copper Foil 11 on the upside of described first surface 101 and the 3rd Copper Foil 17 lay respectively at the dielectric layer 50 on the upside of described first surface 101.The inner layer conductive line pattern 30 be arranged on the upside of described first surface 101 is embedded in the dielectric layer 50 be positioned on the upside of described first surface 101.Be positioned at the relative both sides that the first Copper Foil 11 on the downside of described first surface 101 and the 3rd Copper Foil 17 lay respectively at the dielectric layer 50 be positioned on the downside of described first surface 101.The inner layer conductive line pattern 30 be arranged on the downside of described first surface 101 is embedded in the dielectric layer 50 be positioned on the downside of described first surface 101.
5th step, refers to Fig. 5, removes described first garbage area 23, and removes described loading plate 10, obtains two circuit substrates 60 be separated from each other.Each circuit substrate 60 corresponds to described processing district 21, and it all has product zone 211 and the second garbage area 213 around described product zone 211.That is, described product zone 211 and the second garbage area 213 form described processing district 21 jointly.Each circuit substrate 60 includes a dielectric layer 50, first Copper Foil, 11, the 3rd Copper Foil 17 and an inner layer conductive line pattern 30.Described first Copper Foil 11 and the 3rd Copper Foil 17 lay respectively at the relative both sides of described dielectric layer 50.Described inner layer conductive line pattern 30 is embedded in described dielectric layer 50.
6th step, refers to Fig. 6, forms multiple second tooling hole 215 by digital control hole drilling technique in the second garbage area 213 of described circuit substrate 60, forms multiple through hole 217 in the product zone 211 of described circuit substrate 60.Each second tooling hole 215 and each through hole 217 all run through described circuit substrate 60.
7th step, refers to Fig. 7, and each through hole 217 is all made conductive through hole 218.Described conductive through hole 218 is electrically connected described firstth Copper Foil 11, inner layer conductive line pattern 30 and the 3rd Copper Foil 17.In present embodiment, plate copper electroplating layer by electroplating technology by the hole wall of each through hole 217, the first Copper Foil 11 and the 3rd Copper Foil 17, thus each through hole 217 is all made conductive through hole 218.So, described conductive through hole 218 is the conductive hole of hollow.
In other embodiments, by plating process for filling hole, each through hole 217 all can also be filled up, thus each through hole 217 is all made conductive through hole.In such cases, the conductive through hole formed is solid conductive hole.
Be understandable that, when each through hole 217 is all made conductive through hole 218, without the need to also plating copper electroplating layer on whole first Copper Foil 11 and whole 3rd Copper Foil 17, as long as described conductive through hole 218 is electrically connected described first Copper Foil 11, inner layer conductive line pattern 30 and the 3rd Copper Foil 17.
8th step, refers to Fig. 8, forms the first external conducting wire figure 111 at described dielectric layer 50 on the surface of described first Copper Foil 11, forms the second external conducting wire figure 117 at described dielectric layer on the surface of described 3rd Copper Foil 17.Described first external conducting wire figure 111, second external conducting wire figure 117 and inner layer conductive line pattern 30 are electrical connected by described conductive through hole 218.Distance between described first external conducting wire figure 111 and inner layer conductive line pattern 30 is D1.Distance between described second external conducting wire figure 117 and inner layer conductive line pattern 30 is D2.D1/D2 is between 0.8 to 1.2.Wherein, D1 refers to the distance at center to the center of the thickness of inner layer conductive line pattern 30 of the thickness of described first external conducting wire figure 111; D2 refers to the distance at center to the center of the thickness of inner layer conductive line pattern 30 of the thickness of described second external conducting wire figure 117.Preferably, in present embodiment, adopt improve semi-additive process (Modified Semi-Additive Process) by the first Copper Foil 11 and on copper electroplating layer and the 3rd Copper Foil 17 and on copper electroplating layer make the first external conducting wire figure 111 and the second external conducting wire figure 117 respectively.
9th step, refers to Fig. 9, on described first external conducting wire figure 111, forms one deck welding resisting layer 70 on the second external conducting wire figure 117 and in each described conductive through hole 218.Described welding resisting layer 70 is covered in described first external conducting wire figure 111 and the second external conducting wire figure 117, and is filled in described conductive through hole 218.And first opening 71 and multiple second opening 73 is formed in described welding resisting layer 70.The described first external conducting wire figure 111 of part exposes from described multiple second opening 73, to define multiple weld pad 118.The described second external conducting wire figure 117 of part exposes from described first opening 71, to define at least one golden finger end 113.Welding resisting layer 70 can adopt the mode of solder-mask printing ink to be formed.
In other embodiments, when each through hole 217 all being filled up by plating process for filling hole, then anti-described first external conducting wire figure 111 can form one deck welding resisting layer, described second external conducting wire figure 117 can form other one deck welding resisting layer.
Tenth step, refers to Figure 10, described golden finger end 113 forms first protective layer 114, each described weld pad 118 is all formed second protective layer 119.Described first protective layer 114 can be nickel-gold layer.Second protective layer 119 can weld film (OSP) for organic guarantor, also can be NiPdAu layer.
11 step, sees also Figure 10 and Figure 11, removes described second garbage area 213, thus obtains centreless layer package substrate 100.
After this, soldered ball can also be formed on weld pad 118, so that be connected with other circuit boards.
The technical program also provides a kind of centreless layer package substrate 100, and described centreless layer package substrate 100 comprises dielectric layer 50, be embedded in inner layer conductive line pattern 30, first external conducting wire figure 111 in described dielectric layer 50 and the second external conducting wire figure 117.
Described first external conducting wire figure 111 and the second external conducting wire figure 117 lay respectively at the relative both sides of described dielectric layer 50, and described first external conducting wire figure 111, second external conducting wire figure 117 and inner layer conductive line pattern 30 are electrical connected by the conductive through hole 218 be formed in described dielectric layer 50.
Described centreless layer package substrate 100 also comprises the welding resisting layer 70 be formed on described first external conducting wire figure 111, on the second external conducting wire figure 117 and in each described conductive through hole 218.
First opening 71 and multiple second opening 73 is formed in described welding resisting layer 70.The described second external conducting wire figure 117 of part exposes from described first opening 71, to define at least one golden finger end 113.The described first external conducting wire figure 111 of part exposes from described multiple second opening 73, to define multiple weld pad 118.In other embodiments, when being plated layers of copper in conductive through hole 218 and filling up, described welding resisting layer only needs to be formed on described first external conducting wire figure 111 and on the second external conducting wire figure 117.
Described golden finger end 113 is formed with first protective layer 114.Each described weld pad 118 is all formed with the second protective layer 119.Described first protective layer 114 can be nickel-gold layer.Second protective layer 119 can weld film (OSP) for organic guarantor, also can be NiPdAu layer.
Centreless layer package substrate that the technical program provides and preparation method thereof, dielectric layer is made up of the first film and the second film, inner layer conductive line pattern is embedded in described dielectric layer, first external conducting wire figure and the second external conducting wire figure lay respectively at the relative both sides of described dielectric layer, and described first external conducting wire figure, the second external conducting wire figure and inner layer conductive line pattern are electrical connected by the conductive through hole be formed in described dielectric layer, do not need to arrange sandwich layer, reduce the thickness of centreless layer package substrate.In addition, in above-mentioned manufacture method, two circuit substrates can be made simultaneously, thus improve the make efficiency of centreless layer package substrate.
Be understandable that, for the person of ordinary skill of the art, other various corresponding change and distortion can be made by technical conceive according to the present invention, and all these change the protection range that all should belong to the claims in the present invention with distortion.
Claims (10)
1. a centreless layer package substrate, it comprises dielectric layer, inner layer conductive line pattern, the first external conducting wire figure and the second external conducting wire figure, described inner layer conductive line pattern is embedded in described dielectric layer, described first external conducting wire figure and the second external conducting wire figure lay respectively at the relative both sides of described dielectric layer, and described inner layer conductive line pattern, the first external conducting wire figure and the second external conducting wire figure are electrical connected by the conductive through hole in described dielectric layer.
2. centreless layer package substrate as claimed in claim 1, it is characterized in that, described conductive through hole is the conductive hole of hollow, described centreless layer package substrate also comprises one deck welding resisting layer, described welding resisting layer is covered in described first external conducting wire figure and the second external conducting wire figure, and is filled in described conductive through hole.
3. centreless layer package substrate as claimed in claim 2; it is characterized in that, described welding resisting layer has first opening, and part second external conducting wire figure exposes from described first opening; form at least one golden finger end, described golden finger end is also formed with first protective layer.
4. centreless layer package substrate as claimed in claim 2, it is characterized in that, described welding resisting layer has multiple second opening, and part first external conducting wire figure exposes from described multiple second opening, forms multiple weld pad.
5. centreless layer package substrate as claimed in claim 1, it is characterized in that, the ratio of the distance between described first external conducting wire figure and inner layer conductive line pattern and the distance between described second external conducting wire figure and inner layer conductive line pattern is between 0.8 to 1.2.
6. a manufacture method for centreless layer package substrate, it comprises:
A loading plate is provided, described loading plate comprises relative first surface and second surface, superimposed first Copper Foil successively on the first surface of described loading plate, first film and second Copper Foil, another first Copper Foil superimposed successively on described second surface, another first film and another the second Copper Foil, and the second Copper Foil on first surface described in one step press, the second Copper Foil on described loading plate and described second surface, to obtain first solderless substrate, described first solderless substrate comprises a processing district and the first garbage area around described processing district,
Each second Copper Foil is all made and forms inner layer conductive line pattern;
Superimposed second film and the 3rd Copper Foil successively on each described inner layer conductive line pattern, and described second film on the upside of the first solderless substrate described in one step press and the second film on the downside of the 3rd Copper Foil, described first solderless substrate and the first solderless substrate and the 3rd Copper Foil, obtain the second solderless substrate, in described second solderless substrate, be positioned at the first film on the upside of described first surface and the second film forms a dielectric layer jointly, the first film on the downside of described first surface and the second film form a dielectric layer jointly;
Remove described first garbage area, and remove described loading plate, obtain two circuit substrates be separated from each other, each circuit substrate all has product zone and the second garbage area around described product zone, each circuit substrate includes a described dielectric layer, described first Copper Foil, described 3rd Copper Foil and a described inner layer conductive line pattern, described first Copper Foil and the 3rd Copper Foil lay respectively at the relative both sides of described dielectric layer, and described inner layer conductive line pattern is embedded in described dielectric layer;
In the product zone of described circuit substrate, form multiple through hole, each described through hole all runs through described circuit substrate, and each through hole is all made conductive through hole, and described conductive through hole is electrically connected described first Copper Foil, inner layer conductive line pattern and the 3rd Copper Foil;
On the surface of described first Copper Foil, the first external conducting wire figure is formed at described dielectric layer, on the surface of described 3rd Copper Foil, form the second external conducting wire figure at described dielectric layer, described first external conducting wire figure, the second external conducting wire figure and inner layer conductive line pattern are electrical connected by described conductive through hole; And
Remove described second garbage area, obtain centreless layer package substrate.
7. the manufacture method of centreless layer package substrate as claimed in claim 6, it is characterized in that, described conductive through hole is the conductive hole of mesopore, after formation first external conducting wire figure and the second external conducting wire patterning step, before removing described second garbage area step, the manufacture method of described centreless layer package substrate is also included on described first external conducting wire figure, welding resisting layer is formed on second external conducting wire figure and in each described conductive through hole, described welding resisting layer is covered in described first external conducting wire figure and the second external conducting wire figure, and be filled in described conductive through hole, and in described welding resisting layer, form the step of first opening and multiple second opening, the described second external conducting wire pattern of part exposes from described first opening, to define at least one golden finger end, the described first external conducting wire figure of part exposes from described multiple second opening, to define multiple weld pad.
8. the manufacture method of centreless layer package substrate as claimed in claim 7; it is characterized in that; after the described welding resisting layer step of formation; before removing described second garbage area step; the manufacture method of described centreless layer package substrate is also included on described golden finger end and forms first protective layer, and each described weld pad is all formed the step of second protective layer.
9. the manufacture method of centreless layer package substrate as claimed in claim 6, it is characterized in that, after obtaining described first solderless substrate step, each second Copper Foil is all made before forming inner layer conductive line pattern, the manufacture method of described centreless layer package substrate is also included in the step that described first garbage area forms multiple first tooling hole, and each first tooling hole all runs through described first solderless substrate.
10. the manufacture method of centreless layer package substrate as claimed in claim 6, it is characterized in that, the ratio of the distance between described first external conducting wire figure and inner layer conductive line pattern and the distance between described second external conducting wire figure and inner layer conductive line pattern is between 0.8 to 1.2.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310265770.4A CN104254191B (en) | 2013-06-28 | 2013-06-28 | Centreless layer package substrate and preparation method thereof |
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|---|---|---|---|
| CN201310265770.4A CN104254191B (en) | 2013-06-28 | 2013-06-28 | Centreless layer package substrate and preparation method thereof |
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| CN104254191B CN104254191B (en) | 2017-08-25 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107611036A (en) * | 2016-07-12 | 2018-01-19 | 碁鼎科技秦皇岛有限公司 | Package substrate and preparation method thereof, encapsulating structure |
| CN113498275A (en) * | 2020-04-07 | 2021-10-12 | 无锡深南电路有限公司 | Preparation method of coreless circuit board |
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| US20060284640A1 (en) * | 2005-06-20 | 2006-12-21 | Shing-Ru Wang | Structure of circuit board and method for fabricating the same |
| US20060283625A1 (en) * | 2005-06-17 | 2006-12-21 | Nec Corporation | Wiring board, method for manufacturing same, and semiconductor package |
| CN101364587A (en) * | 2007-08-10 | 2009-02-11 | 全懋精密科技股份有限公司 | Circuit board construction for embedding capacitor element and preparation thereof |
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2013
- 2013-06-28 CN CN201310265770.4A patent/CN104254191B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060283625A1 (en) * | 2005-06-17 | 2006-12-21 | Nec Corporation | Wiring board, method for manufacturing same, and semiconductor package |
| US20060284640A1 (en) * | 2005-06-20 | 2006-12-21 | Shing-Ru Wang | Structure of circuit board and method for fabricating the same |
| CN101364587A (en) * | 2007-08-10 | 2009-02-11 | 全懋精密科技股份有限公司 | Circuit board construction for embedding capacitor element and preparation thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107611036A (en) * | 2016-07-12 | 2018-01-19 | 碁鼎科技秦皇岛有限公司 | Package substrate and preparation method thereof, encapsulating structure |
| CN113498275A (en) * | 2020-04-07 | 2021-10-12 | 无锡深南电路有限公司 | Preparation method of coreless circuit board |
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| Publication number | Publication date |
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| CN104254191B (en) | 2017-08-25 |
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Effective date of registration: 20161220 Address after: 066004 Qinhuangdao economic and Technological Development Zone, Hebei Tengfei Road, No. 18 Applicant after: Qi Ding Technology Qinhuangdao Co.,Ltd. Applicant after: Zhen Ding Technology Co.,Ltd. Address before: 066000 Qinhuangdao economic and Technological Development Zone, Hebei Tengfei Road, No. 18 Applicant before: HONGQISHENG PRECISION ELECTRONICS (QINHUANGDAO) Co.,Ltd. Applicant before: Zhen Ding Technology Co.,Ltd. |
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