CN103458628B - Multilayer circuit board and making method thereof - Google Patents
Multilayer circuit board and making method thereof Download PDFInfo
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- CN103458628B CN103458628B CN201210171915.XA CN201210171915A CN103458628B CN 103458628 B CN103458628 B CN 103458628B CN 201210171915 A CN201210171915 A CN 201210171915A CN 103458628 B CN103458628 B CN 103458628B
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Abstract
The present invention provides the making method of a kind of multilayer circuit board, comprises step: provide dielectric base, and it has the first relative surface and the 2nd surface; Dielectric base is formed run through the first surface and the 2nd surface through hole, be only exposed to the first blind slot figure on the first surface and be only exposed to the 2nd blind slot figure on the 2nd surface; Deposits conductive material on a dielectric base, to form the flat together first line figure of the conductive hole being embedded in dielectric base and the first surface and two line pattern flat together with the 2nd surface, first line figure has assembling district and pressing district; Forming the first pressing substrate on the first surface thus obtain multilager base plate, the first pressing substrate comprises the first conductive circuit layer and the first film; And remove the first pressing substrate corresponding with assembling district, and it being exposed to outer groove to form one in multilager base plate, assembling district exposes in a groove. The present invention also provides a kind of multilayer circuit board being made up of above method.
Description
Technical field
The present invention relates to circuit board technology, particularly relate to a kind of multilayer circuit board and the making method thereof with groove.
Background technology
In information, communication and consumer electronics industry, circuit card is the indispensable basic constitutive requirements of all electronic products. Along with electronic product develops toward miniaturization, high speedization direction, circuit card also from single-sided circuit board toward double-sided PCB, multilayer circuit board direction develops. Multilayer circuit board, especially the multilayer circuit board burying electronic devices and components in is widely used especially, refer to Takahashi, A. people is waited to be published in IEEETrans.onComponents in 1992, the document " HighdensitymultilayerprintedcircuitboardforHITACM ~ 880 " of Packaging, andManufacturingTechnology.
The multilayer circuit board inside burying electronic devices and components generally has a groove, with embedding electronic devices and components. But, on the one hand, owing to the existence of groove reduces the area of line design so that built-in type circuit card may have bigger thickness; On the other hand, when groove is assembled electronic devices and components, it is easy to occur the phenomenon of assembly failure, so then affects good rate and the quality of circuit card.
Summary of the invention
Therefore, it is necessary to provide a kind of multilayer circuit board with groove and the making method thereof with better product quality.
A kind of multilayer circuit board and making method thereof below will be described with embodiment.
A making method for multilayer circuit board, comprises step: provide dielectric base, and described dielectric base has the first relative surface and the 2nd surface, dielectric base is formed at least one through hole running through the first surface and the 2nd surface, and is formed and be only exposed to the first blind slot figure on the first surface and be only exposed to the 2nd blind slot figure on the 2nd surface, by coating technology deposits conductive material on a dielectric base, so that electro-conductive material is filled at least one through hole described forms at least one conductive hole, it is filled in the first blind slot figure and forms first line figure, also it is filled in the 2nd blind slot figure and forms the 2nd line pattern, described first line figure is embedded in dielectric base and puts down with the first surface is neat, described 2nd line pattern is embedded in dielectric base and puts down with the 2nd surface is neat, described first line figure has assembling district and around the pressing district assembling district, described first line figure is electrically connected with the 2nd line pattern by least one conductive hole described, form the first pressing substrate on the first surface of dielectric base thus obtain multilager base plate, described first pressing substrate comprises the first conductive circuit layer and the first film, described first film is pressed together between the first conductive circuit layer and the first surface, and described first conductive circuit layer is electrically connected with first line figure, and remove the first pressing substrate corresponding with assembling district, thus in multilager base plate, form one be exposed to outer groove, described assembling district is exposed in described groove.
Preferably, after formation one is exposed to outer groove in multilager base plate, also comprising the step installing electronic devices and components in a groove, described electronic devices and components are electrically connected with the assembling district of first line figure.
Preferably, described assembling district comprises multiple pad, and described electronic devices and components have and multiple one to one with multiple pad are connected terminal, and each is connected terminal and is all electrically connected with a pad by a weldering ball projection.
A kind of multilayer circuit board, it comprises the first pressing substrate and the circuit base plate being pressed on together. Described first pressing substrate comprises the first conductive circuit layer and the first film. Described circuit base plate comprises dielectric base, first line figure, the 2nd line pattern and at least one conductive hole. Described dielectric base has the first relative surface and the 2nd surface, and described first film is between the first conductive circuit layer and the first surface. Described first line figure, the 2nd line pattern and at least one conductive hole are all embedded in dielectric base. At least one conductive hole described is exposed to the first surface and the 2nd surface, and all flushes with the first surface, the 2nd surface. Described first line figure is only exposed to the first surface and neat flat with the first surface, and described first line figure comprises assembling district and around the pressing district assembling district. Described 2nd line pattern is only exposed to the 2nd surface and puts down with the 2nd surface is neat, and described 2nd line pattern is electrically connected with first line figure by least one conductive hole described. It is that run through the first pressing substrate and be exposed to outer groove that described multilayer circuit board has one, and described groove is corresponding with assembling district, and the exposure of described assembling district is in a groove.
A kind of multilayer circuit board, it comprises the first pressing substrate, circuit base plate and electronic devices and components. Together with described first pressing substrate is pressed on circuit base plate. Described first pressing substrate comprises the first conductive circuit layer and the first film. Described circuit base plate comprises dielectric base, first line figure, the 2nd line pattern and at least one conductive hole. Described dielectric base has the first relative surface and the 2nd surface, and described first film is between the first conductive circuit layer and the first surface. Described first line figure, the 2nd line pattern and at least one conductive hole are all embedded in dielectric base. At least one conductive hole described is exposed to the first surface and the 2nd surface, and all flushes with the first surface, the 2nd surface. Described first line figure is only exposed to the first surface and neat flat with the first surface, and described first line figure comprises assembling district and around the pressing district assembling district. Described 2nd line pattern is only exposed to the 2nd surface and puts down with the 2nd surface is neat, and described 2nd line pattern is electrically connected with first line figure by least one conductive hole described. It is that run through the first pressing substrate and be exposed to outer groove that described multilayer circuit board has one, and described groove is corresponding with assembling district, and in a groove, described electronic devices and components are placed in described groove and are installed on the assembling district of circuit base plate the exposure of described assembling district.
In the technical program, by first formed in insulated substrate blind slot figure made by the method for coating technology deposits conductive material again have in sunken cord the circuit base plate on road, this circuit base plate at least has the following advantages as the central layer of the multilayer circuit board with groove: on the one hand, the pad exposing circuit base plate in a groove is separated by the material of insulated substrate each other, there will not be tin bridge phenomenon when assembling electronic devices and components, ensure that the good rate of assembling; On the other hand, this circuit base plate can conveniently realize the design on fine rule road, it is also possible to reduces the thickness of whole multilayer circuit board, is conducive to lightening, short and smallization of realizing circuit plate.
Accompanying drawing explanation
The schematic diagram of the double-sided copper-clad substrate that Fig. 1 provides for the technical program first embodiment.
The schematic diagram of the dielectric base that Fig. 2 provides for the technical program first embodiment.
Fig. 3 is the schematic diagram after the dielectric base of use laser ablation Fig. 2.
Fig. 4 is schematic diagram after deposits conductive material in the dielectric base of Fig. 3.
The schematic diagram of the circuit base plate that Fig. 5 provides for the technical program first embodiment.
Fig. 6 is the schematic top plan view of Fig. 5.
Fig. 7 is the schematic diagram arranging protection film on the circuit base plate of Fig. 5.
Fig. 8 is the schematic diagram after pressing film and Copper Foil are distinguished in the both sides up and down of the circuit base plate of Fig. 7.
Fig. 9 is the schematic diagram after forming blind guide hole in the film of pressing.
Figure 10 is the schematic diagram of four laminar substrates obtained after the Copper Foil of pressing is made conductive circuit layer.
Figure 11 is the schematic diagram forming a groove in four laminar substrates of Figure 10.
Figure 12 is the schematic diagram after assembling electronic devices and components in the groove of four laminar substrates of Figure 11.
Figure 13 is the schematic diagram after pressing film and Copper Foil are distinguished in the both sides up and down of four laminar substrates of Figure 10.
Figure 14 is the schematic diagram after forming blind guide hole in the film of pressing.
Figure 15 is the schematic diagram of six laminar substrates obtained after the Copper Foil of pressing is made conductive circuit layer.
Figure 16 is the schematic diagram forming a groove in six laminar substrates.
Figure 17 is the schematic diagram of the 6-layer circuit board obtained after the six laminar substrate both sides of Figure 16 form welding resisting layer respectively.
Figure 18 is the schematic diagram after assembling electronic devices and components in the groove of the 6-layer circuit board of Figure 17.
Main element nomenclature
| Dielectric base | 100 |
| First surface | 111 |
| 2nd surface | 112 |
| Double-sided copper-clad substrate | 120 |
| Upside Copper Foil | 121 |
| Downside Copper Foil | 122 |
| Through hole | 130 |
| First blind slot figure | 131 |
| 2nd blind slot figure | 132 |
| Electro-conductive material | 14 |
| Conductive hole | 101 |
| First line figure | 11 |
| 2nd line pattern | 12 |
| Circuit base plate | 10 |
| Assembling district | 1101 |
| Pressing district | 1102 |
| Pad | 113 |
| Circuit | 114 |
| Protection film | 15 |
| First pressing substrate | 21��61 |
| 2nd pressing substrate | 22��62 |
| First conductive circuit layer | 211 |
| First film | 212 |
| 2nd conductive circuit layer | 221 |
| 2nd film | 222 |
| First Copper Foil | 210 |
| 2nd Copper Foil | 220 |
| First blind guide hole | 102 |
| 2nd blind guide hole | 103 |
| Four laminar substrates | 10a |
| First opening | 213 |
| Groove | 31��71 |
| First welding resisting layer | 41��81 |
| 2nd welding resisting layer | 42��82 |
| Four-layer circuit board | 10b��10c |
| Electronic devices and components | 50��90 |
| Connect terminal | 51��91 |
| Weldering ball projection | 52��92 |
| 3rd film | 612 |
| 3rd Copper Foil | 610 |
| 4th film | 622 |
| 4th Copper Foil | 620 |
| 3rd blind guide hole | 104 |
| 4th blind guide hole | 105 |
| Conducting hole | 106 |
| 3rd conductive circuit layer | 611 |
| 4th conductive circuit layer | 621 |
| Six laminar substrates | 10d |
| 2nd opening | 613 |
| 6-layer circuit board | 10e��10f |
Following embodiment will illustrate the present invention further in conjunction with above-mentioned accompanying drawing.
Embodiment
Below in conjunction with accompanying drawing and multiple embodiment, the multilayer circuit board and the making methods thereof that provide the technical program are described in further detail.
The making method of the multilayer circuit board that the technical program first embodiment provides, comprises step:
The first step, sees also Fig. 1 and Fig. 2, it is provided that dielectric base 100, and described dielectric base 100 has the first relative surface 111 and the 2nd surface 112.
Described dielectric base 100 can be the insulation sheet material bought, it is also possible to made by the copper-clad base plate of etching purchase. In the present embodiment, described dielectric base 100 is formed as follows: first, thering is provided double-sided copper-clad substrate 120, described double-sided copper-clad substrate 120 comprises described dielectric base 100 and is fitted in upside Copper Foil 121 and the downside Copper Foil 122 of dielectric base 100 both sides; Secondly, etch double-sided copper-clad substrate 120 with chemical etching liquor, thus remove upside Copper Foil 121 and downside Copper Foil 122, namely define described dielectric base 100. The thickness of described dielectric base 100 is 40-80 micron.
2nd step, refer to Fig. 3, use laser ablation dielectric base 100, dielectric base 100 is formed at least one through hole 130 running through the first surface 111 and the 2nd surface 112, and is formed and be only exposed to the first blind slot figure 131 on the first surface 111 and be only exposed to the 2nd blind slot figure 132 on the 2nd surface 112. Described first blind slot figure 131 is for forming a line pattern, it comprises multiple first blind slot, described multiple first blind slot has the substantially identical degree of depth and different shapes, and it comprises multiple blind slot corresponding with circuit shape and multiple blind slot corresponding with bond pad shapes. 2nd blind slot figure 132 is also for forming a line pattern, it comprises multiple 2nd blind slot, described multiple 2nd blind slot has the substantially identical degree of depth and different shapes, also comprises multiple blind slot corresponding with circuit shape and multiple blind slot corresponding with bond pad shapes. Preferably, the degree of depth of the first blind slot equals the degree of depth of the 2nd blind slot. Generally speaking, the degree of depth of the first blind slot, the 2nd blind slot is 15-25 micron.
3rd step, refers to Fig. 4, by coating technology deposits conductive material 14 in dielectric base 100 so that electro-conductive material 14 is deposited at least one through hole 130, in the first blind slot figure 131 and in the 2nd blind slot figure 132. Described electro-conductive material 14 can be copper, it is also possible to be the materials such as carbon black, nickel, silver, gold, it is also possible to be the combination of above material. Such as, can by chemical-copper-plating process or blackening craft in dielectric base surface deposition chemistry layers of copper or carbon black layer, then by copper plating process in chemistry layers of copper or carbon black layer surface deposition copper electroplating layer, the electro-conductive material 14 being full the electro-conductive material 14 of copper or being made up of carbon black and copper can so then be formed.
It will be appreciated by those skilled in the art that, if not covering the first surface 111 and the 2nd surface 112 before deposits conductive material 14, then electro-conductive material 14 also can be deposited on the first surface 111 and the 2nd surface 112. In addition; in order to guarantee electro-conductive material 14 enough in deposition at least one through hole 130, in the first blind slot figure 131 and in the 2nd blind slot figure 132; usually can slightly extend the plating time, and make the electro-conductive material 14 being deposited at least one through hole 130, in the first blind slot figure 131 and in the 2nd blind slot figure 132 protrude from the first surface 111 and the 2nd surface 112.
Refer to Fig. 5, also need after deposits conductive material 14 to remove the electro-conductive material 14 protruding from the first surface 111 and the 2nd surface 112 through the step of overground brush or etching. That is, be deposited on the first surface 111 and the 2nd electro-conductive material 14 on surface 112 will be removed, make simultaneously the electro-conductive material 14 being deposited at least one through hole 130 respectively with the first surface 111 and the 2nd surface 112 flushes, electro-conductive material 14 in the first blind slot figure 131 and the first surface 111 is put down together, electro-conductive material 14 in the 2nd blind slot figure 132 and the 2nd surface 112 are put down together. Thus, electro-conductive material 14 is filled at least one through hole 130 described and forms at least one conductive hole 101, is filled in the first blind slot figure 131 and forms first line figure 11, is filled in the 2nd blind slot figure 132 and forms the 2nd line pattern 12. Described first line figure 11 is embedded in dielectric base 100 and flushes with the first surface 111, and described 2nd line pattern 12 is embedded in dielectric base 100 and flushes with the 2nd surface 112. Described first line figure 11 and the 2nd line pattern 12 include many articles of conducting wires and multiple pad, conducting wire and pad in described first line figure 11 are all put down together with the first surface 111, and conducting wire and pad in described 2nd line pattern 12 are all put down together with the 2nd surface 112. So, dielectric base 100, first line figure 11 and the 2nd line pattern 12 combined closely can form have in bury the circuit base plate 10 of line pattern.
Certainly, it will be appreciated by those skilled in the art that, if being blinded by the first surface 111 and the 2nd surface 112 before deposits conductive material 14, and plating condition and plating time is strictly controlled when plating, so that the electro-conductive material 14 being deposited at least one through hole 130 flushes with the first surface 111 and the 2nd surface 112 just respectively, electro-conductive material 14 and the first surface 111 in first blind slot figure 131 are put down together, electro-conductive material 14 and the 2nd surface 112 in 2nd blind slot figure 132 are put down together, then follow-up needs removes the electro-conductive material 14 protruding from the first surface 111 and the 2nd surface 112 by the step of mill brush or etching, circuit base plate 10 can be obtained.
In the present embodiment, define described first line figure 11 comprise assembling district 1101 and around be connected to assembling district 1101 around pressing district 1102, as shown in Figure 6. Assembling district 1101 in the present embodiment for rectangle, it at least has multiple pad 113, and described pressing district 1102 is around described assembling district 1101, and it at least has many circuits 114. It will be appreciated by those skilled in the art that, pad in first line figure 11 and the quantity of circuit and shape are determined according to the circuit layout of circuit card, generally there is more pad and circuit, in Fig. 5 and Fig. 6 of the present embodiment, only schematically draw a circuit 114 in pressing district 1102, schematically draw two pads 113 in assembling district 1101.
4th step, refers to Fig. 7, arranges protection film 15 in the assembling district 1101 of described first line figure 11, to protect the pad 113 in assembling district 1101. Described protection film 15 can be release film. The cross-sectional area of protection film 15 can equal or be slightly less than the cross-sectional area in assembling district 1101, only needs fully to cover the circuit assembled in district 1101 and pad 113. In the present embodiment, the cross-sectional area of protection film 15 is slightly less than the cross-sectional area in assembling district 1101.
5th step, refer to Fig. 8 to Figure 10, the first surperficial 111 side pressings at circuit base plate 10 form the first pressing substrate 21, the 2nd pressing substrate 22 is formed in the 2nd surperficial 112 side pressings, and the first pressing substrate 21 is conducted with first line figure 11, the 2nd pressing substrate 22 and the 2nd line pattern 12 conduct.
In the present embodiment, the first pressing substrate 21 is single layer substrate, and it comprises the first conductive circuit layer 211 and the first film the 212, two pressing substrate 22 is also single layer substrate, and it comprises the 2nd conductive circuit layer 221 and the 2nd film 222. Specifically, pressing first pressing substrate 21 and the 2nd pressing substrate 22 can be realized by following technique: first provide the first film 212, first Copper Foil 210, the 2nd film 222 and the 2nd Copper Foil 220; First film 212 is placed on the first surface 111 and covering protection film 15, first Copper Foil 210 is placed on the upside of the first film 212, and also the 2nd film 222 is arranged on the 2nd surface 112,2nd Copper Foil 220 is placed on the downside of the 2nd film 222, that is, by stacking successively to the first Copper Foil 210, first film 212, circuit base plate 10, the 2nd film 222 and the 2nd Copper Foil 220; Then the first stacking Copper Foil 210, first film 212, circuit base plate 10, the 2nd film 222 and the 2nd Copper Foil 220 are put into pressing machine, first Copper Foil 210, first film 212, circuit base plate 10, the 2nd film 222 and the 2nd Copper Foil 220 described in one step press, form four layers of force fit plate, as shown in Figure 8. Secondly in four layers of force fit plate, at least one first blind hole and at least one the 2nd blind hole is formed by laser drill technology, at least one first blind hole described only runs through the first Copper Foil 210 and the first film 212 of the first pressing substrate 21, and at least one the 2nd blind hole described only runs through the 2nd Copper Foil 220 and the 2nd film 222 of the 2nd pressing substrate 22; Then the copper layer at least one first blind hole described and at least one the 2nd blind hole by chemical-copper-plating process and copper plating process, thus at least one first blind hole described is made the first blind guide hole 102,2nd blind hole is made the 2nd blind guide hole 103, as shown in Figure 9. Again, the first Copper Foil 210 and the 2nd Copper Foil 220 is optionally etched by image transfer and chemical etching process, thus the first Copper Foil 210 is made the first conductive circuit layer 211,2nd Copper Foil 220 is made the 2nd conductive circuit layer 221, first conductive circuit layer 211 is conducted with first line figure 11 by least one first blind guide hole 102,2nd conductive circuit layer 221 is conducted by least one the 2nd blind guide hole 103 and the 2nd line pattern 12, so can obtain four laminar substrate 10a as shown in Figure 10. All having many articles of conducting wires and multiple pad in described first conductive circuit layer 211 and the 2nd conductive circuit layer 221, concrete circuit layout can be determined on demand.
Preferably, when selective etch the first Copper Foil 210, part first Copper Foil 210 corresponding with the border in assembling district 1101 is removed in etching, forms first opening 213 corresponding with the border in assembling district 1101 in the first conductive circuit layer 211.
6th step; refer to Figure 11; remove the part first pressing substrate 21 corresponding with assembling district 1101, thus in four laminar substrate 10a, form that only run through the first pressing substrate 21 and corresponding with assembling district 1101 groove 31, and remove the protection film 15 being fitted in assembling surface, district 1101.
Specifically, it is possible to form groove 31 as follows: first use laser to cut the first pressing substrate 21 along the border in assembling district 1101, namely cut the first conductive circuit layer 211 and the first film 212. After cutting, this part first pressing substrate 21 i.e. the first pressing substrate 21 with other regions above assembling district 1101 is separated from each other, that is, assemble the first pressing substrate 21 above district 1101 namely with pressing district 1102 above the first pressing substrate 21 be separated from each other. So, the first pressing substrate 21 peeling off this part corresponding with assembling district 1101 can form groove 31. In the present embodiment, due to the existence of the first opening 213 in the first conductive circuit layer 211, directly from the first opening 213, cut first film 212 along the border in assembling district 1101 with laser, then directly peel off this part first film 212 above assembling district 1101 and can remove this part first pressing substrate 21 corresponding with assembling district 1101, thus form groove 31. It will be appreciated by those skilled in the art that, when protect the bounding force between film 15 and the first film 212 better and with the bounding force on assembling surface, district 1101 poor time, namely, when the bounding force protecting the bounding force between film 15 and the first film 212 to be better than between protection film 15 and assembling surface, district 1101, the film 15 of self-assembly district 1101 sur-face peeling protection simultaneously is got final product when peeling off the first film 212; When protect the bounding force between film 15 and the first film 212 poor and with the bounding force on assembling surface, district 1101 better time; namely when protecting the poor adhesion between film 15 and the first film 212 in time protecting the bounding force between film 15 and assembling surface, district 1101, it is possible to again from assembling district 1101 sur-face peeling protection film 15 after peeling off the first film 212. Now, after peeling off the first film 212, protection film 15 is exposed in groove 31, it is possible to than relatively easily from assembling district 1101 sur-face peeling protection film 15, expose the pad 113 in assembling district 1101.
Described groove 31 has the shape corresponding with assembling district 1101 and position, and in the present embodiment, shape and the position in the shape of groove 31 assembling district 1101 as shown in Figure 6 are corresponding, that is, groove 31 is for being positioned at the rectangle blind slot in the middle part of four laminar substrate 10a.
Before forming groove 31 or after forming groove 31; first welding resisting layer 41 can also be set on the first conductive circuit layer 211 surface; 2nd welding resisting layer 42 is set on the 2nd conductive circuit layer 221 surface, thus protects the circuit in the first conductive circuit layer 211 and the 2nd conductive circuit layer 221 and pad. So, the four-layer circuit board 10b with groove 31 can be obtained.
7th step, refers to Figure 12, installs electronic devices and components 50 in groove 31, and described electronic devices and components 50 are electrically connected with the assembling district 1101 of first line figure 11. Specifically, first providing described electronic devices and components 50, it can be active member or passive element, such as chip. The surface of described electronic devices and components 50 has multiple connection terminal 51, described multiple connection terminal 51 and multiple pads 113 one_to_one corresponding in assembling district 1101. Secondly, connect terminal 51 surface at each and weldering ball projection 52 is set, and electronic devices and components 50 are positioned in groove 31 so that the weldering ball projection 52 on connection terminal 51 surface that each pad 113 is all corresponding with it contacts. Again, make each weldering ball projection 52 melting by reflow and it is electrically connected one after solidification and connects terminal 51 and a pad 113. So, the electrical connection of electronic devices and components 50 with first line figure 11 can be realized, obtain the four-layer circuit board 10c that structure has filled electronic devices and components 50.
Preferably, it is also possible to fill encapsulation adhesion material between described electronic devices and components 50 and groove 31, better to fix electronic devices and components 50.
As shown in figure 12, it comprises the first welding resisting layer 41, first pressing substrate 21, circuit base plate 10, the 2nd pressing substrate 22, the 2nd welding resisting layer 42 and electronic devices and components 50 to the four-layer circuit board 10c that above step according to the first embodiment obtains. Described first pressing substrate 21, circuit base plate 10 and the 2nd pressing substrate 22 pressing successively. Described first pressing substrate 21 comprises the first conductive circuit layer 211 and the first film 212. First welding resisting layer 41 is arranged at the first pressing substrate 21 surface, and covers the first conductive circuit layer 211. Described 2nd pressing substrate 22 comprises the 2nd conductive circuit layer 221 and the 2nd film 222. 2nd welding resisting layer 42 is arranged at the 2nd pressing substrate 22 surface, and covers the 2nd conductive circuit layer 221 surface. Described circuit base plate 10 comprises dielectric base 100 and interior first line figure 11, the 2nd line pattern 12 and at least one conductive hole 101 being embedded in dielectric base 100. Wherein, first line figure 11 is only exposed to the first surface 111 and puts down together with the first surface 111, and the 2nd line pattern 12 is only exposed to the 2nd surface 112 and puts down together with the 2nd surface 112. Conductive hole 101 is exposed to the first surface 111, the 2nd surface 112, and puts down all together with the first surface 111, the 2nd surface 112, for being electrically connected first line figure 11 and the 2nd line pattern 12. First conductive circuit layer 211, first line figure 11, the 2nd line pattern 12 and the 2nd conductive circuit layer 221 are conducted by the blind guide hole 102 of conductive hole 101, first and the 2nd blind guide hole 103. Described four-layer circuit board 10c has the groove 31 running through the first pressing substrate 21 and the first welding resisting layer 41, and groove 31 is one and is exposed to outside blind slot. The assembling district 1101 of first line figure 11 is exposed in groove 31. Electronic devices and components 50 are arranged in groove 31, are installed on multiple pads 113 in assembling district 1101 and outside being exposed to. Electronic devices and components 50 have multiple connection terminal 51, and it realizes being electrically connected by multiple weldering ball projection 52 and first line figure 11.
Owing to first line figure 11 is embedded in dielectric base 100, separated by the material of dielectric base 100 between each pad 113, when therefore assembling electronic devices and components 50 in groove 31, there will not be the phenomenon of Xi Qiao (solderbridge) between each weldering ball projection 52, ensure that the good rate that electronic devices and components 50 are assembled.
In addition, owing to first line figure 11 is by etching the formation of rear plating, it is possible to conveniently realize the design on fine rule road; And it is embedded in dielectric base 100 due to first line figure 11, compared to previous technology, it is possible to reduce the thickness of whole four-layer circuit board 10c, it is achieved lightening, short and smallization of circuit card.
It will be appreciated by those skilled in the art that, the step in the method for the making multilayer circuit board of the first embodiment is not essential features. Such as, in the third step, it is possible to only pressing first pressing substrate 21 on the upside of circuit base plate 10, and pressing the 2nd pressing substrate 22 on the downside of online base board 10 time different, so, after subsequent step, it is possible to make three layer circuit boards with a groove. Equally, the element in the four-layer circuit board 10c that the first embodiment is obtained is also not essential features, such as, and the first welding resisting layer 41 and the 2nd welding resisting layer 42. In addition, first conductive circuit layer 211, first line figure 11, the 2nd line pattern 12 and the 2nd conductive circuit layer 221 are not limited to realize conducting by the blind guide hole 102 of conductive hole 101, first and the 2nd blind guide hole 103, the first blind guide hole 102 and the 2nd blind guide hole 103 can not also be formed, and form the conducting hole that at least one runs through four-layer circuit board 10c, conduct to realize each layer.
Certainly, it will be appreciated by those skilled in the art that, except making three layer circuit boards or four-layer circuit board with a groove, the technical program can make the multilayer circuit board of any number of plies with any amount groove. Such as, more than one groove can also be formed in the 6th step, such as two or three grooves, so namely can be made into the multilayer circuit board with two or more groove. Again such as, continue addition film and Copper Foil in four laminar substrate 10a both sides shown in Figure 10, namely can be made into the multilayer circuit board of more than four layers. Hereinafter, it is described to make the 6-layer circuit board with a groove.
The making method of the multilayer circuit board that the technical program the 2nd embodiment provides, comprises step:
The first step, refers to Fig. 7, it is provided that what in the first embodiment, the 4th step obtained is provided with the circuit base plate 10 after protection film 15.
2nd step, refer to Fig. 8 to Figure 10 and Figure 13 to Figure 15, the first surperficial 111 side pressings in dielectric base 100 form the first pressing substrate 61, the 2nd pressing substrate 62 is formed in the 2nd surperficial 112 side pressings, and the first pressing substrate 61 is conducted with first line figure 11, the 2nd pressing substrate 62 and the 2nd line pattern 12 conduct.
In the present embodiment, first pressing substrate 61 is multilager base plate, it comprises the first film 212, first conductive circuit layer 211, the 3rd film 612 and the 3rd conductive circuit layer 611,2nd pressing substrate 62 is also multilager base plate, and it comprises the 2nd film 222, the 2nd conductive circuit layer 221, the 4th film 622 and the 4th conductive circuit layer 621. specifically, form the first pressing substrate 61 and the 2nd pressing substrate 62 can be realized by following technique: first, refer to Fig. 8 to Figure 10, by the concrete steps in the 5th step in the first embodiment, the first surperficial 111 side pressings at circuit base plate 10 form the first film 212 and the first conductive circuit layer 211, the 2nd surperficial 112 side pressings at circuit base plate 10 form the 2nd film 222 and the 2nd conductive circuit layer 221, first conductive circuit layer 211 is conducted with first line figure 11 by least one first blind guide hole 102, 2nd conductive circuit layer 221 is conducted by least one the 2nd blind guide hole 103 and the 2nd line pattern 12, so can obtain four laminar substrate 10a as shown in Figure 10. secondly, refer to Figure 13, it is provided that the 3rd film 612, the 3rd Copper Foil 610, the 4th film 622 and the 4th Copper Foil 620, 3rd film 612 is placed on above the first conductive circuit layer 211,3rd Copper Foil 610 is placed on the 3rd film 612, and also the 4th film 622 is arranged on below the 2nd conductive circuit layer 221,4th Copper Foil 620 is placed on the downside of the 4th film 622, stacking successively by the 3rd Copper Foil 610, the 3rd film 612, four laminar substrate 10a, the 4th film 622 and the 4th Copper Foil 620, then the 3rd stacking Copper Foil 610, the 3rd film 612, four laminar substrate 10a, the 4th film 622 and the 4th Copper Foil 620 are put into pressing machine, 3rd Copper Foil 610, the 3rd film 612, four laminar substrate 10a, the 4th film 622 and the 4th Copper Foil 620 described in one step press, form six layers of force fit plate, as shown in figure 13. again, in six layers of force fit plate, at least one the 3rd blind hole, at least one the 4th blind hole and at least one through hole is formed by drilling technique, at least one the 3rd blind hole described only runs through the 3rd Copper Foil 610 and the 3rd film 612, at least one the 4th blind hole described only runs through the 4th Copper Foil 620 and the 4th film 622, and at least one through hole described runs through the 3rd Copper Foil 610, the 3rd film 612, four laminar substrate 10a, the 4th film 622 and the 4th Copper Foil 620, then by chemical-copper-plating process and copper plating process copper layer at least one the 3rd blind hole described, at least one the 4th blind hole and at least one through hole, thus at least one the 3rd blind hole described is made the 3rd blind guide hole 104,4th blind hole is made the 4th blind guide hole 105, at least one through hole is made conducting hole 106, as shown in figure 14. finally, the 3rd Copper Foil 610 and the 4th Copper Foil 620 is optionally etched by image transfer and chemical etching process, thus the 3rd Copper Foil 610 is made the 3rd conductive circuit layer 611, 4th Copper Foil 620 is made the 4th conductive circuit layer 621, 3rd conductive circuit layer 611 is conducted by least one the 3rd blind guide hole 104 and the first conductive circuit layer 211, 4th conductive circuit layer 621 is conducted by least one the 4th blind guide hole 105 and the 2nd conductive circuit layer 221, at least one conducting hole 106 can conduct the 3rd conductive circuit layer 611, first conductive circuit layer 211, first line figure 11, 2nd line pattern 12, 2nd conductive circuit layer 221 and the 4th conductive circuit layer 621, so can obtain six laminar substrate 10d as shown in figure 15.All having many articles of conducting wires and multiple pad in described 3rd conductive circuit layer 611 and the 4th conductive circuit layer 621, concrete circuit layout can be determined on demand.
Preferably, when selective etch the 3rd Copper Foil 610, part three Copper Foil 610 corresponding with the border in assembling district 1101 is removed in etching, forming two opening 613 corresponding with the border in assembling district 1101 in the 3rd conductive circuit layer 611, described 2nd opening 613 and the first opening 213 are mutually corresponding.
3rd step; refer to Figure 16; remove the part first pressing substrate 61 corresponding with assembling district 1101, thus in six laminar substrate 10d, form that only run through the first pressing substrate 61 and corresponding with assembling district 1101 groove 71, and remove the protection film 15 being fitted in assembling surface, district 1101.
Specifically, it is possible to form groove 71 as follows: first use laser to cut the first pressing substrate 61 along the border in assembling district 1101, namely cut the 3rd conductive circuit layer 611, the 3rd film 612, first conductive circuit layer 211 and the first film 212. After cutting, this part first pressing substrate 61 i.e. the first pressing substrate 61 with other regions above assembling district 1101 is separated from each other, that is, assemble the first pressing substrate 61 above district 1101 namely with pressing district 1102 above the first pressing substrate 61 be separated from each other. So, peel off this part first pressing substrate 61 above assembling district 1101 and can form groove 71. In the present embodiment, due to the 2nd opening 613 in the 3rd conductive circuit layer 611 and the existence of the first opening 213 in the first conductive circuit layer 211, and due to the 2nd opening 613 and the first opening 213 all with assembling district 1101 border corresponding, therefore, after directly cutting the 3rd film 612 and the first film 212 from the 2nd opening 613 with laser, this part can be positioned at the first pressing substrate 61 above assembling district 1101 from circuit base plate 10 sur-face peeling.
It will be appreciated by those skilled in the art that, when protect the bounding force between film 15 and the first film 212 better and with the bounding force on assembling surface, district 1101 poor time, namely, when the bounding force protecting the bounding force between film 15 and the first film 212 to be better than between protection film 15 and assembling surface, district 1101, the film 15 of self-assembly district 1101 sur-face peeling protection simultaneously is got final product when peeling off the first film 212; When protect the bounding force between film 15 and the first film 212 poor and with the bounding force on assembling surface, district 1101 better time; namely when protecting the poor adhesion between film 15 and the first film 212 in time protecting the bounding force between film 15 and assembling surface, district 1101, it is possible to again from assembling district 1101 sur-face peeling protection film 15 after peeling off the first film 212. Now, after peeling off the first film 212, protection film 15 is exposed in groove 71, it is possible to than relatively easily from assembling district 1101 sur-face peeling protection film 15, expose the pad 113 in assembling district 1101.
After peeling off this part first pressing substrate 61 corresponding with assembling district 1101 and peeling off protection film 15, groove 71 can be formed. Groove 71 be one corresponding with the assembling shape in district 1101 and position, be exposed to outer blind slot. Assembling district 1101 is exposed in groove 71, outside namely pad 113 is also exposed to. In the present embodiment, groove 71 is a rectangle blind slot corresponding with assembling district 1101 shape shown in Fig. 6, position.
Refer to Figure 17; after forming groove 71; also the first welding resisting layer 81 is set on the 3rd conductive circuit layer 611 surface, the 2nd welding resisting layer 82 is set on the 4th conductive circuit layer 621 surface, thus protect the circuit in the 3rd conductive circuit layer 611 and the 4th conductive circuit layer 621 and pad. So, the 6-layer circuit board 10e with groove 71 can be obtained.
It will be appreciated by those skilled in the art that, the first welding resisting layer 81 and the 2nd welding resisting layer 82 can also be formed before forming groove 71. Now, the first welding resisting layer 81 can only in the surface formation of three conductive circuit layer 611 corresponding with pressing district 1102; Or, the first welding resisting layer 81 in the surface formation of whole 3rd conductive circuit layer 611, only when peeling off the first pressing substrate 61 corresponding with assembling district 1101, need to can also remove this part first welding resisting layer 81 corresponding with assembling district 1101 simultaneously.
4th step, refers to Figure 18, installs electronic devices and components 90 in groove 71, and described electronic devices and components 90 are electrically connected with the assembling district 1101 of first line figure 11. Specifically, first providing described electronic devices and components 90, electronic devices and components 90 can be active member or passive element, such as electric capacity, resistance, chip etc. The surface of described electronic devices and components 90 has multiple connection terminal 91, described multiple connection terminal 91 and multiple pads 113 one_to_one corresponding in assembling district 1101. Secondly, connect terminal 91 surface at each and weldering ball projection 92 is set, and electronic devices and components 90 are positioned in groove 81 so that the weldering ball projection 92 on connection terminal 91 surface that each pad 113 is all corresponding with it contacts. Again, make each weldering ball projection 92 melting by reflow and it is electrically connected one after solidification and connects terminal 91 and a pad 113. So, the electrical connection of electronic devices and components 90 with first line figure 11 can be realized, obtain the 6-layer circuit board 10f that structure has filled electronic devices and components 90.
Preferably, it is also possible between described electronic devices and components 90 and 6-layer circuit board 10e, fill encapsulation adhesion material.
As shown in figure 18, it comprises the first welding resisting layer 81, first pressing substrate 61, circuit base plate 10, the 2nd pressing substrate 62, the 2nd welding resisting layer 82 and electronic devices and components 90 to the 6-layer circuit board 10f that above step according to the 2nd embodiment obtains. Together with described first pressing substrate 61, circuit base plate 10 are pressed on successively with the 2nd pressing substrate 62. Described first pressing substrate 61 comprise fit successively the 3rd conductive circuit layer 611, the 3rd film 612, first conductive circuit layer 211 and the first film 212. Described first welding resisting layer 81 is arranged at the 3rd conductive circuit layer 611 surface. Described 2nd pressing substrate 62 comprises the 4th conductive circuit layer 621, the 4th film 622, the 2nd conductive circuit layer 221 and the 2nd film 222 fitted successively. Described 2nd welding resisting layer 82 is arranged at the 4th conductive circuit layer 621 surface. Described circuit base plate 10 as previously mentioned, comprises dielectric base 100 and interior first line figure 11, the 2nd line pattern 12 and at least one conductive hole 101 being embedded in dielectric base 100. 3rd conductive circuit layer 611, first conductive circuit layer 211, first line figure 11, the 2nd line pattern 12, the 2nd conductive circuit layer 221 and the 4th conductive circuit layer 621 are conducted mutually by the blind guide hole 102 of conductive hole 101, first, the 2nd blind guide hole 103, the 3rd blind guide hole 104, the 4th blind guide hole 105, conducting hole 106. Described 6-layer circuit board 10f has the groove 71 running through the first pressing substrate 61, and groove 71 is one and is exposed to outside blind slot. That is, the first welding resisting layer 81 exposes described groove 71. The assembling district 1101 of described first line figure 11 is exposed in groove 71. Electronic devices and components 90 are arranged in groove 71, are installed on multiple pads 113 in assembling district 1101 and outside being exposed to. Electronic devices and components 90 have multiple connection terminal 91, and it realizes being electrically connected with multiple pads 113 of first line figure 11 by multiple weldering ball projection 92.
Owing to first line figure 11 is embedded in dielectric base 100, separated by the material of dielectric base 100 between each pad 113, when therefore assembling electronic devices and components 90 in groove 71, there will not be the phenomenon of Xi Qiao (solderbridge) between each weldering ball projection 92, ensure that the good rate that electronic devices and components 90 are assembled. In addition, owing to first line figure 11 is by etching the formation of rear plating, it is possible to conveniently realize the design on fine rule road; And it is embedded in dielectric base 100 due to first line figure 11, compared to previous technology, it is possible to reduce the thickness of whole 6-layer circuit board 10f, it is achieved lightening, short and smallization of circuit card.
It will be appreciated by those skilled in the art that, it may also be useful to the distortion of the above step of the technical program can make the multilayer circuit board of other numbers of plies of the groove with other quantity. Such as, pressing film and Copper Foil is continued by the upside of the six laminar substrate 10d at Figure 15 or both sides, it is possible to make the multilayer circuit board with more multi-layered number. That is, the number of plies of the first pressing substrate in the multilayer circuit board that the technical program is produced is not limit, it is also possible to comprise three layers and above conductive circuit layer. Certainly, the quantity of multilayer circuit board further groove is not also limit, it is possible to be two, three or more, it is possible to the quantity of the electronic devices and components installed in multilayer circuit board according to need and offer.
In the process of the making multilayer circuit board of the technical program, by first formed in insulated substrate blind slot figure made by the method for coating technology deposits conductive material again have in sunken cord the circuit base plate on road, this circuit base plate at least has the following advantages as the central layer of the multilayer circuit board with groove: on the one hand, the pad exposing circuit base plate in a groove is separated by the material of insulated substrate each other, there will not be tin bridge phenomenon when assembling electronic devices and components, ensure that the good rate of assembling; On the other hand, this circuit base plate can conveniently realize the design on fine rule road, it is also possible to reduces the thickness of whole multilayer circuit board, is conducive to lightening, short and smallization of realizing circuit plate.
It should be appreciated that for the person of ordinary skill of the art, it is possible to make other various corresponding change and distortion according to the technical conceive of the present invention, and all these change the protection domain that all should belong to the claims in the present invention with distortion.
Claims (9)
1. a making method for multilayer circuit board, comprises step:
Thering is provided dielectric base, described dielectric base has the first relative surface and the 2nd surface;
Dielectric base is formed at least one through hole running through the first surface and the 2nd surface, and is formed and be only exposed to the first blind slot figure on the first surface and be only exposed to the 2nd blind slot figure on the 2nd surface;
By coating technology deposits conductive material on a dielectric base, so that electro-conductive material is filled at least one through hole described forms at least one conductive hole, it is filled in the first blind slot figure and forms first line figure, also it is filled in the 2nd blind slot figure and forms the 2nd line pattern, the electro-conductive material protruding from the first surface and the 2nd surface is removed by the step of mill brush or etching, so that described first line figure is embedded in dielectric base and puts down with the first surface is neat, described 2nd line pattern is embedded in dielectric base and puts down with the 2nd surface is neat, described first line figure comprises multiple pad by dielectric base interval, described first line figure has assembling district and around the pressing district assembling district, described first line figure is electrically connected with the 2nd line pattern by least one conductive hole described,
Form the first pressing substrate on the first surface of dielectric base thus obtain multilager base plate, described first pressing substrate comprises the first conductive circuit layer and the first film, described first film is pressed together between the first conductive circuit layer and the first surface, and described first conductive circuit layer is electrically connected with first line figure;
Removing the first pressing substrate corresponding with assembling district, thus form one in multilager base plate and be exposed to outer groove, described assembling district is exposed in described groove; And
Electronic devices and components are installed in a groove, described electronic devices and components are electrically connected with the assembling district of first line figure.
2. the making method of multilayer circuit board as claimed in claim 1, it is characterized in that, after forming first line figure and the 2nd line pattern, before the first surface of dielectric base forms the first pressing substrate, the making method of described multilayer circuit board is also included in the step that surface, assembling district arranges protection film; Remove with assemble this part first pressing substrate corresponding to district while or afterwards, the making method of described multilayer circuit board also comprises the step removing described protection film.
3. the making method of multilayer circuit board as claimed in claim 1, it is characterised in that, form the first pressing substrate on the first surface of dielectric base and comprise step:
First Copper Foil and described first film are provided;
Stacking described first Copper Foil, the first film and dielectric base successively, and the first Copper Foil, the first film and dielectric base described in one step press;
In the first film, at least one first blind guide hole is formed to be electrically connected the first Copper Foil and first line figure by boring and coating technology; And
Described first conductive circuit layer is made by image transfer and chemical etching process selective etch first Copper Foil thus by the first Copper Foil.
4. the making method of multilayer circuit board as claimed in claim 1, it is characterized in that, described first pressing substrate comprises the 3rd conductive circuit layer, the 3rd film, the first conductive circuit layer and the first film fitted successively, described 3rd film is pressed together between the 3rd conductive circuit layer and the first conductive circuit layer, described first film is pressed together between the first conductive circuit layer and the first surface, forms the first pressing substrate on the first surface of dielectric base and comprises step:
First Copper Foil and described first film are provided;
Stacking described first Copper Foil, the first film and dielectric base successively, and the first Copper Foil, the first film and dielectric base described in one step press;
In the first film, at least one first blind guide hole is formed to be electrically connected the first Copper Foil and first line figure by boring and coating technology;
Described first conductive circuit layer is made by image transfer and chemical etching process selective etch first Copper Foil thus by the first Copper Foil;
3rd Copper Foil and described 3rd film are provided;
3rd film is pressed between the 3rd Copper Foil and the first conductive circuit layer;
In the 3rd film, at least one the 3rd blind guide hole is formed to be electrically connected the 3rd Copper Foil and the first conductive circuit layer by boring and coating technology; And
Described 3rd conductive circuit layer is made by image transfer and chemical etching process selective etch the 3rd Copper Foil thus by the 3rd Copper Foil.
5. the making method of multilayer circuit board as claimed in claim 1, it is characterized in that, while the first surface of dielectric base forms the first pressing substrate, also form the 2nd pressing substrate on the 2nd surface of dielectric base, described 2nd pressing substrate comprises the 2nd conductive circuit layer and the 2nd film, described 2nd film is pressed together between the 2nd conductive circuit layer and the 2nd surface, described 2nd conductive circuit layer and the electrical connection of the 2nd line pattern.
6. the making method of multilayer circuit board as claimed in claim 1, it is characterised in that, before forming groove or afterwards, also form welding resisting layer at the first pressing substrate surface.
7. a multilayer circuit board, it comprises the first pressing substrate and the circuit base plate being pressed on together, described first pressing substrate comprises the first conductive circuit layer and the first film, described circuit base plate comprises dielectric base, first line figure, 2nd line pattern and at least one conductive hole, described dielectric base has the first relative surface and the 2nd surface, described first film is between the first conductive circuit layer and the first surface, described first line figure, 2nd line pattern and at least one conductive hole are all embedded in dielectric base, at least one conductive hole described is exposed to the first surface and the 2nd surface, and it is surperficial with first, 2nd surface all flushes, described first line figure is only exposed to the first surface and puts down with the first surface is neat, described first line figure has multiple pad by dielectric base interval, described first line figure comprises assembling district and around the pressing district assembling district, described 2nd line pattern is only exposed to the 2nd surface and puts down with the 2nd surface is neat, described 2nd line pattern is electrically connected with first line figure by least one conductive hole described, described multilayer circuit board also comprises the 2nd pressing substrate, described 2nd pressing substrate comprises the 2nd conductive circuit layer and the 2nd film, described 2nd film is pressed together between the 2nd conductive circuit layer and the 2nd surface, described first conductive circuit layer is electrically connected with first line figure by least one first blind guide hole, described 2nd conductive circuit layer is electrically connected with the 2nd line pattern by least one the 2nd blind guide hole, described first pressing substrate also comprises the 3rd conductive circuit layer and the 3rd film, described 3rd film is pressed together between the 3rd conductive circuit layer and the first conductive circuit layer, described 3rd conductive circuit layer is electrically connected with the first conductive circuit layer by least one the 3rd blind guide hole, described 2nd pressing substrate also comprises the 4th conductive circuit layer and the 4th film, described 4th film is pressed together between the 4th conductive circuit layer and the 2nd conductive circuit layer, described 4th conductive circuit layer is electrically connected with the 2nd conductive circuit layer by least one the 4th blind guide hole, it is that run through the first pressing substrate and be exposed to outer groove that described multilayer circuit board has one, described groove is corresponding with assembling district, described assembling district exposes in a groove, described multilayer circuit board also comprises the first welding resisting layer and the 2nd welding resisting layer, described first welding resisting layer is arranged on the 3rd conductive circuit layer surface and exposes described groove, described 2nd welding resisting layer is arranged on the 4th conductive circuit layer surface.
8. a multilayer circuit board, it comprises the first pressing substrate, circuit base plate and electronic devices and components, together with described first pressing substrate is pressed on circuit base plate, described first pressing substrate comprises the first conductive circuit layer and the first film, described circuit base plate comprises dielectric base, first line figure, 2nd line pattern and at least one conductive hole, described dielectric base has the first relative surface and the 2nd surface, described first film is between the first conductive circuit layer and the first surface, described first line figure, 2nd line pattern and at least one conductive hole are all embedded in dielectric base, at least one conductive hole described is exposed to the first surface and the 2nd surface, and it is surperficial with first, 2nd surface all flushes, described first line figure is only exposed to the first surface and puts down with the first surface is neat, described first line figure has multiple pad by dielectric base interval, described first line figure comprises assembling district and around the pressing district assembling district, described 2nd line pattern is only exposed to the 2nd surface and puts down with the 2nd surface is neat, described 2nd line pattern is electrically connected with first line figure by least one conductive hole described, described multilayer circuit board also comprises the 2nd pressing substrate, described 2nd pressing substrate comprises the 2nd conductive circuit layer and the 2nd film, described 2nd film is pressed together between the 2nd conductive circuit layer and the 2nd surface, described first conductive circuit layer is electrically connected with first line figure by least one first blind guide hole, described 2nd conductive circuit layer is electrically connected with the 2nd line pattern by least one the 2nd blind guide hole, described first pressing substrate also comprises the 3rd conductive circuit layer and the 3rd film, described 3rd film is pressed together between the 3rd conductive circuit layer and the first conductive circuit layer, described 3rd conductive circuit layer is electrically connected with the first conductive circuit layer by least one the 3rd blind guide hole, described 2nd pressing substrate also comprises the 4th conductive circuit layer and the 4th film, described 4th film is pressed together between the 4th conductive circuit layer and the 2nd conductive circuit layer, described 4th conductive circuit layer is electrically connected with the 2nd conductive circuit layer by least one the 4th blind guide hole, it is that run through the first pressing substrate and be exposed to outer groove that described multilayer circuit board has one, described groove is corresponding with assembling district, described assembling district exposes in a groove, described multilayer circuit board also comprises the first welding resisting layer and the 2nd welding resisting layer, described first welding resisting layer is arranged on the 3rd conductive circuit layer surface and exposes described groove, described 2nd welding resisting layer is arranged on the 4th conductive circuit layer surface, described electronic devices and components are placed in described groove and are installed on the assembling district of circuit base plate.
9. multilayer circuit board as claimed in claim 8, it is characterized in that, described assembling district comprises multiple pad, and described electronic devices and components have and multiple one to one with multiple pad are connected terminal, and each is connected terminal and is all electrically connected with a pad by a weldering ball projection.
Priority Applications (2)
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|---|---|---|---|
| CN201210171915.XA CN103458628B (en) | 2012-05-30 | 2012-05-30 | Multilayer circuit board and making method thereof |
| TW101120393A TWI507096B (en) | 2012-05-30 | 2012-06-07 | Multilayer printed circuit board and method for manufacturing same |
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| CN201210171915.XA CN103458628B (en) | 2012-05-30 | 2012-05-30 | Multilayer circuit board and making method thereof |
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| CN105101640B (en) * | 2014-05-22 | 2018-02-23 | 深南电路有限公司 | A kind of processing method of polytetrafluoroethylene (PTFE) step groove circuit board |
| TWI580327B (en) * | 2014-06-30 | 2017-04-21 | 蔡蒔銓 | Printed circuit board and method for fabricating the same, and apparatus for fabricating printed circuit borad |
| CN104159400A (en) * | 2014-08-26 | 2014-11-19 | 安捷利电子科技（苏州）有限公司 | Packaging structure and circuit board of novel embedded components |
| CN106163124A (en) * | 2015-04-02 | 2016-11-23 | 富葵精密组件(深圳)有限公司 | Circuit board manufacturing method |
| JP2017076698A (en) * | 2015-10-15 | 2017-04-20 | 日本特殊陶業株式会社 | Wiring board and manufacturing method of the same |
| CN106231790A (en) * | 2016-07-27 | 2016-12-14 | 上海摩软通讯技术有限公司 | A kind of printed circuit board and manufacture method and mobile terminal |
| TWI699907B (en) * | 2018-01-25 | 2020-07-21 | 致伸科技股份有限公司 | Light source module |
| CN112712764B (en) * | 2019-10-24 | 2022-09-02 | 深圳市百柔新材料技术有限公司 | Method for manufacturing display panel |
| US20220020807A1 (en) * | 2020-07-16 | 2022-01-20 | Canon Kabushiki Kaisha | Intermediate connection member, method for manufacturing intermediate connection member, electronic module, method for manufacturing electronic module, and electronic equipment |
| CN114126224A (en) * | 2020-08-28 | 2022-03-01 | 深南电路股份有限公司 | Circuit board and manufacturing method thereof |
| CN112164326B (en) * | 2020-09-18 | 2021-07-13 | 熊周成 | Display circuit board, manufacturing method thereof and LED display screen |
| CN112165767B (en) * | 2020-10-27 | 2021-12-07 | 惠州市特创电子科技股份有限公司 | Multilayer circuit board and mobile communication device |
| CN112261801A (en) * | 2020-10-27 | 2021-01-22 | 惠州市特创电子科技有限公司 | Manufacturing method of multilayer circuit board and multilayer circuit board |
| WO2022222282A1 (en) * | 2021-04-20 | 2022-10-27 | 梅州市志浩电子科技有限公司 | Method for manufacturing circuit board in which capacitor and resistor are embedded, and circuit board |
| CN118647130A (en) * | 2021-06-30 | 2024-09-13 | 荣耀终端有限公司 | Terminal equipment |
| CN215935150U (en) * | 2021-06-30 | 2022-03-01 | 荣耀终端有限公司 | Terminal device |
| CN116156786A (en) * | 2021-11-23 | 2023-05-23 | 礼鼎半导体科技(深圳)有限公司 | Embedded chip substrate and manufacturing method thereof |
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| TWI507096B (en) | 2015-11-01 |
| TW201349957A (en) | 2013-12-01 |
| CN103458628A (en) | 2013-12-18 |
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