CN103458628A - Multi-layer circuit board and manufacturing method thereof - Google Patents
Multi-layer circuit board and manufacturing method thereof Download PDFInfo
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- CN103458628A CN103458628A CN201210171915XA CN201210171915A CN103458628A CN 103458628 A CN103458628 A CN 103458628A CN 201210171915X A CN201210171915X A CN 201210171915XA CN 201210171915 A CN201210171915 A CN 201210171915A CN 103458628 A CN103458628 A CN 103458628A
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Abstract
The invention provides a manufacturing method of a multi-layer circuit board. The method includes providing an insulation substrate provided with a corresponding first surface and second surface; forming a through hole penetrating the first surface and the second surface on the insulation substrate, a first blind groove only exposing on the first surface and a second blind groove only exposing on the second surface; depositing conductive material on the insulation substrate to form a conductive hole embedded in the insulation substrate, a first circuit pattern, provided with an assembling area and a pressing area, flush with the first surface and a second circuit pattern flush with the second surface; forming a first pressed substrate plate, comprising a first conductive circuit layer and a first film, on the first surface to obtain a multi-layer substrate plate; removing the first pressed substrate plate corresponding to the assembling area, forming an outer-exposing groove in the multi-layer substrate plate, and allowing the assembling area to expose in the groove. The invention further provides a multi-layer circuit board manufactured by the method.
Description
Technical field
The present invention relates to circuit board technology, relate in particular to reeded multilayer circuit board of a kind of tool and preparation method thereof.
Background technology
In information, communication and consumer electronics industry, circuit board is the indispensable basic comprising important documents of all electronic products.Along with electronic product, toward miniaturization, high speed future development, circuit board is also from the past double-sided PCB of single-sided circuit board, multilayer circuit board future development.Multilayer circuit board, especially the multilayer circuit board that buries electronic devices and components in is widely used especially, refer to Takahashi, A. wait the people to be published in IEEE Trans. on Components in 1992, Packaging, the document of and Manufacturing Technology " High density multilayer printed circuit board for HITAC M ~ 880 ".
The multilayer circuit board that inside buries electronic devices and components generally has a groove, with embedding electronic devices and components.Yet, on the one hand, because the area of line design has been dwindled in the existence of groove, make the built-in type circuit board may there is larger thickness; On the other hand, in groove, assembling is easy to occur the phenomenon of assembly failure during electronic devices and components, like this affect yield and the quality of circuit board.
Summary of the invention
Therefore, be necessary to provide a kind of reeded multilayer circuit board of tool with better product quality and preparation method thereof.
Below will a kind of multilayer circuit board and preparation method thereof be described with embodiment.
A kind of manufacture method of multilayer circuit board comprises step: dielectric base is provided, and described dielectric base has relative first surface and second surface, form at least one through hole that runs through first surface and second surface in dielectric base, and form the second blind slot figure that only is exposed to the first blind slot figure of first surface and only is exposed to second surface, by coating technology deposits conductive material on dielectric base, so that being filled in described at least one through hole, electric conducting material forms at least one conductive hole, be filled in the first blind slot figure and form the first line pattern, also be filled in the second blind slot figure and form the second line pattern, described the first line pattern is embedded in dielectric base and flushes with first surface, described the second line pattern is embedded in dielectric base and flushes with second surface, described the first line pattern has the assembling district and reaches around the pressing district that assembles district, described the first line pattern is electrically connected to the second line pattern by described at least one conductive hole, thereby the first surface in dielectric base forms the first solderless substrate acquisition multilager base plate, described the first solderless substrate comprises the first conducting wire layer and the first film, described the first film is pressed together between the first conducting wire layer and first surface, and described the first conducting wire layer is electrically connected to the first line pattern, and remove first solderless substrate corresponding with the assembling district, thereby in multilager base plate the groove of one of formation outside being exposed to, described assembling district is exposed in described groove.
Preferably, in multilager base plate, form one be exposed to outer groove after, also be included in the step of installation electronic devices and components in groove, described electronic devices and components are electrically connected to the assembling district of the first line pattern.
Preferably, described assembling district comprises a plurality of pads, and described electronic devices and components have and a plurality of pads a plurality of splicing ears one to one, and each splicing ear all is electrically connected to a pad by a soldered ball projection.
A kind of multilayer circuit board, it comprises the first solderless substrate and the circuit base plate be pressed on together.Described the first solderless substrate comprises the first conducting wire layer and the first film.Described circuit base plate comprises dielectric base, the first line pattern, the second line pattern and at least one conductive hole.Described dielectric base has relative first surface and second surface, and described the first film is between the first conducting wire layer and first surface.Described the first line pattern, the second line pattern and at least one conductive hole all are embedded in dielectric base.Described at least one conductive hole is exposed to first surface and second surface, and all flushes with first surface, second surface.Described the first line pattern only is exposed to first surface and flushes with first surface, and described the first circuit graphics package is drawn together the assembling district and reached around the pressing district that assembles district.Described the second line pattern only is exposed to second surface and flushes with second surface, and described the second line pattern is electrically connected to the first line pattern by described at least one conductive hole.Described multilayer circuit board have one that run through the first solderless substrate and be exposed to outer groove, described groove is with to assemble district corresponding, described assembling district is exposed in groove.
A kind of multilayer circuit board, it comprises the first solderless substrate, circuit base plate and electronic devices and components.Described the first solderless substrate is with together with circuit base plate is pressed on.Described the first solderless substrate comprises the first conducting wire layer and the first film.Described circuit base plate comprises dielectric base, the first line pattern, the second line pattern and at least one conductive hole.Described dielectric base has relative first surface and second surface, and described the first film is between the first conducting wire layer and first surface.Described the first line pattern, the second line pattern and at least one conductive hole all are embedded in dielectric base.Described at least one conductive hole is exposed to first surface and second surface, and all flushes with first surface, second surface.Described the first line pattern only is exposed to first surface and flushes with first surface, and described the first circuit graphics package is drawn together the assembling district and reached around the pressing district that assembles district.Described the second line pattern only is exposed to second surface and flushes with second surface, and described the second line pattern is electrically connected to the first line pattern by described at least one conductive hole.Described multilayer circuit board have one that run through the first solderless substrate and be exposed to outer groove, described groove is with to assemble district corresponding, described assembling district is exposed in groove, described electronic devices and components are placed in described groove and are installed on the assembling district of circuit base plate.
In the technical program, made in having again the circuit base plate on the road of sunkening cord by the method for coating technology deposits conductive material by first in insulated substrate, forming the blind slot figure, this circuit base plate at least has the following advantages as the central layer of the reeded multilayer circuit board of tool: on the one hand, the material that the pad that is exposed to the circuit base plate in groove is insulated substrate each other separates, not there will be tin bridge phenomenon when the assembling electronic devices and components, guaranteed the assembling yield; On the other hand, this circuit base plate can be realized the design on fine rule road easily, can also reduce the thickness of whole multilayer circuit board, is conducive to realize lightening, short and smallization of circuit board.
The accompanying drawing explanation
The schematic diagram of the double-sided copper-clad substrate that Fig. 1 provides for the technical program the first embodiment.
The schematic diagram of the dielectric base that Fig. 2 provides for the technical program the first embodiment.
Schematic diagram after the dielectric base that Fig. 3 is use laser ablation Fig. 2.
Fig. 4 is the schematic diagram after deposits conductive material on the dielectric base of Fig. 3.
The schematic diagram of the circuit base plate that Fig. 5 provides for the technical program the first embodiment.
The schematic top plan view that Fig. 6 is Fig. 5.
Fig. 7 for arranging the schematic diagram of protection film on the circuit base plate of Fig. 5.
Fig. 8 is the schematic diagram after the both sides up and down of the circuit base plate of Fig. 7 difference pressing film and Copper Foil.
Fig. 9 is the schematic diagram after the formation blind via hole in the film of pressing.
Figure 10 is for making the Copper Foil of pressing in the schematic diagram of four laminar substrates that the conducting wire layer obtains afterwards.
Figure 11 forms the schematic diagram of a groove in four laminar substrates of Figure 10.
Figure 12 is the schematic diagram after the assembling electronic devices and components in the groove of four laminar substrates of Figure 11.
Figure 13 is the schematic diagram after the both sides up and down of four laminar substrates of Figure 10 difference pressing film and Copper Foil.
Figure 14 is the schematic diagram after the formation blind via hole in the film of pressing.
Figure 15 is for making the Copper Foil of pressing in the schematic diagram of six laminar substrates that the conducting wire layer obtains afterwards.
Figure 16 forms the schematic diagram of a groove in six laminar substrates.
The schematic diagram that Figure 17 is the 6-layer circuit board that obtains after the six laminar substrate both sides of Figure 16 form welding resisting layer respectively.
Figure 18 is the schematic diagram after the assembling electronic devices and components in the groove of the 6-layer circuit board of Figure 17.
The main element symbol description
| |
100 |
| |
111 |
| |
112 |
| The double-sided copper- |
120 |
| The |
121 |
| The |
122 |
| Through |
130 |
| The first blind slot figure | 131 |
| The second blind slot figure | 132 |
| Electric conducting |
14 |
| |
101 |
| The |
11 |
| The |
12 |
| |
10 |
| The assembling |
1101 |
| The |
1102 |
| |
113 |
| |
114 |
| The |
15 |
| The first |
21、61 |
| The second |
22、62 |
| The first conducting |
211 |
| The |
212 |
| The second conducting |
221 |
| The |
222 |
| The first Copper Foil | 210 |
| The |
220 |
| The first blind via |
102 |
| The second blind via |
103 |
| Four |
10a |
| The first opening | 213 |
| |
31、71 |
| The first |
41、81 |
| The second |
42、82 |
| Four- |
10b、10c |
| Electronic devices and |
50、90 |
| |
51、91 |
| The |
52、92 |
| The |
612 |
| The |
610 |
| The |
622 |
| The |
620 |
| The 3rd blind via |
104 |
| The 4th blind via |
105 |
| |
106 |
| The 3rd conducting |
611 |
| The 4th conducting |
621 |
| Six |
10d |
| The second opening | 613 |
| 6- |
10e、10f |
Following embodiment further illustrates the present invention in connection with above-mentioned accompanying drawing.
Embodiment
Below in conjunction with accompanying drawing and a plurality of embodiment, multilayer circuit board that the technical program is provided and preparation method thereof is described in further detail.
The manufacture method of the multilayer circuit board that the technical program the first embodiment provides comprises step:
The first step, see also Fig. 1 and Fig. 2, and dielectric base 100 is provided, and described dielectric base 100 has relative first surface 111 and second surface 112.
Described dielectric base 100 can be the insulation sheet material of buying, and the copper-clad base plate that also can buy by etching is made.In the present embodiment, described dielectric base 100 forms as follows: at first, double-sided copper-clad substrate 120 is provided, and described double-sided copper-clad substrate 120 comprises described dielectric base 100 and is fitted in upside Copper Foil 121 and the downside Copper Foil 122 of dielectric base 100 both sides; Secondly, with chemical etching liquor etching double-sided copper-clad substrate 120, thereby remove upside Copper Foil 121 and downside Copper Foil 122, formed described dielectric base 100.The thickness of described dielectric base 100 is the 40-80 micron.
Second step, refer to Fig. 3, use laser ablation dielectric base 100, form at least one through hole 130 that runs through first surface 111 and second surface 112 in dielectric base 100, and form the second blind slot figure 132 that only is exposed to the first blind slot figure 131 of first surface 111 and only is exposed to second surface 112.Described the first blind slot figure 131 is for forming a line pattern, it comprises a plurality of the first blind slots, described a plurality of the first blind slot has the essentially identical degree of depth and different shapes, and it comprises a plurality of blind slots corresponding with the circuit shape and a plurality of blind slot corresponding with bond pad shapes.The second blind slot figure 132 is also for forming a line pattern, it comprises a plurality of the second blind slots, described a plurality of the second blind slot has the essentially identical degree of depth and different shapes, also comprises a plurality of blind slots corresponding with the circuit shape and a plurality of blind slot corresponding with bond pad shapes.Preferably, the degree of depth of the first blind slot equals the degree of depth of the second blind slot.Generally speaking, the degree of depth of the first blind slot, the second blind slot is the 15-25 micron.
The 3rd step, refer to Fig. 4, by coating technology deposits conductive material 14 on dielectric base 100 so that electric conducting material 14 is deposited at least one through hole 130, in the first blind slot figure 131 and in the second blind slot figure 132.Described electric conducting material 14 can be copper, can be also the materials such as carbon black, nickel, silver, gold, can also be the combination of above material.For example, can pass through chemical-copper-plating process or blackening craft in dielectric base surface deposition chemical copper layer or carbon black layer, then by copper plating process at chemical copper layer or carbon black layer surface deposition copper electroplating layer, like this can to form be the electric conducting material 14 of copper or the electric conducting material 14 be comprised of carbon black and copper entirely.
It will be understood by those skilled in the art that electric conducting material 14 also can be deposited on first surface 111 and second surface 112 if do not cover first surface 111 and second surface 112 before deposits conductive material 14.In addition; in order to ensure enough electric conducting materials 14 on deposition at least one through hole 130, in the first blind slot figure 131 and in the second blind slot figure 132; usually can slightly extend the plating time, and make be deposited at least one through hole 130, in the first blind slot figure 131 and the electric conducting material 14 in the second blind slot figure 132 protrude from first surface 111 and second surface 112.
Refer to Fig. 5, also need after deposits conductive material 14 to remove through polish-brush or etched step the electric conducting material 14 that protrudes from first surface 111 and second surface 112.That is to say, the electric conducting material 14 that is deposited on first surface 111 and second surface 112 will be removed, and make that the electric conducting material 14 be deposited at least one through hole 130 flushes with first surface 111 and second surface 112 respectively, the electric conducting material 14 in the first blind slot figure 131 flushes with first surface 111, the electric conducting material 14 in the second blind slot figure 132 flushes with second surface 112 simultaneously.Thereby electric conducting material 14 is filled in described at least one through hole 130 and forms at least one conductive hole 101, is filled in the first blind slot figure 131 and forms the first line pattern 11, is filled in the second blind slot figure 132 and forms the second line pattern 12.Described the first line pattern 11 is embedded in dielectric base 100 and flushes with first surface 111, and described the second line pattern 12 is embedded in dielectric base 100 and flushes with second surface 112.Described the first line pattern 11 and the second line pattern 12 include many conducting wires and a plurality of pad, conducting wire and pad in described the first line pattern 11 all flush with first surface 111, and conducting wire and pad in described the second line pattern 12 all flush with second surface 112.Dielectric base 100, the first line pattern 11 and second line pattern 12 of so, combining closely can form in having the circuit base plate 10 of the road figure of sunkening cord.
Certainly, it will be appreciated by those skilled in the art that, if covered first surface 111 and second surface 112 before deposits conductive material 14, and strictly when plating control plating condition and plating time, so that the electric conducting material 14 be deposited at least one through hole 130 flushes with first surface 111 and second surface 112 respectively just, electric conducting material 14 in the first blind slot figure 131 flushes with first surface 111, electric conducting material 14 in the second blind slot figure 132 flushes with second surface 112, follow-up the needs removes by polish-brush or etched step the electric conducting material 14 that protrudes from first surface 111 and second surface 112, can obtain circuit base plate 10.
In the present embodiment, define described the first line pattern 11 and comprise assembling district 1101 and assemble pressing district 1102 on every side, district 1101 around being connected to, as shown in Figure 6.In the present embodiment, assembling district 1101 is rectangle, and it at least has a plurality of pads 113, and described pressing district 1102 is around described assembling district 1101, and it at least has many circuits 114.It will be appreciated by those skilled in the art that, pad in the first line pattern 11 and quantity and the shape of circuit are determined according to the circuit design of circuit board, generally there is more pad and circuit, in Fig. 5 and Fig. 6 of the present embodiment, only schematically draw a circuit 114 in pressing district 1102, schematically draw two pads 113 in assembling district 1101.
The 4th step, refer to Fig. 7, and protection film 15 is set in the assembling district 1101 of described the first line pattern 11, with the pad 113 in protection assembling district 1101.Described protection film 15 can be release film.The cross-sectional area of protection film 15 can equal or be slightly less than the cross-sectional area in assembling district 1101, only needs the circuit and the pad 113 that fully cover in assembling district 1101 to get final product.In the present embodiment, the cross-sectional area of protection film 15 is slightly less than the cross-sectional area in assembling district 1101.
The 5th step, refer to Fig. 8 to Figure 10, close and form the first solderless substrate 21 in first surface 111 1 side pressures of circuit base plate 10, close and form the second solderless substrate 22 in second surface 112 1 side pressures, and making the first solderless substrate 21 and the first line pattern 11 conduct, the second solderless substrate 22 and the second line pattern 12 conduct.
In the present embodiment, the first solderless substrate 21 is single layer substrate, and it comprises that the first conducting wire layer 211 and the first film 212, the second solderless substrates 22 are also single layer substrate, and it comprises the second conducting wire layer 221 and the second film 222.Particularly, pressing the first solderless substrate 21 and the second solderless substrate 22 can be realized by following technique: at first the first film 212, the first Copper Foil 210, the second film 222 and the second Copper Foil 220 are provided; By the first film 212, be placed on first surface 111 and covering protection film 15, the first Copper Foil 210 is placed on to the first film 212 upsides, and also the second film 222 is arranged on to second surface 112, the second Copper Foil 220 is placed on to the second film 222 downsides, that is, the first Copper Foil 210, the first film 212, circuit base plate 10, the second film 222 and the second Copper Foil 220 are stacked gradually; Then stacking the first Copper Foil 210, the first film 212, circuit base plate 10, the second film 222 and the second Copper Foil 220 are put into to pressing machine, described the first Copper Foil 210 of one step press, the first film 212, circuit base plate 10, the second film 222 and the second Copper Foil 220, form four lamination plywood, as shown in Figure 8.Secondly form at least one first blind hole and at least one second blind hole by the laser drill technology in four lamination plywood, described at least one first blind hole only runs through the first Copper Foil 210 and first film 212 of the first solderless substrate 21, and described at least one second blind hole only runs through the second Copper Foil 220 and second film 222 of the second solderless substrate 22; Then by chemical-copper-plating process and copper plating process copper layer in described at least one first blind hole and at least one second blind hole, thereby described at least one first blind hole is made to the first blind via hole 102, the second blind hole is made to the second blind via hole 103, as shown in Figure 9.Again, by image transfer and chemical etching process optionally etching the first Copper Foil 210 and the second Copper Foil 220, thereby the first Copper Foil 210 is made to the first conducting wire layer 211, the second Copper Foil 220 is made to the second conducting wire layer 221, the first conducting wire layer 211 conducts by least one first blind via hole 102 and the first line pattern 11, the second conducting wire layer 221 conducts by least one second blind via hole 103 and the second line pattern 12, so can obtain four laminar substrate 10a as shown in figure 10.All have many conducting wires and a plurality of pad in described the first conducting wire layer 211 and the second conducting wire layer 221, concrete circuit design can be determined on demand.
Preferably, when selective etch the first Copper Foil 210, part first Copper Foil 210 corresponding with the border in assembling district 1101 removed in etching, forms first opening 213 corresponding with the border in assembling district 1101 in the first conducting wire floor 211.
The 6th step; refer to Figure 11; remove part first solderless substrate 21 corresponding with assembling district 1101, only run through groove 31 the first solderless substrate 21 and corresponding with assembling district 1101 thereby form one in four laminar substrate 10a, and remove the protection film 15 that is fitted in assembling 1101 surfaces, district.
Particularly, can form as follows groove 31: at first use laser to cut the first solderless substrate 21 along the border in assembling district 1101, cut the first conducting wire layer 211 and the first film 212.After cutting, this part first solderless substrate 21 of assembling 1101 tops, district is separated from each other with first solderless substrate 21 in other zones, that is to say, the first solderless substrate 21 of assembling 1101 tops, district is separated from each other with the first solderless substrate 21 of 1102 tops, pressing district.So, peel off this part first solderless substrate 21 corresponding with assembling district 1101 and can form groove 31.In the present embodiment, existence due to the first opening 213 in the first conducting wire layer 211, directly with laser, from the first opening 213, along the border in assembling district 1101, cut the first film 212, then directly peel off this part first film 212 of assembling 1101 tops, district and can remove this part first solderless substrate 21 corresponding with assembling district 1101, thereby form groove 31.It will be appreciated by those skilled in the art that, when the bonding force between protection film 15 and the first film 212 better and when poor with the bonding force of assembling 1101 surfaces, district, when the bonding force between protection film 15 and the first film 212 is better than protecting the bonding force between film 15 and assembling 1101 surfaces, district, when peeling off the first film 212, self assembly district 1101 sur-face peelings are protected films 15 simultaneously; When the bonding force between protection film 15 and the first film 212 poor and when better with the bonding force of assembling 1101 surfaces, district; during in the bonding force between protection film 15 and assembling 1101 surfaces, district, can after peeling off the first film 212, protect films 15 from assembling district's 1101 sur-face peelings again when the poor adhesion between protection film 15 and the first film 212.Now, after peeling off the first film 212, protection film 15 is exposed in groove 31, and the 1101 sur-face peeling protection films 15 from the assembling district, expose the pad 113 of assembling district 1101 with comparalive ease.
Described groove 31 has shape and the position corresponding with assembling district 1101, and in the present embodiment, shape and the position in the shape of groove 31 assembling district 1101 as shown in Figure 6 are corresponding, that is, groove 31 is for being positioned at the rectangle blind slot at four laminar substrate 10a middle parts.
Before forming groove 31 or after forming groove 31; can also the first welding resisting layer 41 be set on the first conducting wire layer 211 surface; on the second conducting wire layer 221 surface, the second welding resisting layer 42 is set, thereby protects circuit and pad in the first conducting wire layer 211 and the second conducting wire layer 221.So, can obtain the four-layer circuit board 10b with groove 31.
The 7th step, refer to Figure 12, and electronic devices and components 50 are installed in groove 31, and described electronic devices and components 50 are electrically connected to the assembling district 1101 of the first line pattern 11.Particularly, at first provide described electronic devices and components 50, it can be active member or passive device, for example chip.The surface of described electronic devices and components 50 has a plurality of splicing ears 51, and described a plurality of splicing ears 51 are corresponding one by one with a plurality of pads 113 in assembling district 1101.Secondly, on each splicing ear 51 surface, soldered ball projection 52 is set, and electronic devices and components 50 are positioned in groove 31, make each pad 113 all contact with the soldered ball projection 52 on splicing ear 51 surfaces corresponding with it.Again, make each soldered ball projection 52 melting by reflow and solidify a rear splicing ear 51 and the pad 113 of being electrically connected to.So, can realize being electrically connected to of electronic devices and components 50 and the first line pattern 11, obtain the four-layer circuit board 10c that structure has filled electronic devices and components 50.
Preferably, can also between described electronic devices and components 50 and groove 31, fill the encapsulation adhesion material, with better fixing electronic devices and components 50.
As shown in figure 12, it comprises the first welding resisting layer 41, the first solderless substrate 21, circuit base plate 10, the second solderless substrate 22, the second welding resisting layer 42 and electronic devices and components 50 to the four-layer circuit board 10c made according to the above step of the first embodiment.Described the first solderless substrate 21, circuit base plate 10 and the second solderless substrate 22 pressing successively.Described the first solderless substrate 21 comprises the first conducting wire layer 211 and the first film 212.The first welding resisting layer 41 is arranged at the first solderless substrate 21 surfaces, and covers the first conducting wire layer 211.Described the second solderless substrate 22 comprises the second conducting wire layer 221 and the second film 222.The second welding resisting layer 42 is arranged at the second solderless substrate 22 surfaces, and covers the second conducting wire layer 221 surface.Described circuit base plate 10 comprise dielectric base 100 and in be embedded in the first line pattern 11, the second line pattern 12 and at least one conductive hole 101 in dielectric base 100.Wherein, the first line pattern 11 only is exposed to first surface 111 and flushes with first surface 111, and the second line pattern 12 only is exposed to second surface 112 and flushes with second surface 112.Conductive hole 101 is exposed to first surface 111, second surface 112, and all flushes with first surface 111, second surface 112, for being electrically connected to the first line pattern 11 and the second line pattern 12.The first conducting wire layer 211, the first line pattern 11, the second line pattern 12 and the second conducting wire layer 221 conduct by conductive hole 101, the first blind via hole 102 and the second blind via hole 103.Described four-layer circuit board 10c has the groove 31 that runs through the first solderless substrate 21 and the first welding resisting layer 41, and groove 31 is one and is exposed to outside blind slot.The assembling district 1101 of the first line pattern 11 is exposed in groove 31.Electronic devices and components 50 are arranged in groove 31, be installed on the assembling district 1101 a plurality of pads 113 on and be exposed to outside.Electronic devices and components 50 have a plurality of splicing ears 51, and it realizes being electrically connected to the first line pattern 11 by a plurality of soldered ball projections 52.
Because the first line pattern 11 is embedded in dielectric base 100, the material that is insulated substrate 100 between each pad 113 separates, therefore when the interior assembling electronic devices and components 50 of groove 31, the phenomenon that not there will be Xi Qiao (solder bridge) between each soldered ball projection 52, guaranteed the yield that electronic devices and components 50 are assembled.
In addition, because the first line pattern 11 is to form by plating after etching, can realize easily the design on fine rule road; And, because the first line pattern 11 is embedded in dielectric base 100, compared to prior art, can reduce the thickness of whole four-layer circuit board 10c, realize lightening, short and smallization of circuit board.
It will be understood by those skilled in the art that the step in the method for making multilayer circuit board of the first embodiment not is essential features.For example, in the 3rd step, can be only at circuit base plate 10 upside pressing the first solderless substrates 21, and online base board 10 downside pressing the second solderless substrates 22 when different so, through after subsequent step, can be made three layer circuit boards with a groove.Equally, the element in the four-layer circuit board 10c that the first embodiment makes also not is essential features, for example, and the first welding resisting layer 41 and the second welding resisting layer 42.In addition, the first conducting wire layer 211, the first line pattern 11, the second line pattern 12 and the second conducting wire layer 221 are not limited to realize conducting by conductive hole 101, the first blind via hole 102 and the second blind via hole 103, also can not form the first blind via hole 102 and the second blind via hole 103, and form the via that at least one runs through four-layer circuit board 10c, to realize each layer, conduct.
Certainly, it will be understood by those skilled in the art that the technical program can be made the multilayer circuit board of any number of plies with any amount groove except making has three layer circuit boards or four-layer circuit board of a groove.For example, in the 6th step, also can form more than one groove, for example two or three grooves, so can be made into and have two multilayer circuit boards with upper groove.Again for example, in four laminar substrate 10a both sides shown in Figure 10, continue addition film and Copper Foil, can be made into the multilayer circuit board more than four layers.Below, the 6-layer circuit board that the making of take has a groove describes as example.
The manufacture method of the multilayer circuit board that the technical program the second embodiment provides comprises step:
The first step, refer to Fig. 7, provides in the first embodiment being provided with that the 4th step obtains to protect film 15 circuit base plate 10 afterwards.
Second step, refer to Fig. 8 to Figure 10 and Figure 13 to Figure 15, close and form the first solderless substrate 61 in first surface 111 1 side pressures of dielectric base 100, close and form the second solderless substrate 62 in second surface 112 1 side pressures, and making the first solderless substrate 61 and the first line pattern 11 conduct, the second solderless substrate 62 and the second line pattern 12 conduct.
In the present embodiment, the first solderless substrate 61 is multilager base plate, it comprises the first film 212, the first conducting wire layer 211, the 3rd film 612 and the 3rd conducting wire layer 611, the second solderless substrate 62 is also multilager base plate, and it comprises the second film 222, the second conducting wire layer 221, the 4th film 622 and the 4th conducting wire layer 621.Particularly, forming the first solderless substrate 61 and the second solderless substrate 62 can realize by following technique: at first, refer to Fig. 8 to Figure 10, by the concrete steps in the 5th step in the first embodiment, close and form the first film 212 and the first conducting wire layer 211 in first surface 111 1 side pressures of circuit base plate 10, close and form the second film 222 and the second conducting wire layer 221 in second surface 112 1 side pressures of circuit base plate 10, the first conducting wire layer 211 conducts by least one first blind via hole 102 and the first line pattern 11, the second conducting wire layer 221 conducts by least one second blind via hole 103 and the second line pattern 12, so can obtain four laminar substrate 10a as shown in figure 10.Secondly, refer to Figure 13, the 3rd film 612, the 3rd Copper Foil 610, the 4th film 622 and the 4th Copper Foil 620 are provided; The 3rd film 612 is placed on to the first conducting wire layer 211 top, the 3rd Copper Foil 610 is placed on the 3rd film 612, and also the 4th film 622 is arranged on to the second conducting wire layer 221 below, the 4th Copper Foil 620 is placed on to the 4th film 622 downsides, is about to the 3rd Copper Foil 610, the 3rd film 612, four laminar substrate 10a, the 4th film 622 and the 4th Copper Foil 620 and stacks gradually; Then stacking the 3rd Copper Foil 610, the 3rd film 612, four laminar substrate 10a, the 4th film 622 and the 4th Copper Foil 620 are put into to pressing machine, described the 3rd Copper Foil 610 of one step press, the 3rd film 612, four laminar substrate 10a, the 4th film 622 and the 4th Copper Foil 620, form six lamination plywood, as shown in figure 13.Again, form at least one the 3rd blind hole, at least one the 4th blind hole and at least one through hole in six lamination plywood by drilling technique, described at least one the 3rd blind hole only runs through the 3rd Copper Foil 610 and the 3rd film 612, described at least one the 4th blind hole only runs through the 4th Copper Foil 620 and the 4th film 622, and described at least one through hole runs through the 3rd Copper Foil 610, the 3rd film 612, four laminar substrate 10a, the 4th film 622 and the 4th Copper Foil 620; Then by chemical-copper-plating process and copper plating process in described at least one the 3rd blind hole, copper layer at least one the 4th blind hole and at least one through hole, thereby described at least one the 3rd blind hole is made to the 3rd blind via hole 104, the 4th blind hole is made to the 4th blind via hole 105, at least one through hole is made to via 106, as shown in figure 14.Finally, by image transfer and chemical etching process optionally etching the 3rd Copper Foil 610 and the 4th Copper Foil 620, thereby the 3rd Copper Foil 610 is made to the 3rd conducting wire layer 611, the 4th Copper Foil 620 is made to the 4th conducting wire layer 621, the 3rd conducting wire layer 611 conducts by least one the 3rd blind via hole 104 and the first conducting wire layer 211, the 4th conducting wire layer 621 conducts by least one the 4th blind via hole 105 and the second conducting wire layer 221, at least one via 106 can conduct the 3rd conducting wire layer 611, the first conducting wire layer 211, the first line pattern 11, the second line pattern 12, the second conducting wire layer 221 and the 4th conducting wire layer 621, so can obtain six laminar substrate 10d as shown in figure 15.All have many conducting wires and a plurality of pad in described the 3rd conducting wire layer 611 and the 4th conducting wire layer 621, concrete circuit design can be determined on demand.
Preferably, when selective etch the 3rd Copper Foil 610, part three Copper Foil 610 corresponding with the border in assembling district 1101 removed in etching, form second opening 613 corresponding with the border in assembling district 1101 in the 3rd conducting wire floor 611, described the second opening 613 and the first opening 213 are mutually corresponding.
The 3rd step; refer to Figure 16; remove part first solderless substrate 61 corresponding with assembling district 1101, only run through groove 71 the first solderless substrate 61 and corresponding with assembling district 1101 thereby form one in six laminar substrate 10d, and remove the protection film 15 that is fitted in assembling 1101 surfaces, district.
Particularly, can form as follows groove 71: at first use laser to cut the first solderless substrate 61 along the border in assembling district 1101, cut the 3rd conducting wire layer 611, the 3rd film 612, the first conducting wire layer 211 and the first film 212.After cutting, this part first solderless substrate 61 of assembling 1101 tops, district is separated from each other with first solderless substrate 61 in other zones, that is to say, the first solderless substrate 61 of assembling 1101 tops, district is separated from each other with the first solderless substrate 61 of 1102 tops, pressing district.So, peel off this part first solderless substrate 61 of assembling 1101 tops, district and can form groove 71.In the present embodiment, existence due to the first opening 213 in the second opening 613 in the 3rd conducting wire layer 611 and the first conducting wire layer 211, and because the second opening 613 and the first opening 213 are all corresponding with the border in assembling district 1101, therefore, after directly with laser, from the second opening 613, cutting the 3rd film 612 and the first film 212, this part can be positioned to the first solderless substrate 61 of assembling 1101 tops, district from circuit base plate 10 sur-face peelings.
It will be appreciated by those skilled in the art that, when the bonding force between protection film 15 and the first film 212 better and when poor with the bonding force of assembling 1101 surfaces, district, when the bonding force between protection film 15 and the first film 212 is better than protecting the bonding force between film 15 and assembling 1101 surfaces, district, when peeling off the first film 212, self assembly district 1101 sur-face peelings are protected films 15 simultaneously; When the bonding force between protection film 15 and the first film 212 poor and when better with the bonding force of assembling 1101 surfaces, district; during in the bonding force between protection film 15 and assembling 1101 surfaces, district, can after peeling off the first film 212, protect films 15 from assembling district's 1101 sur-face peelings again when the poor adhesion between protection film 15 and the first film 212.Now, after peeling off the first film 212, protection film 15 is exposed in groove 71, and the 1101 sur-face peeling protection films 15 from the assembling district, expose the pad 113 of assembling district 1101 with comparalive ease.
After peeling off this part first solderless substrate 61 corresponding with assembling district 1101 and peeling off protection film 15, can form groove 71.Groove 71 be one corresponding with the assembling shape in district 1101 and position, be exposed to outer blind slot.Assembling district 1101 is exposed in groove 71, outside pad 113 also is exposed to.In the present embodiment, groove 71 is a rectangle blind slot corresponding with assembling district 1101 shapes, position shown in Fig. 6.
Refer to Figure 17; after forming groove 71; also on the 3rd conducting wire layer 611 surface, the first welding resisting layer 81 is set, on the 4th conducting wire layer 621 surface, the second welding resisting layer 82 is set, thereby protect circuit and pad in the 3rd conducting wire layer 611 and the 4th conducting wire layer 621.So, can obtain the 6-layer circuit board 10e with groove 71.
It will be understood by those skilled in the art that the first welding resisting layer 81 and the second welding resisting layer 82 also can form before forming groove 71.Now, the first welding resisting layer 81 can only form on the surface of the 3rd conducting wire floor 611 corresponding with pressing district 1102; Perhaps, the first welding resisting layer 81 also can form on the surface of whole the 3rd conducting wire layer 611, only need, peeling off when assembling the first solderless substrate 61 corresponding to district 1101, remove this part first welding resisting layer 81 corresponding with assembling district 1101 simultaneously and get final product.
The 4th step, refer to Figure 18, and electronic devices and components 90 are installed in groove 71, and described electronic devices and components 90 are electrically connected to the assembling district 1101 of the first line pattern 11.Particularly, at first provide described electronic devices and components 90, electronic devices and components 90 can be active member or passive device, such as electric capacity, resistance, chip etc.The surface of described electronic devices and components 90 has a plurality of splicing ears 91, and described a plurality of splicing ears 91 are corresponding one by one with a plurality of pads 113 in assembling district 1101.Secondly, on each splicing ear 91 surface, soldered ball projection 92 is set, and electronic devices and components 90 are positioned in groove 81, make each pad 113 all contact with the soldered ball projection 92 on splicing ear 91 surfaces corresponding with it.Again, make each soldered ball projection 92 melting by reflow and solidify a rear splicing ear 91 and the pad 113 of being electrically connected to.So, can realize being electrically connected to of electronic devices and components 90 and the first line pattern 11, obtain the 6-layer circuit board 10f that structure has filled electronic devices and components 90.
Preferably, can also between described electronic devices and components 90 and 6-layer circuit board 10e, fill the encapsulation adhesion material.
As shown in figure 18, it comprises the first welding resisting layer 81, the first solderless substrate 61, circuit base plate 10, the second solderless substrate 62, the second welding resisting layer 82 and electronic devices and components 90 to the 6-layer circuit board 10f made according to the above step of the second embodiment.Described the first solderless substrate 61, circuit base plate 10 and together with the second solderless substrate 62 is pressed on successively.Described the first solderless substrate 61 comprises the 3rd conducting wire layer 611, the 3rd film 612, the first conducting wire layer 211 and first film 212 of laminating successively.Described the first welding resisting layer 81 is arranged at the 3rd conducting wire layer 611 surface.Described the second solderless substrate 62 comprises the 4th conducting wire layer 621, the 4th film 622, the second conducting wire layer 221 and second film 222 of laminating successively.Described the second welding resisting layer 82 is arranged at the 4th conducting wire layer 621 surface.Described circuit base plate 10 as previously mentioned, comprise dielectric base 100 and in be embedded in the first line pattern 11, the second line pattern 12 and at least one conductive hole 101 in dielectric base 100.The 3rd conducting wire layer 611, the first conducting wire layer 211, the first line pattern 11, the second line pattern 12, the second conducting wire layer 221 and the 4th conducting wire layer 621 conduct mutually by conductive hole 101, the first blind via hole 102, the second blind via hole 103, the 3rd blind via hole 104, the 4th blind via hole 105, via 106.Described 6-layer circuit board 10f has the groove 71 that runs through the first solderless substrate 61, and groove 71 is one and is exposed to outside blind slot.That is, the first welding resisting layer 81 exposes described groove 71.The assembling district 1101 of described the first line pattern 11 is exposed in groove 71.Electronic devices and components 90 are arranged in groove 71, be installed on the assembling district 1101 a plurality of pads 113 on and be exposed to outside.Electronic devices and components 90 have a plurality of splicing ears 91, and it realizes being electrically connected to a plurality of pads 113 of the first line pattern 11 by a plurality of soldered ball projections 92.
Because the first line pattern 11 is embedded in dielectric base 100, the material that is insulated substrate 100 between each pad 113 separates, therefore when the interior assembling electronic devices and components 90 of groove 71, the phenomenon that not there will be Xi Qiao (solder bridge) between each soldered ball projection 92, guaranteed the yield that electronic devices and components 90 are assembled.In addition, because the first line pattern 11 is to form by plating after etching, can realize easily the design on fine rule road; And, because the first line pattern 11 is embedded in dielectric base 100, compared to prior art, can reduce the thickness of whole 6-layer circuit board 10f, realize lightening, short and smallization of circuit board.
The distortion that it will be understood by those skilled in the art that the above step of using the technical program can be made the multilayer circuit board of other numbers of plies of the groove with other quantity.For example, by upside or the both sides of the six laminar substrate 10d at Figure 15, continue pressing film and Copper Foil, can make the multilayer circuit board with more multi-layered number.That is to say, the number of plies of the first solderless substrate in the multilayer circuit board that the technical program is produced is not limit, and can also comprise three layers and above conducting wire layer.Certainly, the quantity of multilayer circuit board further groove is not limit yet, and can be two, three or more, the quantity of the electronic devices and components that can install in multilayer circuit board according to need and being offered.
In the process of the making multilayer circuit board of the technical program, made in having again the circuit base plate on the road of sunkening cord by the method for coating technology deposits conductive material by first in insulated substrate, forming the blind slot figure, this circuit base plate at least has the following advantages as the central layer of the reeded multilayer circuit board of tool: on the one hand, the material that the pad that is exposed to the circuit base plate in groove is insulated substrate each other separates, not there will be tin bridge phenomenon when the assembling electronic devices and components, guaranteed the assembling yield; On the other hand, this circuit base plate can be realized the design on fine rule road easily, can also reduce the thickness of whole multilayer circuit board, is conducive to realize lightening, short and smallization of circuit board.
Be understandable that, for the person of ordinary skill of the art, can make other various corresponding changes and distortion by technical conceive according to the present invention, and all these change and distortion all should belong to the protection range of the claims in the present invention.
Claims (15)
1. the manufacture method of a multilayer circuit board comprises step:
Dielectric base is provided, and described dielectric base has relative first surface and second surface;
Form at least one through hole that runs through first surface and second surface in dielectric base, and form the second blind slot figure that only is exposed to the first blind slot figure of first surface and only is exposed to second surface;
By coating technology deposits conductive material on dielectric base, so that being filled in described at least one through hole, electric conducting material forms at least one conductive hole, be filled in the first blind slot figure and form the first line pattern, also be filled in the second blind slot figure and form the second line pattern, described the first line pattern is embedded in dielectric base and flushes with first surface, described the second line pattern is embedded in dielectric base and flushes with second surface, described the first line pattern has the assembling district and reaches around the pressing district that assembles district, described the first line pattern is electrically connected to the second line pattern by described at least one conductive hole,
Thereby the first surface in dielectric base forms the first solderless substrate acquisition multilager base plate, described the first solderless substrate comprises the first conducting wire layer and the first film, described the first film is pressed together between the first conducting wire layer and first surface, and described the first conducting wire layer is electrically connected to the first line pattern; And
Remove first solderless substrate corresponding with the assembling district, thus in multilager base plate the groove of one of formation outside being exposed to, described assembling district is exposed in described groove.
2. the manufacture method of multilayer circuit board as claimed in claim 1, it is characterized in that, in multilager base plate, form one be exposed to outer groove after, also be included in the step of installation electronic devices and components in groove, described electronic devices and components are electrically connected to the assembling district of the first line pattern.
3. the manufacture method of multilayer circuit board as claimed in claim 2, it is characterized in that, by coating technology on dielectric base after deposits conductive material, also by polish-brush or etched step, remove the electric conducting material that protrudes from first surface and second surface, so that the electric conducting material be filled in described at least one through hole all flushes with first surface, second surface, make the electric conducting material be filled in the first blind slot figure flush with first surface, make the electric conducting material be filled in the second blind slot figure flush with second surface.
4. the manufacture method of multilayer circuit board as claimed in claim 2, it is characterized in that, after forming the first line pattern and the second line pattern, before the first surface of dielectric base forms the first solderless substrate, the manufacture method of described multilayer circuit board also is included in the step that assembling surface, district arranges the protection film; When removing this part first solderless substrate corresponding with assembling district or afterwards, the manufacture method of described multilayer circuit board is also removed the step of described protection film.
5. the manufacture method of multilayer circuit board as claimed in claim 2, is characterized in that, forms the first solderless substrate at the first surface of dielectric base and comprise step:
The first Copper Foil and described the first film are provided;
Stack gradually described the first Copper Foil, the first film and dielectric base, and described the first Copper Foil of one step press, the first film and dielectric base;
Form at least one first blind via hole to be electrically connected to the first Copper Foil and the first line pattern in the first film by boring and coating technology; And
Thereby by image transfer and chemical etching process selective etch the first Copper Foil, the first Copper Foil is made to described the first conducting wire layer.
6. the manufacture method of multilayer circuit board as claimed in claim 2, it is characterized in that, described the first solderless substrate comprises the 3rd conducting wire layer, the 3rd film, the first conducting wire layer and first film of laminating successively, described the 3rd film is pressed together between the 3rd conducting wire layer and the first conducting wire layer, described the first film is pressed together between the first conducting wire layer and first surface, forms the first solderless substrate at the first surface of dielectric base and comprises step:
The first Copper Foil and described the first film are provided;
Stack gradually described the first Copper Foil, the first film and dielectric base, and described the first Copper Foil of one step press, the first film and dielectric base;
Form at least one first blind via hole to be electrically connected to the first Copper Foil and the first line pattern in the first film by boring and coating technology;
Thereby by image transfer and chemical etching process selective etch the first Copper Foil, the first Copper Foil is made to described the first conducting wire layer;
The 3rd Copper Foil and described the 3rd film are provided;
The 3rd film is pressed between the 3rd Copper Foil and the first conducting wire layer;
Form at least one the 3rd blind via hole to be electrically connected to bronze medal three Copper Foils and the first conducting wire layer in the 3rd film by boring and coating technology; And
Thereby by image transfer and chemical etching process selective etch the 3rd Copper Foil, the 3rd Copper Foil is made to described the 3rd conducting wire layer.
7. the manufacture method of multilayer circuit board as claimed in claim 2, it is characterized in that, when the first surface of dielectric base forms the first solderless substrate, also the second surface in dielectric base forms the second solderless substrate, described the second solderless substrate comprises the second conducting wire layer and the second film, described the second film is pressed together between the second conducting wire layer and second surface, and described the second conducting wire layer and the second line pattern are electrically connected to.
8. the manufacture method of multilayer circuit board as claimed in claim 2, is characterized in that, before forming groove or afterwards, also on the first solderless substrate surface, forms welding resisting layer.
9. a multilayer circuit board, it comprises the first solderless substrate and the circuit base plate be pressed on together, described the first solderless substrate comprises the first conducting wire layer and the first film, described circuit base plate comprises dielectric base, the first line pattern, the second line pattern and at least one conductive hole, described dielectric base has relative first surface and second surface, described the first film is between the first conducting wire layer and first surface, described the first line pattern, the second line pattern and at least one conductive hole all are embedded in dielectric base, described at least one conductive hole is exposed to first surface and second surface, and with first surface, second surface all flushes, described the first line pattern only is exposed to first surface and flushes with first surface, described the first circuit graphics package is drawn together the assembling district and is reached around the pressing district that assembles district, described the second line pattern only is exposed to second surface and flushes with second surface, described the second line pattern is electrically connected to the first line pattern by described at least one conductive hole, described multilayer circuit board have one that run through the first solderless substrate and be exposed to outer groove, described groove is corresponding with the assembling district, described assembling district is exposed in groove.
10. a multilayer circuit board, it comprises the first solderless substrate, circuit base plate and electronic devices and components, described the first solderless substrate is with together with circuit base plate is pressed on, described the first solderless substrate comprises the first conducting wire layer and the first film, described circuit base plate comprises dielectric base, the first line pattern, the second line pattern and at least one conductive hole, described dielectric base has relative first surface and second surface, described the first film is between the first conducting wire layer and first surface, described the first line pattern, the second line pattern and at least one conductive hole all are embedded in dielectric base, described at least one conductive hole is exposed to first surface and second surface, and with first surface, second surface all flushes, described the first line pattern only is exposed to first surface and flushes with first surface, described the first circuit graphics package is drawn together the assembling district and is reached around the pressing district that assembles district, described the second line pattern only is exposed to second surface and flushes with second surface, described the second line pattern is electrically connected to the first line pattern by described at least one conductive hole, described multilayer circuit board have one that run through the first solderless substrate and be exposed to outer groove, described groove is corresponding with the assembling district, described assembling district is exposed in groove, described electronic devices and components are placed in described groove and are installed on the assembling district of circuit base plate.
11. multilayer circuit board as described as claim 9 or 10, it is characterized in that, described multilayer circuit board also comprises the second solderless substrate, described the second solderless substrate comprises the second conducting wire layer and the second film, described the second film is pressed together between the second conducting wire layer and second surface, and described the second conducting wire layer and the second line pattern are electrically connected to.
12. multilayer circuit board as claimed in claim 11, it is characterized in that, described multilayer circuit board also comprises the first welding resisting layer and the second welding resisting layer, described the first welding resisting layer is arranged on the first layer surface, conducting wire and exposes described groove, and described the second welding resisting layer is arranged on the second layer surface, conducting wire.
13. multilayer circuit board as claimed in claim 11, it is characterized in that, described the first conducting wire layer is electrically connected to the first line pattern by least one first blind via hole, described the second conducting wire layer is electrically connected to the second line pattern by least one second blind via hole, described the first solderless substrate also comprises the 3rd conducting wire layer and the 3rd film, described the 3rd film is pressed together between the 3rd conducting wire layer and the first conducting wire layer, described the 3rd conducting wire layer is electrically connected to the first conducting wire layer by least one the 3rd blind via hole, described the second solderless substrate also comprises the 4th conducting wire layer and the 4th film, described the 4th film is pressed together between the 4th conducting wire layer and the second conducting wire layer, described the 4th conducting wire layer is electrically connected to the second conducting wire layer by least one the 4th blind via hole.
14. multilayer circuit board as claimed in claim 13, it is characterized in that, described multilayer circuit board also comprises the first welding resisting layer and the second welding resisting layer, described the first welding resisting layer is arranged on the 3rd layer surface, conducting wire and exposes described groove, and described the second welding resisting layer is arranged on the 4th layer surface, conducting wire.
15. multilayer circuit board as claimed in claim 10, it is characterized in that, described assembling district comprises a plurality of pads, and described electronic devices and components have and a plurality of pads a plurality of splicing ears one to one, and each splicing ear all is electrically connected to a pad by a soldered ball projection.
Priority Applications (2)
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| CN201210171915.XA CN103458628B (en) | 2012-05-30 | 2012-05-30 | Multilayer circuit board and making method thereof |
| TW101120393A TWI507096B (en) | 2012-05-30 | 2012-06-07 | Multilayer printed circuit board and method for manufacturing same |
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| CN201210171915.XA CN103458628B (en) | 2012-05-30 | 2012-05-30 | Multilayer circuit board and making method thereof |
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| CN103458628B CN103458628B (en) | 2016-06-01 |
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Also Published As
| Publication number | Publication date |
|---|---|
| TWI507096B (en) | 2015-11-01 |
| TW201349957A (en) | 2013-12-01 |
| CN103458628B (en) | 2016-06-01 |
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