JP2014107552A - Multilayer printed circuit board and method of manufacturing the same - Google Patents

Multilayer printed circuit board and method of manufacturing the same Download PDF

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JP2014107552A
JP2014107552A JP2013233798A JP2013233798A JP2014107552A JP 2014107552 A JP2014107552 A JP 2014107552A JP 2013233798 A JP2013233798 A JP 2013233798A JP 2013233798 A JP2013233798 A JP 2013233798A JP 2014107552 A JP2014107552 A JP 2014107552A
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circuit board
density
layer
conductive
electrical contact
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Shr-Bin Shiu
詩濱 許
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Zhen Ding Technology Co Ltd
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Zhen Ding Technology Co Ltd
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4688Composite multilayer circuits, i.e. comprising insulating layers having different properties
    • H05K3/4694Partitioned multilayer circuits having adjacent regions with different properties, e.g. by adding or inserting locally circuit layers having a higher circuit density
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4697Manufacturing multilayer circuits having cavities, e.g. for mounting components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/183Components mounted in and supported by recessed areas of the printed circuit board
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09009Substrate related
    • H05K2201/09036Recesses or grooves in insulating substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09009Substrate related
    • H05K2201/09127PCB or component having an integral separable or breakable part
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09372Pads and lands
    • H05K2201/09445Pads for connections not located at the edge of the PCB, e.g. for flexible circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09372Pads and lands
    • H05K2201/09472Recessed pad for surface mounting; Recessed electrode of component
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10Methods of surface bonding and/or assembly therefor
    • Y10T156/1052Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing
    • Y10T156/1062Prior to assembly
    • Y10T156/1064Partial cutting [e.g., grooving or incising]

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer printed circuit board and a method of manufacturing the same.SOLUTION: The multilayer printed circuit board includes a multilayer substrate and a first high-density circuit board. The multilayer substrate includes a base layer, a first conductive circuit layer which is formed on one side of the base layer, a plurality of first insulation material layers and a plurality of third conductive circuit layers which are successively and alternately laminated on the first conductive circuit layer. A first housing part is formed within the plurality of first insulation material layers and the plurality of third conductive circuit layers, and the first conductive circuit layer is partially exposed from the first housing part and constitutes a plurality of electric contact pads. The first high-density circuit board includes a plurality of first high-density circuit layers and a plurality of third insulation material layers which are alternately installed on each other. An outermost first high-density circuit layer on one side of the first high-density circuit board includes a plurality of third electric contact pads, the first high-density circuit board is installed in the first housing part, and the plurality of third electric contact pads are respectively electrically connected to the plurality of first electric contact pads.

Description

本発明は、多層回路基板及びその製作方法に関するものである。   The present invention relates to a multilayer circuit board and a manufacturing method thereof.

プリント回路基板は、実装密度が高い美点を有するので広く応用されている。回路基板の応用に関しては、非特許文献1を参照することができる。   Printed circuit boards are widely applied because they have the beauty of high mounting density. Regarding the application of the circuit board, Non-Patent Document 1 can be referred to.

従来の高密度多層回路基板において、高密度導電回路領域は回路基板の比較的小さい局部領域に集中される。高密度多層回路基板の製作過程において、回路基板全体に対して加工し、高密度領域の導電回路の製作歩留まり率が低密度領域の導電回路の製作歩留まり率より低く、高密度領域の導電回路に不良が存在する場合、回路基板全体の不良を招き、従って回路基板の製作歩留まり率が低下してしまう。又、高密度回路製作技術を利用して低密度回路領域を製作する場合は、製造コストが高くなってしまう。   In a conventional high density multilayer circuit board, the high density conductive circuit area is concentrated in a relatively small local area of the circuit board. In the manufacturing process of the high-density multilayer circuit board, the entire circuit board is processed, and the manufacturing yield rate of the conductive circuit in the high-density region is lower than the manufacturing yield rate of the conductive circuit in the low-density region. If there is a defect, the entire circuit board will be defective, and therefore the production yield of the circuit board will be reduced. In addition, when a low density circuit region is manufactured using a high density circuit manufacturing technique, the manufacturing cost is increased.

Takahashi,A.Ooki,N.Nagai,A.Akahoshi,H.Mukoh,A.Wajima,M.Res.Lab,High density multilayer printed circuit board for HITAC M−880,IEEE Trans.on Components,Packaging,and Manufacturing Technology,1992,15(4):1418−1425Takahashi, A .; Oki, N .; Nagai, A .; Akahoshi, H .; Mukoh, A .; Wajima, M .; Res. Lab, High density multi-layer printed circuit board for HITAC M-880, IEEE Trans. on Components, Packaging, and Manufacturing Technology, 1992, 15 (4): 1418-1425.

本発明の目的は、前記課題を解決し、製作歩留まり率が高く且つコストが低い多層回路基板及びその製作方法を提供することである。   An object of the present invention is to solve the above-mentioned problems and to provide a multilayer circuit board having a high production yield rate and low cost and a method for producing the same.

本発明に係る多層回路基板は、ベース層、ベース層の一方側の面に形成される第一導電回路層、第一導電回路層の上に順次に交互に積層される複数の第一絶縁材料層及び複数の第三導電回路層を備え、複数の第一絶縁材料層及び複数の第三導電回路層の内部に第一収容部が形成され、一部分の第一導電回路層は第一収容部から露出されて複数の第一電気接触パッドを構成する多層基板と、交互に設置される複数の第一高密度回路層及び複数の第三絶縁材料層を備える第一高密度回路基板であって、第一高密度回路層の回路密度は第一導電回路層の回路密度より大きく、第一高密度回路基板の一方側の最外層の第一高密度回路層は複数の第三電気接触パッドを備え、第一高密度回路基板は第一収容部に設置されて、複数の第三電気接触パッドは複数の第一電気接触パッドのそれぞれに電気的に接続される第一高密度回路基板と、を備える。   A multilayer circuit board according to the present invention includes a base layer, a first conductive circuit layer formed on one surface of the base layer, and a plurality of first insulating materials that are sequentially stacked on the first conductive circuit layer. A first housing part is formed inside the plurality of first insulating material layers and the plurality of third conductive circuit layers, and a part of the first conductive circuit layer is a first housing part. A first high-density circuit board comprising a multi-layer board that is exposed from and constituting a plurality of first electrical contact pads, and a plurality of first high-density circuit layers and a plurality of third insulating material layers that are alternately disposed The circuit density of the first high-density circuit layer is greater than the circuit density of the first conductive circuit layer, and the outermost first high-density circuit layer on one side of the first high-density circuit board includes a plurality of third electrical contact pads. The first high-density circuit board is installed in the first housing portion, and the plurality of third electrical contact pads are And a first high-density circuit board electrically connected to each of the first electrical contact pad number.

本発明に係る多層回路基板の製作方法は、ベース層と、ベース層の一方側の面に形成される第一導電回路層と、第一導電回路層の上に順次に交互に積層される複数の第一絶縁材料層及び複数の第三導電回路層と、を備える多層基板を提供するステップと、複数の第一絶縁材料層及び複数の第三導電回路層の内部に第一収容部を形成して、一部分の第一導電回路層を第一収容部から露出させて複数の第一電気接触パッドを構成するステップと、交互に設置される複数の第一高密度回路層及び複数の第三絶縁材料層を備える第一高密度回路基板を提供し、第一高密度回路基板の一方側の最外層の第一高密度回路層は複数の第三電気接触パッドを備え、第一高密度回路層の回路密度は第一導電回路層の回路密度より大きいステップと、第一高密度回路基板を多層基板の第一収容部に設置して、複数の第三電気接触パッドを複数の第一電気接触パッドのそれぞれに電気的に接続させて多層回路基板を形成するステップと、を備える。   A method for manufacturing a multilayer circuit board according to the present invention includes a base layer, a first conductive circuit layer formed on one surface of the base layer, and a plurality of layers alternately stacked on the first conductive circuit layer sequentially. Providing a multilayer substrate comprising: a first insulating material layer and a plurality of third conductive circuit layers; and forming a first accommodating portion inside the plurality of first insulating material layers and the plurality of third conductive circuit layers. A step of exposing a part of the first conductive circuit layer from the first housing part to form a plurality of first electrical contact pads, a plurality of first high-density circuit layers and a plurality of thirds arranged alternately A first high-density circuit board comprising an insulating material layer is provided, and the first high-density circuit layer on the outermost layer on one side of the first high-density circuit board comprises a plurality of third electrical contact pads, The circuit density of the layer is greater than the circuit density of the first conductive circuit layer, and the first high-density circuit By installing a substrate in the first housing part of the multi-layer substrate, comprising the steps of forming a multilayer circuit board electrically connected to the respective plurality of third electrical contact pads of the plurality of first electrical contact pad, a.

本発明の多層回路基板及びその製作方法は、第一高密度回路基板を独立に製作してから電気回路基板の高密度回路領域として多層基板に設置するので、第一高密度回路基板の導電回路に不良が存在する場合、ただ第一高密度回路基板を捨てるだけで良く、多層回路基板全体を捨てることを必要としない。従って多層回路基板の製作歩留まり率を高め、製作コストを下げることができる。   In the multilayer circuit board and the manufacturing method thereof according to the present invention, the first high-density circuit board is independently manufactured and then installed on the multilayer board as the high-density circuit area of the electric circuit board. If there is a defect, it is only necessary to discard the first high-density circuit board, and it is not necessary to discard the entire multilayer circuit board. Therefore, the production yield rate of the multilayer circuit board can be increased and the production cost can be reduced.

本発明の実施形態に係る多層回路基板の製作過程で提供される回路基板の断面図である。1 is a cross-sectional view of a circuit board provided in a manufacturing process of a multilayer circuit board according to an embodiment of the present invention. 図1に示す回路基板における互いに反対側の2つの表面に別々に多層導電回路層及び多層絶縁材料層を形成してなる多層基板の断面図である。FIG. 2 is a cross-sectional view of a multilayer substrate in which a multilayer conductive circuit layer and a multilayer insulating material layer are separately formed on two opposite surfaces of the circuit substrate shown in FIG. 1. 図2に示す多層基板における互いに反対側の両側に別々に収容部を形成した後の断面図である。It is sectional drawing after forming a accommodating part separately in the both sides on the opposite side in the multilayer substrate shown in FIG. 本発明の実施形態に係る多層回路基板の製作過程で提供される第一高密度回路基板の断面図である。It is sectional drawing of the 1st high-density circuit board provided in the manufacture process of the multilayer circuit board based on embodiment of this invention. 複数の図4に示す第一高密度回路基板を第一テープに取り付けた後の平面図である。It is a top view after attaching the several 1st high-density circuit board shown in FIG. 4 to the 1st tape. 本発明の実施形態に係る多層回路基板の製作過程で提供される第二高密度回路基板の断面図である。It is sectional drawing of the 2nd high-density circuit board provided in the manufacture process of the multilayer circuit board based on embodiment of this invention. 複数の図6に示す第二高密度回路基板を第二テープに取り付けた後の平面図である。It is a top view after attaching the 2nd high-density circuit board shown in Drawing 6 to the 2nd tape. 図3に示す多層基板における互いに反対側の両側の収容部に導電粘着剤を設置した後の断面図である。It is sectional drawing after installing a conductive adhesive in the accommodating part of the both opposite sides in the multilayer substrate shown in FIG. 図8に示す多層基板における互いに反対側の両側の収容部に図4に示す第一高密度回路基板及び図6に示す第二高密度回路基板を設置した後の断面図である。FIG. 9 is a cross-sectional view after the first high-density circuit board shown in FIG. 4 and the second high-density circuit board shown in FIG. 6 are installed in the accommodating portions on opposite sides of the multilayer board shown in FIG. 8. 図3に示す多層基板における互いに反対側の両側の収容部に異方性導電フィルムを設置した後の断面図である。It is sectional drawing after installing an anisotropic conductive film in the accommodating part of the both opposite sides in the multilayer substrate shown in FIG. 図3に示す多層基板における互いに反対側の両側の収容部に導電溶接剤を設置した後の断面図である。It is sectional drawing after installing a conductive welding agent in the accommodating part of the both opposite sides in the multilayer board | substrate shown in FIG.

以下、図面を参照して、本発明の実施形態について説明する。   Embodiments of the present invention will be described below with reference to the drawings.

本発明の実施形態に係る多層回路基板の製作方法は、以下のステップを備える。   A method for manufacturing a multilayer circuit board according to an embodiment of the present invention includes the following steps.

第一ステップ:図1に示されたように、回路基板10を提供する。   First step: As shown in FIG. 1, a circuit board 10 is provided.

回路基板10は、対向する第一表面111及び第二表面112を有するベース層11と、第一表面111に形成される第一導電回路層12と、第二表面112に形成される第二導電回路層13と、を備える。第一導電回路層12及び第二導電回路層13は、イメージ転写及びエッチングによって形成される。   The circuit board 10 includes a base layer 11 having a first surface 111 and a second surface 112 facing each other, a first conductive circuit layer 12 formed on the first surface 111, and a second conductive formed on the second surface 112. And a circuit layer 13. The first conductive circuit layer 12 and the second conductive circuit layer 13 are formed by image transfer and etching.

第二ステップ:図2に示されたように、回路基板10の第一導電回路層12側に複数の第一絶縁材料層15及び複数の第三導電回路層14を交互に圧合形成して、第一導電回路層12と第三導電回路層14との間及び隣り合う2つの第三導電回路層14の間は、それぞれ第一絶縁材料層15によって隔てられ、回路基板10の第二導電回路層13側に複数の第二絶縁材料層17及び複数の第四導電回路層16を交互に圧合形成して、第二導電回路層13と第四導電回路層16との間及び隣り合う2つの第四導電回路層16の間は、それぞれ第二絶縁材料層17によって隔てられる。第一導電回路層12、第二導電回路層13、第三導電回路層14及び第四導電回路層16は、導電貫通孔18及び導電ブラインドビア(BlindVia)19によって層間電気接続を実現して、多層基板20を形成する。   Second step: As shown in FIG. 2, a plurality of first insulating material layers 15 and a plurality of third conductive circuit layers 14 are alternately pressed and formed on the first conductive circuit layer 12 side of the circuit board 10. The first conductive circuit layer 12 and the third conductive circuit layer 14 and the two adjacent third conductive circuit layers 14 are separated by the first insulating material layer 15, respectively. A plurality of second insulating material layers 17 and a plurality of fourth conductive circuit layers 16 are alternately pressed and formed on the circuit layer 13 side, and between and adjacent to the second conductive circuit layer 13 and the fourth conductive circuit layer 16. The two fourth conductive circuit layers 16 are separated from each other by a second insulating material layer 17. The first conductive circuit layer 12, the second conductive circuit layer 13, the third conductive circuit layer 14, and the fourth conductive circuit layer 16 realize interlayer electrical connection by a conductive through hole 18 and a conductive blind via (Blind Via) 19, A multilayer substrate 20 is formed.

多層基板20のベース層11の対向する両側は、全て高密度回路領域及び低密度回路領域を備える。ベース層11の第一表面111側は第一高密度回路領域21及び第一低密度回路領域22を備え、ベース層11の第二表面112側は第二高密度回路領域23及び第二低密度回路領域24を備える。本実施形態においては、第一高密度回路領域21及び第二高密度回路領域23に導電回路を設置しなかった。複数の第一絶縁材料層15、複数の第三導電回路層14、複数の第二絶縁材料層17及び複数の第四導電回路層16は、他の製造方法でも形成することができ、本実施形態の圧合方法で形成されることに制限されるものではない。   Both opposing sides of the base layer 11 of the multilayer substrate 20 are each provided with a high density circuit region and a low density circuit region. The first surface 111 side of the base layer 11 includes a first high density circuit region 21 and a first low density circuit region 22, and the second surface 112 side of the base layer 11 includes a second high density circuit region 23 and a second low density circuit region. A circuit region 24 is provided. In the present embodiment, no conductive circuit is installed in the first high-density circuit region 21 and the second high-density circuit region 23. The plurality of first insulating material layers 15, the plurality of third conductive circuit layers 14, the plurality of second insulating material layers 17 and the plurality of fourth conductive circuit layers 16 can be formed by other manufacturing methods. It is not limited to being formed by the form compression method.

第三ステップ:図3に示されたように、多層基板20の第一高密度回路領域21の複数の第一絶縁材料層15を除去して第一収容部201を形成し、一部分の第一導電回路層12は第一収容部201から露出されて複数の第一電気接触パッド25を構成し、多層基板20の第二高密度回路領域23の複数の第二絶縁材料層17を除去して第二収容部202を形成し、一部分の第二導電回路層13は第二収容部202から露出されて複数の第二電気接触パッド26を構成する。   Third step: As shown in FIG. 3, the plurality of first insulating material layers 15 in the first high-density circuit region 21 of the multilayer substrate 20 are removed to form a first accommodating portion 201, and a part of the first The conductive circuit layer 12 is exposed from the first accommodating portion 201 to form a plurality of first electrical contact pads 25, and the plurality of second insulating material layers 17 in the second high-density circuit region 23 of the multilayer substrate 20 are removed. The second accommodating part 202 is formed, and a part of the second conductive circuit layer 13 is exposed from the second accommodating part 202 to constitute a plurality of second electrical contact pads 26.

レーザー切断方式又は機械切断方式を採用して複数の第一絶縁材料層15及び複数の第二絶縁材料層17を除去することができる。第一高密度回路領域21及び第二高密度回路領域23に導電回路が設置される場合、対応する導電回路を一緒に除去する。   The plurality of first insulating material layers 15 and the plurality of second insulating material layers 17 can be removed by employing a laser cutting method or a mechanical cutting method. When conductive circuits are installed in the first high-density circuit region 21 and the second high-density circuit region 23, the corresponding conductive circuits are removed together.

第四ステップ:図4及び図5に示されたように、第一高密度回路基板27を提供する。第一高密度回路基板27は、交互に設置される複数の第一高密度回路層28及び複数の第三絶縁材料層29を備え、複数の第一高密度回路層28は、複数の第三絶縁材料層29の内部に設置された複数の第一導電孔30によって電気的に接続される。第一高密度回路基板27の最外層の第一高密度回路層28の一部分は露出されて複数の第三電気接触パッド282を構成し、第三電気接触パッド282と第一電気接触パッド25の数量及び位置は対応する。   Fourth step: As shown in FIGS. 4 and 5, the first high-density circuit board 27 is provided. The first high-density circuit board 27 includes a plurality of first high-density circuit layers 28 and a plurality of third insulating material layers 29 that are alternately arranged. The plurality of first high-density circuit layers 28 includes a plurality of third high-density circuit layers 28. They are electrically connected by a plurality of first conductive holes 30 installed inside the insulating material layer 29. A portion of the first high-density circuit layer 28 that is the outermost layer of the first high-density circuit board 27 is exposed to form a plurality of third electrical contact pads 282, and the third electrical contact pads 282 and the first electrical contact pads 25 are formed. Quantity and position correspond.

複数の第一高密度回路層28の回路密度は、第一導電回路層12及び第二導電回路層13の回路密度より大きい。図5に示されたように、第一高密度回路基板27の製作を完了してから第一テープ31に取り付けて、後に、高速チップマウンターで第一テープ31の上の第一高密度回路基板27を多層基板20に装着する。第一高密度回路基板27は圧合方法で形成されるが、これに限定されるものではない。本実施形態において、第一導電孔30は導電ブラインドビアである。本実施形態において、第一高密度回路基板27の第三電気接触パッド282から離れている最外層の第三絶縁材料層29は第一溶接防止層292であり、第一溶接防止層292はそれに隣り合う第一高密度回路層28を部分的に覆って、第一溶接防止層292から露出された最外層の第一高密度回路層28は、レジスター、キャパシター、チップなどの電子素子を溶接するために用いられる第四電気接触パッド284を構成する。   The circuit density of the plurality of first high-density circuit layers 28 is larger than the circuit density of the first conductive circuit layer 12 and the second conductive circuit layer 13. As shown in FIG. 5, after the first high-density circuit board 27 is manufactured, it is attached to the first tape 31, and then the first high-density circuit board on the first tape 31 with a high-speed chip mounter. 27 is mounted on the multilayer substrate 20. The first high-density circuit board 27 is formed by a compression method, but is not limited to this. In the present embodiment, the first conductive hole 30 is a conductive blind via. In this embodiment, the third outermost insulating material layer 29 that is separated from the third electrical contact pad 282 of the first high-density circuit board 27 is the first welding prevention layer 292, and the first welding prevention layer 292 is The first high-density circuit layer 28, which is the outermost layer and partially covers the adjacent first high-density circuit layers 28 and is exposed from the first welding prevention layer 292, welds electronic elements such as resistors, capacitors, and chips. A fourth electrical contact pad 284 used for the purpose.

第五ステップ:図6及び図7に示されたように、第二高密度回路基板32を提供する。第二高密度回路基板32は、交互に設置される複数の第二高密度回路層33及び複数の第四絶縁材料層34を備え、複数の第二高密度回路層33は、複数の第四絶縁材料層34の内部に設置された複数の第二導電孔37によって電気的に接続される。第二高密度回路基板32の最外層の第二高密度回路層33の一部分は暴露されて複数の第五電気接触パッド332を構成し、第五電気接触パッド332と第二電気接触パッド26の数量及び位置は対応する。   Fifth step: As shown in FIGS. 6 and 7, the second high-density circuit board 32 is provided. The second high-density circuit board 32 includes a plurality of second high-density circuit layers 33 and a plurality of fourth insulating material layers 34 that are alternately arranged, and the plurality of second high-density circuit layers 33 includes a plurality of fourth high-density circuit layers 33. They are electrically connected by a plurality of second conductive holes 37 installed inside the insulating material layer 34. A portion of the second high-density circuit layer 33 that is the outermost layer of the second high-density circuit board 32 is exposed to form a plurality of fifth electrical contact pads 332, and the fifth electrical contact pads 332 and the second electrical contact pads 26 are formed. Quantity and position correspond.

複数の第二高密度回路層33の回路密度は、第一導電回路層12及び第二導電回路層13の回路密度より大きい。図7に示されたように、第二高密度回路基板32の製作を完了してから第二テープ35に取り付けて、後に、高速チップマウンターで第二テープ35の上の第二高密度回路基板32を多層基板20に装着する。第二高密度回路基板32は圧合方法で形成されるが、これに限定されるものではない。本実施形態において、第二導電孔37は導電ブラインドビアである。本実施形態において、第二高密度回路基板32の第五電気接触パッド332から離れている最外層の第四絶縁材料層34は第二溶接防止層342であり、第二溶接防止層342はそれに隣り合う第二高密度回路層33を部分的に覆って、第二溶接防止層342から露出された最外層の第二高密度回路層33は、レジスター、キャパシター、チップなどの電子素子を溶接するために用いられる第六電気接触パッド334を構成する。   The circuit density of the plurality of second high-density circuit layers 33 is greater than the circuit density of the first conductive circuit layer 12 and the second conductive circuit layer 13. As shown in FIG. 7, after the fabrication of the second high-density circuit board 32 is completed, the second high-density circuit board 32 is attached to the second tape 35 and later on the second tape 35 with a high-speed chip mounter. 32 is mounted on the multilayer substrate 20. The second high-density circuit board 32 is formed by a pressing method, but is not limited to this. In the present embodiment, the second conductive hole 37 is a conductive blind via. In the present embodiment, the outermost fourth insulating material layer 34 that is separated from the fifth electrical contact pad 332 of the second high-density circuit board 32 is the second welding prevention layer 342, and the second welding prevention layer 342 is the same. The second high-density circuit layer 33 which is the outermost layer and partially covers the adjacent second high-density circuit layer 33 and is exposed from the second welding prevention layer 342 welds electronic elements such as resistors, capacitors, and chips. The sixth electrical contact pad 334 used for the purpose is configured.

第六ステップ:図8に示されたように、多層基板20の第一収容部201から露出された第一電気接触パッド25及び第二収容部202から露出された第二電気接触パッド26の端面のそれぞれに導電粘着層36を形成する。本実施形態において、導電粘着層36は、導電銀ペースト又は導電銅ペーストを印刷する方式によって形成される。   Sixth Step: As shown in FIG. 8, the end surfaces of the first electrical contact pad 25 exposed from the first housing part 201 and the second electrical contact pad 26 exposed from the second housing part 202 of the multilayer substrate 20. A conductive adhesive layer 36 is formed on each of these. In the present embodiment, the conductive adhesive layer 36 is formed by a method of printing a conductive silver paste or a conductive copper paste.

図10に示されたように、導電粘着層36は異方性導電フィルム361であることができる。図11に示されたように、導電粘着層36は錫導電膏のような導電溶接剤362であることができ、本実施形態において、導電溶接剤362を形成する前に、先ず第一電気接触パッド25及び第二電気接触パッド26の周囲に溶接防止構造363を形成してから、印刷方式によって導電溶接剤362を第一電気接触パッド25及び第二電気接触パッド26の端面に形成する。   As shown in FIG. 10, the conductive adhesive layer 36 may be an anisotropic conductive film 361. As shown in FIG. 11, the conductive adhesive layer 36 may be a conductive welding agent 362 such as a tin conductive paste, and in this embodiment, first, before forming the conductive welding agent 362, first the first electrical contact is made. After the weld prevention structure 363 is formed around the pad 25 and the second electrical contact pad 26, the conductive welding agent 362 is formed on the end surfaces of the first electrical contact pad 25 and the second electrical contact pad 26 by a printing method.

第七ステップ:図9に示されたように、第一高密度回路基板27を第一収容部201に固定して、複数の第三電気接触パッド282は導電粘着層36によって複数の第一電気接触パッド25のそれぞれに電気的に接続され、第二高密度回路基板32を第二収容部202に固定して、複数の第五電気接触パッド332は導電粘着層36によって複数の第二電気接触パッド26のそれぞれに電気的に接続されて、多層回路基板40を形成する。   Seventh step: As shown in FIG. 9, the first high-density circuit board 27 is fixed to the first housing portion 201, and the plurality of third electrical contact pads 282 are formed by the conductive adhesive layer 36 to form a plurality of first electrical contacts. The second high-density circuit board 32 is electrically connected to each of the contact pads 25 and the second high-density circuit board 32 is fixed to the second housing portion 202, and the plurality of fifth electric contact pads 332 are connected to the plurality of second electric contacts by the conductive adhesive layer 36. A multilayer circuit board 40 is formed by being electrically connected to each of the pads 26.

第四ステップ及び第五ステップにおいて、第一高密度回路基板27及び第二高密度回路基板32は別々に第一テープ31及び第二テープ35に取り付けられ、第一テープ31及び第二テープ35は高速チップマウンター(図示せず)に装着されるので、第七ステップにおいて、高速チップマウンターによって第一高密度回路基板27及び第二高密度回路基板32を別々に第一収容部201の第一電気接触パッド25及び第二収容部202の第二電気接触パッド26に接着する。高速チップマウンターの数量は一般的に2つであり、第一高密度回路基板27の接着を完了してから、第一高密度回路基板27を接着した多層基板20を第一高速チップマウンターから退出して反転し、その後に第二高速チップマウンターに入って第二高密度回路基板32を接着する。   In the fourth step and the fifth step, the first high-density circuit board 27 and the second high-density circuit board 32 are separately attached to the first tape 31 and the second tape 35, and the first tape 31 and the second tape 35 are Since it is attached to a high-speed chip mounter (not shown), in the seventh step, the first high-density circuit board 27 and the second high-density circuit board 32 are separately separated from each other by the high-speed chip mounter. It adheres to the contact pad 25 and the second electrical contact pad 26 of the second housing portion 202. The number of high-speed chip mounters is generally two. After completing the bonding of the first high-density circuit board 27, the multilayer board 20 to which the first high-density circuit board 27 is bonded leaves the first high-speed chip mounter. Then, the second high-speed chip mounter is entered and the second high-density circuit board 32 is bonded.

第一高密度回路基板27及び第二高密度回路基板32を接着した後、第一高密度回路基板27及び第二高密度回路基板32の最外側表面は、多層基板20の最外層表面と同じ平面にあるか又は多層基板20の最外層表面から突出されるか又は多層基板20の最外層表面から凹む。第一収容部201の内壁と第一高密度回路基板27との間の隙間及び第二収容部202の内壁と第二高密度回路基板32との間の隙間に樹脂を充填してもよく、又は充填しなくてもよい。   After bonding the first high-density circuit board 27 and the second high-density circuit board 32, the outermost surfaces of the first high-density circuit board 27 and the second high-density circuit board 32 are the same as the outermost surface of the multilayer board 20. It is in a plane or protrudes from the outermost layer surface of the multilayer substrate 20 or is recessed from the outermost layer surface of the multilayer substrate 20. The gap between the inner wall of the first housing part 201 and the first high-density circuit board 27 and the gap between the inner wall of the second housing part 202 and the second high-density circuit board 32 may be filled with resin, Or it does not need to be filled.

実際の生産過程においては、第一ステップ〜第三ステップ、第六ステップ及び第七ステップにおいて、回路基板10は接続された複数の回路基板ユニットを備え、第七ステップで複数の多層回路基板40を形成してから切断して、分離された複数の多層回路基板40を形成する。本実施形態においては、説明を容易にするために、回路基板10及び多層回路基板40の数は1つである。   In the actual production process, in the first step to the third step, the sixth step, and the seventh step, the circuit board 10 includes a plurality of connected circuit board units, and in the seventh step, the plurality of multilayer circuit boards 40 are formed. A plurality of separated multilayer circuit boards 40 are formed by cutting after forming. In the present embodiment, for ease of explanation, the number of the circuit boards 10 and the multilayer circuit boards 40 is one.

多層回路基板40は、第四導電回路層16、第二絶縁材料層17及び第二高密度回路基板32を設置しなくてもよく、ただ片側に高密度回路基板を設置することができ、本実施形態に限定されるものではない。   In the multilayer circuit board 40, the fourth conductive circuit layer 16, the second insulating material layer 17, and the second high-density circuit board 32 do not need to be installed, and the high-density circuit board can be installed only on one side. It is not limited to the embodiment.

図9に示されたように、本実施形態に係る多層回路基板40は、回路基板10、複数の第三導電回路層14、複数の第一絶縁材料層15、複数の第四導電回路層16、複数の第二絶縁材料層17、第一高密度回路基板27及び第二高密度回路基板32を備える。   As shown in FIG. 9, the multilayer circuit board 40 according to this embodiment includes a circuit board 10, a plurality of third conductive circuit layers 14, a plurality of first insulating material layers 15, and a plurality of fourth conductive circuit layers 16. A plurality of second insulating material layers 17, a first high-density circuit board 27, and a second high-density circuit board 32.

回路基板10は、ベース層11及びベース層11における互いに反対側の2つの表面に形成される第一導電回路層12及び第二導電回路層13を備え、複数の第一絶縁材料層15及び複数の第三導電回路層14は、回路基板10の第一導電回路層12側に順次に交互に積層され、複数の第二絶縁材料層17及び複数の第四導電回路層16は、回路基板10の第二導電回路層13側に順次に交互に積層される。複数の第一絶縁材料層15には第一収容部201が設けられて、一部分の第一導電回路層12は第一収容部201から露出されて第一電気接触パッド25を構成し、複数の第二絶縁材料層17には第二収容部202が設けられて、一部分の第二導電回路層13は第二収容部202から露出されて第二電気接触パッド26を構成する。   The circuit board 10 includes a first conductive circuit layer 12 and a second conductive circuit layer 13 formed on two surfaces of the base layer 11 and the base layer 11 opposite to each other. The third conductive circuit layers 14 are sequentially stacked alternately on the first conductive circuit layer 12 side of the circuit board 10, and the plurality of second insulating material layers 17 and the plurality of fourth conductive circuit layers 16 include the circuit board 10. The second conductive circuit layers 13 are sequentially stacked alternately. A plurality of first insulating material layers 15 are provided with a first accommodating portion 201, and a part of the first conductive circuit layer 12 is exposed from the first accommodating portion 201 to form a first electrical contact pad 25, The second insulating material layer 17 is provided with a second housing portion 202, and a part of the second conductive circuit layer 13 is exposed from the second housing portion 202 to constitute the second electrical contact pad 26.

第一高密度回路基板27は、交互に設置される複数の第一高密度回路層28及び複数の第三絶縁材料層29を備え、複数の第一高密度回路層28は、複数の第三絶縁材料層29の内部に設置された複数の第一導電孔30によって電気的に接続される。第一高密度回路基板27の最外層の第一高密度回路層28の一部分は露出されて複数の第三電気接触パッド282を形成し、第三電気接触パッド282と第一電気接触パッド25の数量及び位置は対応する。第一高密度回路基板27の第三電気接触パッド282から離れている最外層の第三絶縁材料層29は第一溶接防止層292であり、第一溶接防止層292はそれに隣り合う第一高密度回路層28を部分的に覆って、第一溶接防止層292から露出された最外層の第一高密度回路層28は、レジスター、キャパシター、チップなどの電子素子を溶接するために用いられる第四電気接触パッド284を構成する。   The first high-density circuit board 27 includes a plurality of first high-density circuit layers 28 and a plurality of third insulating material layers 29 that are alternately arranged. The plurality of first high-density circuit layers 28 includes a plurality of third high-density circuit layers 28. They are electrically connected by a plurality of first conductive holes 30 installed inside the insulating material layer 29. A portion of the outermost first high-density circuit layer 28 of the first high-density circuit board 27 is exposed to form a plurality of third electric contact pads 282, and the third electric contact pads 282 and the first electric contact pads 25 are formed. Quantity and position correspond. The outermost third insulating material layer 29 away from the third electrical contact pad 282 of the first high-density circuit board 27 is the first welding prevention layer 292, and the first welding prevention layer 292 is adjacent to the first height The outermost first high-density circuit layer 28 partially covering the density circuit layer 28 and exposed from the first welding prevention layer 292 is used for welding electronic elements such as resistors, capacitors, and chips. Four electrical contact pads 284 are constructed.

第二高密度回路基板32は、交互に設置される複数の第二高密度回路層33及び複数の第四絶縁材料層34を備え、複数の第二高密度回路層33は、複数の第四絶縁材料層34の内部に設置された複数の第二導電孔37によって電気的に接続される。第二高密度回路基板32の最外層の第二高密度回路層33の一部分は露出されて複数の第五電気接触パッド332を構成し、第五電気接触パッド332と第二電気接触パッド26の数量及び位置は対応する。第二高密度回路基板32の第五電気接触パッド332から離れている最外層の第四絶縁材料層34は第二溶接防止層342であり、第二溶接防止層342はそれに隣り合う第二高密度回路層33を部分的に覆って、第二溶接防止層342から露出された最外層の第二高密度回路層33は、レジスター、キャパシター、チップなどの電子素子を溶接するために用いられる第六電気接触パッド334を構成する。   The second high-density circuit board 32 includes a plurality of second high-density circuit layers 33 and a plurality of fourth insulating material layers 34 that are alternately arranged, and the plurality of second high-density circuit layers 33 includes a plurality of fourth high-density circuit layers 33. They are electrically connected by a plurality of second conductive holes 37 installed inside the insulating material layer 34. A portion of the second high-density circuit layer 33 that is the outermost layer of the second high-density circuit board 32 is exposed to form a plurality of fifth electric contact pads 332, and the fifth electric contact pads 332 and the second electric contact pads 26 are formed. Quantity and position correspond. The outermost fourth insulating material layer 34 that is separated from the fifth electrical contact pad 332 of the second high-density circuit board 32 is the second welding prevention layer 342, and the second welding prevention layer 342 is adjacent to the second height The outermost second high-density circuit layer 33 partially covering the density circuit layer 33 and exposed from the second anti-welding layer 342 is used for welding electronic elements such as resistors, capacitors, and chips. Six electrical contact pads 334 are configured.

複数の第一高密度回路層28及び複数の第二高密度回路層33の回路密度は、第一導電回路層12及び第二導電回路層13の回路密度より大きい。第一高密度回路基板27及び第二高密度回路基板32は別々に第一収容部201及び第二収容部202の内部に設置され、第一高密度回路基板27の複数の第三電気接触パッド282は導電粘着層36によって複数の第一電気接触パッド25のそれぞれに電気的に接続され、第二高密度回路基板32の複数の第五電気接触パッド332は導電粘着層36によって複数の第二電気接触パッド26のそれぞれに電気的に接続される。導電粘着層36は、導電銀ペースト、導電銅ペースト、異方性導電フィルム、錫導電膏のような導電溶接剤などであることができるが、これに限定されるものではない。第一収容部201の内壁と第一高密度回路基板27との間の隙間及び第二収容部202の内壁と第二高密度回路基板32との間の隙間に樹脂を充填することができる。   The circuit density of the plurality of first high-density circuit layers 28 and the plurality of second high-density circuit layers 33 is higher than the circuit density of the first conductive circuit layer 12 and the second conductive circuit layer 13. The first high-density circuit board 27 and the second high-density circuit board 32 are separately installed inside the first housing part 201 and the second housing part 202, and a plurality of third electrical contact pads of the first high-density circuit board 27 are provided. 282 is electrically connected to each of the plurality of first electrical contact pads 25 by the conductive adhesive layer 36, and the plurality of fifth electrical contact pads 332 of the second high-density circuit board 32 are connected to the plurality of second electrical contact pads 36 by the conductive adhesive layer 36. Electrically connected to each of the electrical contact pads 26. The conductive adhesive layer 36 may be a conductive silver paste, a conductive copper paste, an anisotropic conductive film, a conductive welding agent such as a tin conductive paste, but is not limited thereto. Resin can be filled in the gap between the inner wall of the first housing part 201 and the first high-density circuit board 27 and the gap between the inner wall of the second housing part 202 and the second high-density circuit board 32.

従来の技術に比べて、本実施形態に係る多層回路基板40の製造方法において、第一高密度回路基板27及び第二高密度回路基板32を独立に製作した後に電気回路基板の高密度回路領域として多層基板20に装着するので、第一高密度回路基板27及び第二高密度回路基板32の導電回路に不良が存在する場合、ただ第一高密度回路基板27及び第二高密度回路基板32を捨てるだけで良く、多層回路基板40全体を捨てることを必要としない。従って多層回路基板40の製作歩留まり率を高め、製作コストを下げることができる。   Compared to the prior art, in the method of manufacturing the multilayer circuit board 40 according to the present embodiment, the first high-density circuit board 27 and the second high-density circuit board 32 are independently manufactured and then the high-density circuit region of the electric circuit board is manufactured. Is attached to the multilayer substrate 20, so that if there is a defect in the conductive circuit of the first high-density circuit board 27 and the second high-density circuit board 32, only the first high-density circuit board 27 and the second high-density circuit board 32 are present. Need not be discarded, and the entire multilayer circuit board 40 need not be discarded. Therefore, the production yield rate of the multilayer circuit board 40 can be increased and the production cost can be reduced.

10 回路基板
11 ベース層
12 第一導電回路層
13 第二導電回路層
14 第三導電回路層
15 第一絶縁材料層
16 第四導電回路層
17 第二絶縁材料層
18 導電貫通孔
19 導電ブラインドビア
20 多層基板
21 第一高密度回路領域
22 第一低密度回路領域
23 第二高密度回路領域
24 第二低密度回路領域
25 第一電気接触パッド
26 第二電気接触パッド
27 第一高密度回路基板
28 第一高密度回路層
29 第三絶縁材料層
30 第一導電孔
31 第一テープ
32 第二高密度回路基板
33 第二高密度回路層
34 第四絶縁材料層
35 第二テープ
36 導電粘着層
37 第二導電孔
40 多層回路基板
111 第一表面
112 第二表面
201 第一収容部
202 第二収容部
282 第三電気接触パッド
284 第四電気接触パッド
292 第一溶接防止層
332 第五電気接触パッド
334 第六電気接触パッド
342 第二溶接防止層
361 異方性導電フィルム
362 導電溶接剤
363 溶接防止構造
10 circuit board 11 base layer 12 first conductive circuit layer 13 second conductive circuit layer 14 third conductive circuit layer 15 first insulating material layer 16 fourth conductive circuit layer 17 second insulating material layer 18 conductive through hole 19 conductive blind via 20 multilayer substrate 21 first high density circuit area 22 first low density circuit area 23 second high density circuit area 24 second low density circuit area 25 first electric contact pad 26 second electric contact pad 27 first high density circuit board 28 First High Density Circuit Layer 29 Third Insulating Material Layer 30 First Conductive Hole 31 First Tape 32 Second High Density Circuit Board 33 Second High Density Circuit Layer 34 Fourth Insulating Material Layer 35 Second Tape 36 Conductive Adhesive Layer 37 Second conductive hole 40 Multilayer circuit board 111 First surface 112 Second surface 201 First housing portion 202 Second housing portion 282 Third electrical contact pad 284 Fourth electrical contact pad 292 First weld prevention Layer 332 Fifth electrical contact pads 334 sixth electrical contact pads 342 second weld prevention layer 361 an anisotropic conductive film 362 conductive welding material 363 welded preventing structure

Claims (8)

ベース層と、前記ベース層の一方側の面に形成される第一導電回路層と、前記第一導電回路層の上に順次に交互に積層される複数の第一絶縁材料層及び複数の第三導電回路層と、を備える多層基板を提供するステップと、
複数の前記第一絶縁材料層及び複数の前記第三導電回路層の内部に第一収容部を形成して、一部分の前記第一導電回路層を前記第一収容部から露出させて複数の第一電気接触パッドを構成するステップと、
交互に設置される複数の第一高密度回路層及び複数の第三絶縁材料層を備える第一高密度回路基板を提供し、前記第一高密度回路基板の一方側の最外層の第一高密度回路層は複数の第三電気接触パッドを備え、前記第一高密度回路層の回路密度は前記第一導電回路層の回路密度より大きいステップと、
前記第一高密度回路基板を前記多層基板の第一収容部に設置して、複数の前記第三電気接触パッドを複数の第一電気接触パッドのそれぞれに電気的に接続させて多層回路基板を形成するステップと、
を備えることを特徴とする多層回路基板の製造方法。
A base layer, a first conductive circuit layer formed on one surface of the base layer, a plurality of first insulating material layers and a plurality of first insulating layers sequentially stacked on the first conductive circuit layer Providing a multilayer substrate comprising three conductive circuit layers;
A first housing part is formed inside the plurality of first insulating material layers and the plurality of third conductive circuit layers, and a part of the first conductive circuit layer is exposed from the first housing part to form a plurality of second Configuring an electrical contact pad;
Provided is a first high-density circuit board comprising a plurality of first high-density circuit layers and a plurality of third insulating material layers that are alternately arranged, and a first height of an outermost layer on one side of the first high-density circuit board The density circuit layer comprises a plurality of third electrical contact pads, wherein the circuit density of the first high-density circuit layer is greater than the circuit density of the first conductive circuit layer;
The first high-density circuit board is installed in a first housing portion of the multilayer board, and the plurality of third electrical contact pads are electrically connected to each of the plurality of first electrical contact pads to form a multilayer circuit board. Forming step;
A method for producing a multilayer circuit board, comprising:
前記多層基板は、前記ベース層の一方側の反対側の他方側の面に形成される第二導電回路層と、前記第二導電回路層の上に順次に交互に積層される複数の第二絶縁材料層及び複数の第四導電回路層と、をさらに備えることを特徴とする請求項1に記載の多層回路基板の製造方法。   The multilayer substrate includes a second conductive circuit layer formed on the other side of the base layer opposite to the one side, and a plurality of second conductive layers alternately stacked on the second conductive circuit layer. The method for manufacturing a multilayer circuit board according to claim 1, further comprising an insulating material layer and a plurality of fourth conductive circuit layers. 複数の前記第二絶縁材料層及び複数の前記第四導電回路層の内部に第二収容部を形成して、一部分の前記第二導電回路層を前記第二収容部から露出させて複数の第二電気接触パッドを構成するステップと、
交互に設置される複数の第二高密度回路層及び複数の第四絶縁材料層を備える第二高密度回路基板を提供し、前記第二高密度回路基板の一方側の最外層の第二高密度回路層は複数の第五電気接触パッドを備えるステップと、
前記第二高密度回路基板を前記多層基板の第二収容部に設置して、複数の前記第五電気接触パッドを複数の第二電気接触パッドのそれぞれに電気的に接続させて多層回路基板を形成するステップと、
をさらに備えることを特徴とする請求項2に記載の多層回路基板の製造方法。
A second housing part is formed inside the plurality of second insulating material layers and the plurality of fourth conductive circuit layers, and a part of the second conductive circuit layer is exposed from the second housing part to form a plurality of second Configuring two electrical contact pads;
Provided is a second high-density circuit board comprising a plurality of second high-density circuit layers and a plurality of fourth insulating material layers that are alternately arranged, and a second height of an outermost layer on one side of the second high-density circuit board The density circuit layer comprises a plurality of fifth electrical contact pads;
The second high-density circuit board is installed in a second housing portion of the multilayer board, and the plurality of fifth electrical contact pads are electrically connected to each of the plurality of second electrical contact pads to form the multilayer circuit board. Forming step;
The method for manufacturing a multilayer circuit board according to claim 2, further comprising:
前記第一高密度回路基板及び前記第二高密度回路基板を別々に第一テープ及び第二テープに取り付けた後、前記第一テープ及び前記第二テープを高速チップマウンターに装着して、前記第一高密度回路基板及び前記第二高密度回路基板は、高速チップマウンターによって別々に前記第一収容部及び前記第二収容部に設置されることを特徴とする請求項3に記載の多層回路基板の製造方法。   After the first high-density circuit board and the second high-density circuit board are separately attached to the first tape and the second tape, the first tape and the second tape are attached to a high-speed chip mounter, 4. The multilayer circuit board according to claim 3, wherein the one high-density circuit board and the second high-density circuit board are separately installed in the first housing part and the second housing part by a high-speed chip mounter. Manufacturing method. 前記第一高密度回路基板の前記第三電気接触パッドが所在する一方側の反対側の他方側の最外層の第一高密度回路層は複数の第四電気接触パッドを備え、前記第二高密度回路基板の前記第五電気接触パッドが所在する一方側の反対側の他方側の最外層の第二高密度回路層は複数の第六電気接触パッドを備え、前記第四電気接触パッド及び前記第六電気接触パッドは、電子素子を溶接するために用いられることを特徴とする請求項3に記載の多層回路基板の製造方法。   The first high-density circuit layer of the outermost layer opposite to the one side where the third electrical contact pads of the first high-density circuit board are located includes a plurality of fourth electrical contact pads, The second high-density circuit layer of the outermost layer on the other side opposite to the one side where the fifth electric contact pad of the density circuit board is located includes a plurality of sixth electric contact pads, and the fourth electric contact pad and the fourth electric contact pad The method of manufacturing a multilayer circuit board according to claim 3, wherein the sixth electrical contact pad is used for welding an electronic element. ベース層、前記ベース層の一方側の面に形成される第一導電回路層、前記第一導電回路層の上に順次に交互に積層される複数の第一絶縁材料層及び複数の第三導電回路層を備え、複数の前記第一絶縁材料層及び複数の前記第三導電回路層の内部に第一収容部が形成され、一部分の前記第一導電回路層は前記第一収容部から露出されて複数の第一電気接触パッドを構成する多層基板と、
交互に設置される複数の第一高密度回路層及び複数の第三絶縁材料層を備える第一高密度回路基板であって、前記第一高密度回路層の回路密度は前記第一導電回路層の回路密度より大きく、前記第一高密度回路基板の一方側の最外層の第一高密度回路層は複数の第三電気接触パッドを備え、前記第一高密度回路基板は前記第一収容部に設置されて、複数の前記第三電気接触パッドは複数の第一電気接触パッドのそれぞれに電気的に接続される第一高密度回路基板と、
を備えることを特徴とする多層回路基板。
A base layer, a first conductive circuit layer formed on one surface of the base layer, a plurality of first insulating material layers and a plurality of third conductive layers stacked alternately and sequentially on the first conductive circuit layer A first accommodating portion is formed inside the plurality of first insulating material layers and the plurality of third conductive circuit layers, and a part of the first conductive circuit layer is exposed from the first accommodating portion. A multilayer substrate constituting a plurality of first electrical contact pads;
A first high-density circuit board comprising a plurality of first high-density circuit layers and a plurality of third insulating material layers installed alternately, wherein the circuit density of the first high-density circuit layer is the first conductive circuit layer The first high-density circuit layer on the outermost layer on one side of the first high-density circuit board includes a plurality of third electrical contact pads, and the first high-density circuit board includes the first receiving portion. A plurality of third electrical contact pads are electrically connected to each of the plurality of first electrical contact pads; and
A multilayer circuit board comprising:
前記多層基板は、前記ベース層の一方側の反対側の他方側の面に形成される第二導電回路層と、前記第二導電回路層の上に順次に交互に積層される複数の第二絶縁材料層及び複数の第四導電回路層と、をさらに備え、複数の前記第二絶縁材料層及び複数の前記第四導電回路層の内部に第二収容部が形成され、一部分の前記第二導電回路層は前記第二収容部から露出されて複数の第二電気接触パッドを構成し、
前記多層回路基板は、交互に設置される複数の第二高密度回路層及び複数の第四絶縁材料層を備える第二高密度回路基板をさらに備え、前記第二高密度回路層の回路密度は前記第二導電回路層の回路密度より大きく、前記第二高密度回路基板の一方側の最外層の第二高密度回路層は複数の第五電気接触パッドを備え、前記第二高密度回路基板は前記第二収容部に設置されて、複数の前記第五電気接触パッドは複数の第二電気接触パッドのそれぞれに電気的に接続されることを特徴とする請求項6に記載の多層回路基板。
The multilayer substrate includes a second conductive circuit layer formed on the other side of the base layer opposite to the one side, and a plurality of second conductive layers alternately stacked on the second conductive circuit layer. An insulating material layer and a plurality of fourth conductive circuit layers, wherein a second housing portion is formed inside the plurality of second insulating material layers and the plurality of fourth conductive circuit layers, and a portion of the second conductive layer is formed. The conductive circuit layer is exposed from the second accommodating portion to constitute a plurality of second electrical contact pads,
The multilayer circuit board further includes a second high-density circuit board including a plurality of second high-density circuit layers and a plurality of fourth insulating material layers that are alternately arranged, and the circuit density of the second high-density circuit layer is The second high-density circuit board is larger than the circuit density of the second conductive circuit layer, and the second high-density circuit layer on the outermost layer on one side of the second high-density circuit board includes a plurality of fifth electrical contact pads. The multilayer circuit board according to claim 6, wherein the multi-layer circuit board is installed in the second housing portion, and the plurality of fifth electrical contact pads are electrically connected to each of the plurality of second electrical contact pads. .
前記第一高密度回路基板の前記第三電気接触パッドが所在する一方側の反対側の他方側の最外層の第一高密度回路層は複数の第四電気接触パッドを備え、前記第二高密度回路基板の前記第五電気接触パッドが所在する一方側の反対側の他方側の最外層の第二高密度回路層は複数の第六電気接触パッドを備え、前記第四電気接触パッド及び前記第六電気接触パッドは、電子素子を溶接するために用いられることを特徴とする請求項7に記載の多層回路基板。   The first high-density circuit layer of the outermost layer opposite to the one side where the third electrical contact pads of the first high-density circuit board are located includes a plurality of fourth electrical contact pads, The second high-density circuit layer of the outermost layer on the other side opposite to the one side where the fifth electric contact pad of the density circuit board is located includes a plurality of sixth electric contact pads, and the fourth electric contact pad and the fourth electric contact pad The multilayer circuit board according to claim 7, wherein the sixth electrical contact pad is used for welding an electronic device.
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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012053728A1 (en) * 2010-10-20 2012-04-26 Lg Innotek Co., Ltd. Printed circuit board and method for manufacturing the same
WO2015162768A1 (en) 2014-04-24 2015-10-29 ルネサスエレクトロニクス株式会社 Semiconductor device and method for producing same
CN106469705B (en) * 2015-08-14 2019-02-05 恒劲科技股份有限公司 Package module and its board structure
EP3366092B1 (en) 2015-10-22 2023-05-03 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Using a partially uncured component carrier body for manufacturing component carrier
CN106658967B (en) 2015-10-30 2019-12-20 奥特斯(中国)有限公司 Component carrier with alternating vertically stacked layer structure of different charge density
US11355427B2 (en) * 2016-07-01 2022-06-07 Intel Corporation Device, method and system for providing recessed interconnect structures of a substrate
CN107241857B (en) * 2017-06-27 2019-08-13 华为技术有限公司 A kind of printed circuit board and communication equipment
FR3069127B1 (en) * 2017-07-13 2019-07-26 Safran Electronics & Defense ELECTRONIC CARD COMPRISING BRASED CMS ON BRAZING BEACHES ENTERREES
CN113692112B (en) * 2021-08-30 2023-03-24 维沃移动通信有限公司 Circuit board and manufacturing method thereof
TWI808716B (en) * 2022-04-08 2023-07-11 欣興電子股份有限公司 Circuit board and circuit board module with docking structure and manufacture method of the circuit board

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6281446B1 (en) * 1998-02-16 2001-08-28 Matsushita Electric Industrial Co., Ltd. Multi-layered circuit board and method of manufacturing the same
JP3511982B2 (en) * 2000-06-14 2004-03-29 株式会社村田製作所 Method for manufacturing multilayer wiring board
JP4195619B2 (en) * 2003-01-20 2008-12-10 株式会社フジクラ Multilayer wiring board and manufacturing method thereof
US20060180344A1 (en) * 2003-01-20 2006-08-17 Shoji Ito Multilayer printed wiring board and process for producing the same
JP2006019441A (en) * 2004-06-30 2006-01-19 Shinko Electric Ind Co Ltd Method of manufacturing substrate with built-in electronic substrate
TWI299248B (en) * 2004-09-09 2008-07-21 Phoenix Prec Technology Corp Method for fabricating conductive bumps of a circuit board
KR100895241B1 (en) * 2007-09-10 2009-04-28 삼성전기주식회사 Method for manufacturing substrate for package
KR100890217B1 (en) * 2007-12-20 2009-03-25 삼성전기주식회사 Method for manufacturing pcb
JP4940124B2 (en) * 2007-12-27 2012-05-30 京セラSlcテクノロジー株式会社 Wiring board manufacturing method
WO2009141927A1 (en) * 2008-05-23 2009-11-26 イビデン株式会社 Printed wiring board and method for manufacturing the same
KR101136396B1 (en) * 2010-05-28 2012-04-18 엘지이노텍 주식회사 PCB within cavity and Fabricaring method of the same

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