TWI461135B - Method for fabricating circuit board - Google Patents

Description

Method of making a circuit board

The present invention relates to a method of fabricating a circuit board, and more particularly to a method of fabricating a circuit board or an asymmetric circuit board of an odd number of circuit layers.

With the rapid development of the electronics industry, electronic products continue to be light, thin, short, and small, and printed circuit boards (PCBs) are gradually moving toward high-density interconnection (HDI) process technology.俾 can provide more functions in a smaller space, thus reducing the overall system cost.

In the prior art, the manufacturing method of the circuit board is a double-sided stacking method, which mainly consists of a core board and a build-up structure symmetrical on both sides of the core board. However, the use of the core board leads to an increase in the overall structure thickness, in order to reduce the circuit. The overall thickness of the board, thus developing a single stack. However, the single lamination method is prone to the problem of warpage of the board.

Therefore, the industry is in great need of developing a method of manufacturing a circuit board, which not only reduces the thickness of the board, but also avoids the problem of the board being bent.

The present invention provides a method of making a circuit board, including the following Step: (a) providing a first substrate, a second substrate, and a release carrier, wherein the release carrier includes a working area and an outer frame area, wherein the outer frame area surrounds the working area; Bonding the first substrate, the second substrate, and the release carrier such that the release carrier is formed between the first substrate and the second substrate; (c) forming a first build-up structure Forming a second build-up structure on the second substrate; (d) cutting the outer frame region to separate the first substrate and the second substrate from the release carrier; And (e) removing the off-load carrier to obtain two circuit boards, one of which is a combination of the first substrate and the first build-up structure, and the other is the second substrate and the second build-up layer A combination of structures.

10‧‧‧ Temporary substrate

12‧‧‧First buildup structure

22‧‧‧Second layered structure

100, 100a‧‧‧ first substrate

102‧‧‧ first central level

102a‧‧‧ first surface

102b‧‧‧second surface

104, 104a‧‧‧ first metal layer

106, 106a‧‧‧First internal circuit layer

110‧‧‧First conductive blind hole

121‧‧‧ dielectric layer

122‧‧‧ Conductive blind holes

123, 123a‧‧‧ first external circuit layer

150‧‧‧ core board

200, 200a‧‧‧ second substrate

202‧‧‧ second central layer

202a‧‧‧ third surface

202b‧‧‧Fourth surface

204‧‧‧Second metal layer

206, 206a‧‧‧Second internal circuit layer

210‧‧‧Second conductive blind hole

221‧‧‧ dielectric layer

222‧‧‧ Conductive blind holes

223‧‧‧Second external circuit layer

250‧‧‧ core board

300‧‧‧Distracted carrier

300a‧‧‧Working area

300b‧‧‧Outer frame area

400, 500‧‧‧ circuit boards

AA’, BB’, CC’, DD’‧‧ ‧ cutting road

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic view showing the elements required in the method of fabricating the circuit board of the present invention.

2A-2E are a series of cross-sectional views for explaining the flow of a first embodiment of the present invention.

The 2D' diagram is a plan view of the 2D diagram.

3A-3E are a series of cross-sectional views for explaining the flow of a second embodiment of the present invention.

Referring to the schematic of Figure 1, this figure shows the components required in the method of making the circuit board of the present invention. As shown in FIG. 1, first, a first substrate 100 and a second substrate 200 are provided, and a release carrier 300 is provided, wherein the release carrier 300 includes a working area 300a and an outer frame area 300b. The outer frame area 300b surrounds the work area 300a.

It should be noted that the final required circuit board product is formed in the "working area 300a", and the subsequent step will remove the outer frame area 300b. Therefore, those skilled in the art can adjust the working area 300a and the outer frame according to the needs of the actual application. The size of the area 300b.

Please refer to FIG. 2A-2E, which shows steps (a) to (e) of the process stages of the circuit board of the present invention.

Referring to FIG. 2A, step (a) is performed, wherein the first substrate 100 includes a first central layer 102, a first metal layer 104, a first internal wiring layer 106 and a first blind via 110, wherein the first central layer 102 has The first surface 102a and the corresponding second surface 102b, and the second surface 102b faces the off-load carrier 300. The first surface 102a has a first inner wiring layer 106, and the second surface 102b has a first metal layer 104. The first inner wiring layer 106 is electrically connected to the first metal layer 104 by the first blind via 110.

The material of the first central layer 102 is an insulating material such as a paper phenolic resin, a composite epoxy, a polyimide resin or a glass fiber.

The second substrate 200 includes a second center layer 202, a second metal layer 204, a second inner wiring layer 206, and a second blind hole 210, wherein the second center layer 202 has a third surface 202a and a corresponding fourth surface 202b, and The fourth surface 202b faces the off-load carrier 300. The second surface 202a has a second internal wiring layer 206. The fourth surface 202b has a second metal layer 204. The second internal wiring layer 206 is electrically connected to the second via hole 210. Two metal layers 204.

It should be noted that both the first substrate 100 and the second substrate 200 are double-sided substrates, and both have the same thickness. The so-called "double-sided substrate" means that both sides of the substrate have a metal layer, and a wiring layer can be formed through a patterning step to provide line transfer. The first metal layer 104 and the second metal layer 204 are metal layers of the entire layer, which have not been patterned.

The manufacturing process of the first substrate 100 is as follows. First, a double-sided copper foil substrate is provided, and a metal layer (for example, a copper foil) can be formed by a conventional sputtering, laminating or coating process. On the center floor. Thereafter, holes are formed in the double-sided copper foil substrate via a laser drilling method. The conductive material is then filled into the holes by an electroplating process to form conductive vias. Next, an image transfer process is performed to form the first inner wiring layer 106 on the first surface 102a of the first central layer 102. The second substrate 200 is formed in the same manner as the first substrate 100, and details are not described herein again.

Referring to FIG. 2B, step (b) is performed to bond the first substrate 100, the second substrate 200, and the release carrier 300 such that the release carrier 300 is formed between the first substrate 100 and the second substrate 200.

The material of the outer frame region 300b of the release carrier 300 includes a glue material, such as a fiberglass resin (abbreviated as PP), which functions to bond the first substrate 100 and the second substrate 200, and the rubber material passes through a pressing step. The flow range is from 0.1 mm to 5.0 mm to avoid excessive diffusion of the glue.

In addition, since the first metal layer 104 on the second surface 102b of the first central layer 102 is not patterned, the first gold can be The genus layer 104 bonds the outer frame region 300b and the first substrate 100.

The material of the working area 300a of the release carrier 300 includes a copper-free substrate, a copper substrate or a metal layer, and functions to support the first substrate 100 and the second substrate 200, and does not overlap with the first substrate 100 and the second substrate. 200 bonding.

However, the material of the work area 300a is not limited to the above-mentioned materials as long as it is not the first metal layer 104 on the second surface 102b of the first center layer 102 (or the fourth surface 202b of the second center layer 202). The upper second metal layer 204) can be used to produce a bonded and supportive material.

Referring to FIG. 2C, step (c) is performed to form a first build-up structure 12 over the first substrate 100 and a second build-up structure 22 over the second substrate 200 to form the temporary substrate 10. The first build-up structure 12 includes one or more layers of structure.

In FIG. 2C, the first build-up structure 12 includes: a dielectric layer 121; a conductive via 122 is formed in the dielectric layer 121; a first external circuit layer 123 is formed on the dielectric layer 121, wherein the first external line The layer 123 is electrically connected to the first inner wiring layer 106 by the conductive vias 122.

In another embodiment, the first build-up structure 12 includes a multi-layer structure including at least one dielectric layer 121; at least one conductive via 122 is formed in the dielectric layer; at least one first external circuit layer 123 is formed. On the dielectric layer 121, the first external circuit layer 123 is electrically connected to the first internal circuit layer 106 by the conductive vias 122.

The second build-up structure 22 includes: a dielectric layer 221; a conductive blind hole The second outer circuit layer 223 is formed on the dielectric layer 221 , and the second outer circuit layer 223 is electrically connected to the second inner circuit layer 206 via the conductive via 222 .

In another embodiment, the second build-up structure 22 includes a multi-layer structure including at least one dielectric layer 221; at least one conductive via 222 is formed in the dielectric layer; at least one second external trace layer 223 is formed. On the dielectric layer 221 , the second external circuit layer 223 is electrically connected to the second internal wiring layer 206 by the conductive blind vias 222 .

It should be noted that only one layer of the first build-up structure 12 and one layer of the second build-up structure 22 are shown in FIG. 2C. However, in other embodiments, a multi-layer build-up structure may also be formed. The thickness of the first build-up structure 12 is equal to the thickness of the second build-up structure 22, and therefore, when the build-up step is performed, the thickness of the two sides is symmetric, so that the board does not suffer from the problem of warpage of the board.

In one embodiment, the step of forming the build-up structure is as follows, forming an insulating layer (eg, fiberglass resin (PP)) over the first substrate 100 (or the second substrate). Thereafter, a metal layer (for example, a copper foil) is formed on the insulating layer to be pressed. Finally, drilling is performed (laser drilling or mechanical drilling can be used) to form holes to form a comprehensive conductive layer. Thereafter, a patterned dry film is formed, and finally the holes are filled and patterned to form a pattern, after which the dry film is removed.

In another embodiment, the step of forming the build-up structure is as follows. An insulating layer (for example, an ABF film) is formed on the first substrate 100 (or the second substrate) to perform a pressing step. Next, drill holes (laser drilling or mechanical drilling). After that, the holes are plated and patterned to form a dry film. After etching to form a line, the dry film is finally removed.

Referring to FIG. 2D, performing step (d), performing a cutting step on the temporary substrate 10, cutting along the tangential tracks AA' and BB' of the outer frame region 300b, so that the first substrate 100 and the second substrate 200 are separated from each other. The shaped carrier plate 300 is separated. Since the working area 300a of the release carrier 300 does not adhere to the first substrate 100 or the second substrate 200, it can be easily removed when the viscous outer frame region 300b is cut. Detached carrier plate 300.

2D' is a plan view showing the 2D view, and it can be seen from the figure that the cutting is performed along the scribe lines AA', BB', CC', DD' to make the first substrate 100, the second substrate 200 and the off-shape The carrier plate 300 is separated.

Referring to FIG. 2E, after the off-load carrier 300 is removed, two circuit boards 400 can be respectively obtained. The two circuit boards 400 are symmetrical to each other, and one of the two circuit boards 400 is the first substrate 100 and the first One combination of the build-up structures 12 and the other is a combination of the second substrate 200 and the second build-up structure 22. To simplify the description, only one circuit board 400 is shown in FIG. 2E, including the first substrate 100 and the first build-up structure 12 thereon.

Thereafter, a patterning step may be performed on the first metal layer 104 on the second surface 102b of the first central layer 102 and the first outer wiring layer 123 on the outermost layer of the first buildup structure 22.

In the first embodiment of the present invention, since the first substrate 100 and the second substrate 200 have the same thickness, and the first build-up structure 12 and the second build-up structure 22 have the same thickness, the plate warp can be avoided ( Warpage) problem. In addition, since the off-load carrier 300 is finally removed, the overall thickness of the board can be reduced to meet the trend of miniaturization.

In addition, it is conventional to use a double-sided lamination method to obtain only a circuit layer of an even layer (for example, two layers, four layers, six layers, eight layers, etc.), and by the manufacturing method of the present invention, an odd-numbered layer circuit layer can be obtained. The circuit board 400, as in FIG. 2E, obtains a circuit board 400 of three circuit layers (a first metal layer 104, a first internal wiring layer 106, and a first external wiring layer 123).

The present invention further provides a second embodiment, please refer to FIGS. 3A-3E, which show steps (a) to (e) of the process stages of the circuit board of the present invention. The reference numerals in the 3A to 3E drawings are the same as those in the second A-2E, and represent the same components. For the sake of simplicity, the description will not be repeated here.

It should be noted that in the first embodiment, in the second embodiment, the first substrate 100 and the second substrate 200 are both double-sided substrates (metal layers on both sides). In the second embodiment, in the third embodiment, the first substrate 100 and the second substrate 200 are both multi-layer substrates, the number of layers is not limited, and the first substrate 100 includes the core board 150 (the core board 150 is located in the multi-layer substrate) The central position of the second substrate 200 also includes a core plate 250 (the core plate 250 is located at a central position in the multilayer substrate). The term "core board" as used herein refers to a copper foil substrate.

Referring to FIG. 3A, step (a) is performed to provide a first substrate 100a, a second substrate 200a and a release carrier 300, wherein the release carrier 300 includes a working area 300a and an outer frame area 300b, wherein the outer frame area 300b Surrounds the work area 300a.

It should be noted that the first substrate 100a is a multilayer substrate having a multilayer wiring structure, and a four-layer wiring layer is shown in FIG. 3A, and includes a core board 150. Similarly, the second substrate 200a is a plurality of layers The substrate, which has a multilayer wiring structure, shows a four-layer wiring layer in FIG. 3A, and includes a core board 250.

Referring to FIG. 3B, step (b) is performed to bond the first substrate 100a, the second substrate 200a and the release carrier 300 such that the release carrier 300 is formed between the first substrate 100a and the second substrate 200a.

Referring to FIG. 3C, step (c) is performed to form a first build-up structure 12 over the first substrate 100a to form a second build-up structure 22 over the second substrate 200a.

The first build-up structure 12 includes at least one dielectric layer 121; at least one conductive via 122 is formed in the dielectric layer; at least one first external trace layer 123 is formed on the dielectric layer 121, wherein the first external trace layer 123 The conductive inner via layer 106a is electrically connected to the first inner wiring layer 106a.

The second build-up structure 22 includes at least one dielectric layer 221; at least one conductive via 222 is formed in the dielectric layer; at least one second external trace layer 223 is formed on the dielectric layer 221, wherein the second external trace layer 223 The conductive via 222 is electrically connected to the second internal wiring layer 206a.

It should be noted that the first build-up structure 12 includes at least one build-up structure, the second build-up structure 22 includes at least one build-up structure, and the third build-up structure 12 and two layers of the second layer are shown in FIG. 3C. Layering structure 22. The number of the first build-up structure 12 and the second build-up structure 22 are the same, and those skilled in the art can adjust the number of build-up structures according to the needs of practical applications.

Referring to FIG. 3D, step (d) is performed to cut the outer frame region 300b along the scribe lines AA' and BB' to make the first substrate 100a and the second substrate. The 200a is separated from the off-load carrier 300.

Referring to FIG. 3E, step (e) is performed to remove the off-load carrier 300 to obtain two circuit boards 500 respectively. The two circuit boards 500 are symmetrical to each other, and one of the two circuit boards 500 is One substrate 100a is combined with the first build-up structure 12, and the other is a combination of the second substrate 200a and the second build-up structure 22. To simplify the description, only one circuit board 500 is shown in FIG. 3E, including the first substrate 100a and the two first layer buildup structures 12 thereon.

Thereafter, a patterning step may be performed on the first metal layer 104a on the second surface 102b of the first central layer 102 and the first outer wiring layer 123a on the outermost layer of the first buildup structure 22.

Conventionally, when a circuit board is fabricated using a double-sided stacking method, the core board must be positioned at a center position, that is, only a symmetrical circuit board can be fabricated (the core substrate is at the center). It should be noted that, in the second embodiment of the present invention, by using the method of the present invention, in the third embodiment, the first metal layer 104a has a total of six circuit layers, wherein the core board 150 is located in the second embodiment. Between the third circuit layers, therefore, an asymmetric circuit board 500 is fabricated (the core board is not centered).

100‧‧‧First substrate

200‧‧‧second substrate

300‧‧‧Distracted carrier

300a‧‧‧Working area

300b‧‧‧Outer frame area

Claims (14)

A method of manufacturing a circuit board, comprising the steps of: (a) providing a first substrate, a second substrate, and a release carrier, wherein the release carrier includes a working area and a frame area, wherein the outer frame The frame area surrounds the working area, wherein the first substrate comprises a double-sided substrate, the first substrate has a corresponding one of the first surface and a second surface, the second surface faces the off-load carrier, wherein the first surface a surface having a first inner wiring layer having a first metal layer thereon, and the first metal layer is unpatterned, wherein the second substrate comprises a double-sided substrate, and the second substrate has a phase Corresponding to one of the third surface and the fourth surface, the fourth surface facing the release carrier, wherein the third surface has a second internal line having a second metal layer thereon, And the second metal layer is not patterned; (b) bonding the first substrate, the second substrate, and the release carrier to form the release carrier on the first substrate and the second substrate (c) forming a first buildup structure Forming a second build-up structure on the second substrate; (d) cutting the outer frame region to separate the first substrate and the second substrate from the release carrier; And (e) removing the off-load carrier to obtain two circuit boards, one of which is a combination of the first substrate and the first build-up structure, and the other is the second substrate and the second build-up layer A combination of structures. The method of manufacturing a circuit board according to claim 1, wherein the material of the outer frame region of the release carrier comprises a glue. The method for manufacturing a circuit board according to the second aspect of the invention, wherein the glue material has a flow range of 0.1 mm to 5.0 mm after a pressing step. The method of manufacturing a circuit board according to claim 1, wherein the material of the working area of the release carrier comprises a copper-free substrate, a copper substrate or a metal layer. The method of manufacturing a circuit board according to claim 1, wherein the first build-up structure is formed on the first surface of the first substrate. The method of fabricating a circuit board according to claim 5, wherein the first build-up structure comprises one or more layers. The method of fabricating a circuit board according to claim 5, wherein the first build-up structure comprises: at least one dielectric layer; at least one conductive via hole formed in the dielectric layer; at least one external circuit layer Formed on the dielectric layer, wherein the external circuit layer is electrically connected to the first internal circuit layer by the conductive blind via. The method of manufacturing a circuit board according to claim 1, wherein the second build-up structure is formed on the third surface of the second substrate. The method of fabricating a circuit board of claim 8, wherein the second build-up structure comprises one or more layers. The method of fabricating a circuit board according to claim 8, wherein the second build-up structure comprises: at least one dielectric layer; at least one conductive blind hole formed in the dielectric layer; At least one external circuit layer is formed on the dielectric layer, wherein the external circuit layer is electrically connected to the third internal circuit layer by the conductive blind via. The method of manufacturing a circuit board according to claim 1, wherein the thickness of the first substrate is the same as the thickness of the second substrate. The method of manufacturing a circuit board according to claim 1, wherein the thickness of the first build-up structure is the same as the thickness of the second build-up structure. The method of manufacturing a circuit board according to claim 1, wherein the first substrate and the second substrate comprise a multi-layer substrate, and the multi-layer substrate comprises a core. The method of manufacturing a circuit board according to claim 13, wherein after the step (e), the circuit board is an asymmetric circuit board.