CN116507048A

CN116507048A - Circuit board forming method and circuit board

Info

Publication number: CN116507048A
Application number: CN202310767404.2A
Authority: CN
Inventors: 盛凤阳; 郭健强; 滕少磊
Original assignee: Honor Device Co Ltd
Current assignee: Honor Device Co Ltd
Priority date: 2023-06-27
Filing date: 2023-06-27
Publication date: 2023-07-28

Abstract

The application relates to the technical field of circuit boards and discloses a circuit board forming method and a circuit board. The method comprises the following steps: arranging a carrier, wherein the carrier comprises two conductor layers which are stacked, and the opposite surfaces of the two conductor layers are bonded through bonding glue; forming a build-up structure on the surface of the at least one conductor layer facing away from the bonding adhesive; debonding the two conductor layers to obtain a prefabricated plate, wherein the prefabricated plate comprises a layer-adding structure and a conductor layer connected with the layer-adding structure; and obtaining the circuit board according to the prefabricated board. The circuit board forming method can effectively reduce the mechanical stress to be overcome in the separation process, reduce the stripping difficulty of the conductor layer, further reduce the forming difficulty of the circuit board and improve the yield of the circuit board.

Description

Circuit board forming method and circuit board

Technical Field

The application relates to the technical field of circuit boards, in particular to a circuit board forming method and a circuit board.

Background

With the trend of thinning electronic devices, the thickness of circuit boards in electronic devices needs to be further reduced. In some technical solutions, the thinning may be performed by reducing the number of layers of the circuit board, manufacturing the substrate of the circuit board by using low-specification glass fibers (for example, glass fibers with specifications of 1027-1017), or reducing the thickness of the metal layer, etc. However, these methods do not meet both the thinning requirements and the operating requirements of the circuit board (e.g., signal integrity and insertion loss control, characteristic impedance, and routing layout, etc.) well.

In addition, the current method for forming the thin circuit board generally uses copper clad laminate (copper clad laminate, CCL) as a carrier. The copper-clad plate comprises a first base copper foil layer and a first carrier copper foil layer which are bonded with each other. And pressing a second copper foil layer on the first carrier copper foil layer, manufacturing a circuit pattern, and finally separating the first base copper foil layer from the first carrier copper foil layer to obtain the circuit board. However, since the first base copper foil layer and the first carrier copper foil layer are bonded to each other, the first base copper foil layer and the first carrier copper foil layer are difficult to separate, resulting in a difficulty in molding the circuit board.

Disclosure of Invention

In order to solve the above technical problems, the present application provides a circuit board forming method and a circuit board, and the following description will be made in terms of the present application, and the following embodiments and beneficial effects of the following aspects may be referred to each other.

The first aspect of the application provides a circuit board forming method, which comprises the following steps: the carrier is arranged, wherein the carrier comprises two conductor layers which are stacked, and the opposite surfaces of the two conductor layers are bonded through bonding glue. And forming a build-up structure on the surface of the at least one conductor layer facing away from the bonding adhesive. And (3) de-bonding the two conductor layers to obtain a prefabricated plate, wherein the prefabricated plate comprises a layer-adding structure and the conductor layers connected with the layer-adding structure. And obtaining the circuit board according to the prefabricated board.

It is to be understood that the above two conductor layers may be the first conductor layer and the second conductor layer mentioned in the later-described embodiments, respectively.

The carrier provided by the circuit board forming method comprises two conductor layers. The two conductor layers are bonded and unbuckled through temporary bonding and unbuckling technologies, so that the mechanical stress required to be overcome in the separation process of the two conductor layers can be reduced, the stripping difficulty of the two conductor layers is reduced, the forming difficulty of the circuit board is further reduced, and the yield of the circuit board is improved.

In addition, the two conductor layers can play a supporting role in the forming process of the circuit board and can also be used as a component structure of the circuit board, so that the waste of carriers can be avoided, and the manufacturing cost of the circuit board is reduced.

In one possible implementation of the first aspect, the conductor layer includes a first metal layer, and a build-up structure is formed on a surface of the at least one conductor layer facing away from the bonding glue, including:

pressing the second metal layer on one side of the first metal layer, which is opposite to the bonding adhesive, through the first insulating layer;

and manufacturing a circuit pattern on the second metal layer.

In a possible implementation manner of the first aspect, a build-up structure is formed on a surface of the at least one conductor layer facing away from the bonding glue, and the method further includes: and pressing the third metal layer on one side of the second metal layer, which is opposite to the bonding adhesive, through the second insulating layer.

In a possible implementation manner of the first aspect, a build-up structure is formed on a surface of the at least one conductor layer facing away from the bonding glue, and the method further includes: and manufacturing a circuit pattern on the third metal layer, and manufacturing a metallized via hole on the second metal layer, the second insulating layer and the third metal layer, wherein the metallized via hole passes through the second insulating layer to communicate the second metal layer and the third metal layer.

In a possible implementation manner of the first aspect, the conductor layer includes a first metal layer, a first insulating layer, and a second metal layer that are sequentially stacked along a direction away from the bonding glue;

forming a build-up structure on a surface of the at least one conductor layer facing away from the bond paste comprises:

manufacturing a circuit pattern on the second metal layer;

pressing the third metal layer on one side of the second metal layer, which is opposite to the bonding adhesive, through the second insulating layer;

and manufacturing a circuit pattern on the third metal layer, and manufacturing a metallized via hole on the second metal layer, the second insulating layer and the third metal layer, wherein the metallized via hole passes through the second insulating layer to communicate the second metal layer and the third metal layer.

According to the method for forming the build-up structure, the circuit patterns can be firstly manufactured on the metal layer of the conductor layer, then the insulating layers and other metal layers are alternately laminated on the metal layer, so that the build-up structure is formed, the step of laminating the metal layers can be reduced, and the forming efficiency of the build-up structure is further improved.

In a possible implementation manner of the first aspect, the debonding manner of the two conductor layers includes any one of the following: thermal decomposition, laser bonding and chemical bonding.

The above-mentioned deblocking mode can effectively reduce the mechanical stress that needs to overcome in the separation process, reduces the degree of difficulty that the conductor layer separated, and then reduces the fashioned degree of difficulty of circuit board, promotes the yields of circuit board.

A second aspect of the present application provides a method for forming a circuit board, the method comprising: the carrier is arranged, the carrier comprises at least one conductor layer and a reinforcing layer which are overlapped, and the surfaces of the conductor layer and the reinforcing layer, which are opposite, are bonded through bonding glue. And forming a build-up structure on the surface of the conductor layer facing away from the bonding adhesive. And (3) de-bonding the bonding glue between the conductor layer and the reinforcing layer to obtain a prefabricated plate, wherein the prefabricated plate comprises a layer-added structure and a conductor layer connected with the layer-added structure. And obtaining the circuit board according to the prefabricated plate.

It is understood that the above-mentioned at least one conductor layer may be the first conductor layer and the second conductor layer mentioned in the later-described embodiments.

The carrier provided by the circuit board forming method comprises at least one conductor layer and a reinforcing layer which are arranged in a stacked manner. The bonding and the unbinding are realized through a temporary bonding and unbinding technology between the conductor layer and the reinforcing layer, so that the mechanical stress between the conductor layer and the reinforcing layer in the separation process can be effectively reduced, and the forming difficulty of the circuit board is further reduced. Meanwhile, the strength of the carrier can be further increased by the reinforcing layer, so that the carrier can play a better supporting role.

In a possible implementation of the second aspect, the number of conductor layers is two, and the reinforcement layer is disposed between the two conductor layers along the lamination direction of the carrier. So that the strength of the carrier can be further increased, so that the carrier can better play a supporting role.

In a possible implementation of the second aspect, the reinforcement layer is a prepreg.

In one possible implementation manner of the first aspect and the second aspect, along a stacking direction of the carrier, a ratio between an area of projection of the bonding adhesive in the first plane and an area of projection of the conductor layer in the first plane is 0.8-1, where the first plane intersects the stacking direction of the carrier.

It is understood that the lamination direction of the above-described carriers may be the a direction mentioned in the later-described embodiments. The first plane may be perpendicular to the stacking direction of the carrier.

The bonding glue is arranged in a mode, so that the coating range of the bonding glue is larger, the strength of the carrier is effectively improved, and the carrier is ensured to have better supporting effect. For example, the ratio between the projected area of the bond paste in the first plane and the projected area of the conductor layer in the first plane may be 0.8. For another example, the ratio between the projected area of the bonding paste in the first plane and the projected area of the conductor layer in the first plane may also be 0.9. For another example, the ratio between the projected area of the bonding glue in the first plane and the projected area of the conductor layer in the first plane may also be 1.

In a possible implementation of the above first and second aspects, along a lamination direction of the carrier, a projection area of the bonding glue in the first plane is located at an edge of the projection area of the conductor layer in the first plane, wherein the first plane intersects the lamination direction of the carrier. Thus, the difficulty of bond knowing is reduced while the stability of bond is ensured.

A third aspect of the present application provides a method for forming a circuit board, the method comprising: the carrier is arranged, the carrier comprises two conductor layers which are overlapped, wherein the opposite surfaces of the two conductor layers are connected through a connecting part, and along the overlapping direction of the carrier, a projection area of the connecting part in a first plane is positioned at the edge of the projection area of the conductor layer in the first plane, and the first plane is intersected with the overlapping direction of the carrier. And forming a build-up structure on the surface of the at least one conductor layer facing away from the connection part. And cutting off the connecting part to obtain the prefabricated plate, wherein the prefabricated plate comprises a layer-adding structure and a conductor layer connected with the layer-adding structure. And obtaining the circuit board according to the prefabricated board.

The carrier provided by the circuit board forming method comprises two conductor layers which are arranged in a laminated mode. The two opposite surfaces of the two conductor layers are fixedly connected through the connecting part, under the condition that the two conductor layers are fixedly connected, a layer-adding structure is formed on at least one conductor layer, and then the connecting part is cut off to separate the two conductor layers, so that a prefabricated plate is obtained, and a circuit board is obtained according to the prefabricated plate. Therefore, the problem of mechanical stress between the two conductor layers in the separation process is effectively avoided, and the forming difficulty of the circuit board is further reduced.

In a possible implementation of the third aspect, the cutting away the connection portion includes: and cutting off the area occupied by the connecting part, and along the superposition direction of the carrier, the area occupied by the projection of the connecting part on the conductor layer and the build-up structure.

In one possible implementation manner of the third aspect, along a stacking direction of the carrier, a ratio between an area of projection of the connection portion in the first plane and an area of projection of the conductor layer in the first plane is 0.2 to 0.5.

In this way, the cut-out parts can be reduced, unnecessary waste is avoided, and meanwhile, the stability of combination between the two conductor layers can be ensured, so that the carrier can better provide supporting force. For example, the ratio between the projected area of the connection portion in the first plane and the projected area of the conductor layer in the first plane may be 0.2. For another example, the ratio between the projected area of the connection portion in the first plane and the projected area of the conductor layer in the first plane may be 0.3. For another example, the ratio between the projected area of the connection portion in the first plane and the projected area of the conductor layer in the first plane may also be 0.4.

In a possible implementation of the third aspect, the connection portion includes a prepreg or a bonding adhesive.

In a possible implementation of the first, second and third aspects, the conductor layer is a metal layer or a copper-clad plate.

A fourth aspect of the present application provides a circuit board molded by any one of the above-described first aspect, the possible implementation of the first aspect, the second aspect, the possible implementation of the second aspect, the third aspect and the possible implementation of the third aspect.

In one possible implementation of the fourth aspect, the circuit board includes a buried hole, and the aperture of the buried hole gradually increases or gradually decreases in a thickness direction of the circuit board.

The fifth aspect of the present application provides a circuit board, which includes a metal layer, an insulating layer and a buried hole, wherein the metal layer and the insulating layer are alternately laminated in sequence, the buried hole is communicated with the two metal layers, and the aperture of the buried hole is gradually increased or gradually decreased along the thickness direction of the circuit board.

Drawings

Fig. 1A shows a perspective view of a mobile phone according to an embodiment of the present application;

FIG. 1B shows an exploded view of a mobile phone in an embodiment of the present application;

fig. 2 shows a schematic structural diagram of a circuit board in some embodiments;

Fig. 3 is a schematic structural diagram of a circuit board in a mobile phone according to an embodiment of the present application;

fig. 4A shows a schematic diagram of a circuit board in some embodiments;

fig. 4B illustrates a second schematic diagram of circuit board fabrication in some embodiments;

fig. 5 shows a flowchart of a method for forming a circuit board according to an embodiment of the present application;

fig. 6 is a schematic diagram illustrating molding of a circuit board according to an embodiment of the present application according to fig. 5;

fig. 7 is a schematic diagram illustrating a second molding diagram of the circuit board according to the embodiment of the application according to fig. 5;

FIG. 8 illustrates a schematic diagram of applying a bonding paste on a first conductor layer in some embodiments of the present application;

FIG. 9A illustrates an exploded view of a carrier according to some embodiments of the present application, in accordance with FIG. 8;

FIG. 9B illustrates a side view of a carrier according to some embodiments of the present application, in accordance with FIG. 8;

FIG. 10 is a schematic illustration of a bonding paste applied to a first conductor layer in some other embodiments of the present application;

FIG. 11A is an exploded view of a carrier according to some other embodiments of the present application, according to FIG. 10;

FIG. 11B illustrates a side view of a carrier according to FIG. 10 in some other embodiments of the present application;

FIG. 12A illustrates a schematic diagram of debonding a first conductor layer and a second conductor layer in some embodiments of the present application;

FIG. 12B is a schematic diagram illustrating debonding of a first conductor layer and a second conductor layer in other embodiments of the present application;

FIG. 13 illustrates a flow chart of forming a first build-up structure on a first conductor layer in some embodiments of the present application;

FIG. 14A illustrates a schematic diagram of forming a first build-up structure on a first conductor layer in some embodiments of the present application;

FIG. 14B illustrates a second schematic diagram of forming a first build-up structure on a first conductor layer in some embodiments of the present application;

FIG. 14C illustrates a third schematic diagram of forming a first build-up structure on a first conductor layer in some embodiments of the present application;

fig. 15 is a schematic structural view of a first conductor layer according to other embodiments of the present application;

fig. 16 is a flow chart illustrating formation of a first build-up structure on a first conductor layer in further embodiments of the present application;

fig. 17 shows a second flowchart of a method for forming a circuit board according to an embodiment of the present application;

FIG. 18 shows a schematic view of the formation of a carrier in an embodiment of the present application;

fig. 19 shows a flowchart III of a method for forming a circuit board in an embodiment of the present application;

FIG. 20 shows a schematic view of a connection in an embodiment of the present application;

fig. 21 shows a schematic view of a cut-away connection in an embodiment of the present application.

Reference numerals illustrate: 1-a mobile phone; 10-a display screen; 20-a housing; 21-an accommodation space; 30-a functional device; 40-a circuit board; 41-a metal layer; 41 a-41 h-a metal layer; 411-line pattern; 4111 a-411 d-line patterns; 412-metallizing the via; 412 a-412 c-metallized vias; 42-an insulating layer; 42 a-42 f-an insulating layer; 43-build-up structure; 43 a-first build-up structure; 43 b-a second build-up structure; a 40' -circuit board; 41' -metal layer; 42' -insulating layer; 43' -core plate; 50-carrier; 51 a-a first conductor layer; 51 b-a second conductor layer; 52-bonding glue; 53-a reinforcing layer; 54-connection; 50 "-vector; 51'' -a first copper foil; 511 "-a first base copper foil; 512 "-a first carrier copper foil; 52 "-a first prepreg; 40 "-circuit board; 41 "-a first circuit pattern; 42 "-second prepreg; 43 "-a second copper foil; 44 "-a second circuit pattern; 60'' -prefabricated panels; 60-prefabricated panels; 60 a-a first prefabricated panel; 60 b-a second prefabricated panel; 70-a heat source; 80-a transparent carrier plate; 81-a layer of photosensitive responsive material; s1-a first plane; s2, a region to be processed.

Description of the embodiments

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

The application provides a circuit board which can be applied to electronic equipment. Specifically, the electronic device includes, but is not limited to, any one of a mobile phone, a tablet computer (tablet personal computer, TPC), an electronic book reader, a Laptop (LC), a personal digital assistant (personal digital assistant, PDA), a personal computer, a notebook (notebook), a vehicle-mounted device, a wearable device (e.g., a watch), a box, and the like, which have a circuit board, which is not particularly limited in this application.

For convenience of explanation, the electronic device is taken as an example of a mobile phone, and the mobile phone of the present application is described in the following specific embodiments.

Fig. 1A shows a perspective view of a mobile phone 1 in an embodiment of the present application. Fig. 1B shows an exploded view of the mobile phone 1 in the embodiment of the present application. Referring to fig. 1A and 1B, in some embodiments of the present application, a mobile phone 1 includes a display 10, a housing 20, a functional device 30, and a circuit board 40. The display screen 10 and the housing 20 can jointly enclose a receiving space 21. The functional device 30 and the circuit board 40 are both located in the accommodation space 21.

Wherein the functional device 30 is configured to implement one or more functions of the handset 1. The functional device 30 may include, but is not limited to, any one or more of a camera module, a display screen, a speaker, a receiver, an antenna, a microphone, a universal serial bus (universal serial bus, USB) interface, a subscriber identity module (subscriber identification module, SIM) card interface, keys, etc.

The circuit board 40 may be electrically connected to the functional device 30 to perform signal control, data signal processing, and data signal storage operations on the functional device 30. The circuit board 40 may be a motherboard of the mobile phone 1, or other circuit board. For example, the circuit board 40 may be a circuit board for carrying a speaker (not shown) or a USB interface (not shown) in the mobile phone 1, which is not particularly limited in this application.

It should be noted that, in each of the drawings, the dashed line is only for indication, and does not represent a specific structural feature, which will not be described in detail below.

Fig. 2 shows a schematic structural diagram of a circuit board 40' according to some embodiments. Referring to fig. 2, in some aspects, the circuit board 40 'includes a metal layer 41', an insulating layer 42', and a core (core) 43'. The metal layers 41 'are laminated on the two plate surfaces of the core plate 43'. Also, in the a direction, the insulating layer 42' is located between two adjacent metal layers 41' on the same side of the core plate 43'. The core plate 43' serves as a substrate capable of supporting the metal layer 41' and the insulating layer 42'.

To meet the above requirements for light and thin mobile phone 1, the circuit board 40' needs to be further thinned. In some implementations, the circuit board 40 'may be thinned by reducing the number of layers of the circuit board 40' (e.g., reducing the number of metal layers 41 'and insulating layers 42'), making the core board 43 'from low gauge fiberglass (e.g., fiberglass of gauge 1027-1017), or reducing the thickness of the metal layers 41'. However, the requirements of the wiring layout, signal integrity, insertion loss control, and characteristic impedance of the circuit board 40 'cannot be satisfied, and the working performance of the circuit board 40' is further affected.

In order to solve the above-mentioned problem that the thinning requirement and the working requirement of the circuit board cannot be met at the same time, the application provides a circuit board, which is a coreless circuit board. That is, the circuit board includes only the metal layers and the insulating layers alternately stacked, and does not include the core board. The following is a detailed description with reference to the accompanying drawings.

Fig. 3 shows a schematic structural diagram of the circuit board 40 in the mobile phone 1 according to the embodiment of the present application. Referring to fig. 3, the circuit board 40 includes a metal layer 41 and an insulating layer 42. Wherein, the metal layer 41 is n+1 layers, the insulating layer 42 is n layers, and n is more than or equal to 1. The metal layers 41 and the insulating layers 42 are alternately stacked in the a direction. It is understood that the a direction is the thickness direction of the circuit board 40. The thickness of the circuit board 40 is the dimension of the circuit board 40 in the a direction.

Wherein a circuit pattern 411 is formed on each metal layer 41. And, the circuit patterns 411 on each metal layer 41 can be mutually communicated through the metallized via holes 412 so as to meet the circuit design requirement of the circuit board 40. Illustratively, the metal layer 41 may be copper foil.

Referring to fig. 1A to 3, the above-described circuit board 40 includes the metal layers 41 and the insulating layers 42 alternately stacked, and does not include the core board, so that the entire thickness of the circuit board can be reduced without affecting the operation performance. For example, compared with the circuit board 40', in the case that the metal layer 41' and the metal layer 41 are six layers, the thickness of the circuit board 40 provided by the application is smaller, the structure is more compact, and further the thinning of the mobile phone 1 is facilitated.

It is worth noting that, because the coreless circuit board is thinner, the lamination difficulty is high in the manufacturing process. In some technical schemes, copper-clad plates are used as carriers, copper foil layers are pressed on the copper-clad plates, and circuit patterns are manufactured, so that the pressing difficulty is reduced.

Fig. 4A shows a schematic diagram of the fabrication of the circuit board 40″ in some embodiments. Fig. 4B shows a second schematic diagram of the circuit board 40″ in some embodiments. Referring to fig. 4A and 4B, first, a carrier 50″ is provided. The carrier 50″ is a peelable copper-clad plate (or "release core"). The carrier 50″ includes two layers of a first copper foil 51″ and a first prepreg (PP) 52″. The first prepreg 52″ is located between two layers of the first copper foil 51″ along the a direction. Each layer of the first copper foil 51' includes a first base copper foil 511' and a first carrier copper foil 512 '. Wherein, along the A direction, the first base copper foil 511' is located between the first carrier copper foil 512' and the first prepreg 52 '.

Then, a first circuit pattern 41 'is formed on the first carrier copper foil 512'. And sequentially laminating a second prepreg 42'' and a second copper foil 43'' on the first wiring pattern 41''. Then, the second circuit pattern 44 'is continuously formed on the second copper foil 43'. Finally, the first base copper foil 511 'and the first carrier copper foil 512' are separated to obtain a prefabricated plate 60', and the first carrier copper foil 512' on the prefabricated plate 60 'is etched away to obtain the circuit board 40' shown in fig. 4B.

According to the above-described molding process of the circuit board 40', it is not difficult to find that there is a mechanical stress between the first base copper foil 511' and the first carrier copper foil 512', and thus the difficulty of separation is large, and the existing structures (e.g., the first circuit pattern 41' and the second circuit pattern 44 ') are easily damaged during separation, resulting in low yield and large molding difficulty.

In order to solve the above problems, the present application further provides a circuit board forming method. The method provides a carrier comprising two conductor layers. The two conductor layers are bonded and unbuckled by a temporary bonding and unbuckling (TBDB) technique. Under the condition that two conductor layers are bonded, a build-up structure is formed on at least one conductor layer, and then the two conductor layers are unbonded so as to separate the two conductor layers, so that a prefabricated plate is obtained, and a circuit board is obtained according to the prefabricated plate. The circuit board forming method provided by the application effectively reduces the mechanical stress between two conductor layers in the separation process, so that the forming difficulty of the circuit board is reduced, and the technical scheme is introduced by combining the drawings.

Fig. 5 shows a flowchart of a method for forming the circuit board 40 according to an embodiment of the present application. Fig. 6 is a schematic diagram illustrating molding of the circuit board 40 according to the embodiment of the present application according to fig. 5. Fig. 7 is a schematic diagram illustrating a second molding process of the circuit board 40 according to the embodiment of the present application according to fig. 5.

As shown in fig. 5, the molding method specifically includes the following steps:

s110: the carrier 50 is arranged, the carrier 50 includes a first conductor layer 51a and a second conductor layer 51b which are stacked and provided, and the opposed surfaces of the first conductor layer 51a and the second conductor layer 51b are bonded by a bonding paste 52.

In some embodiments of the present application, the first conductor layer 51a and the second conductor layer 51b may be metal layers. For example, as shown in fig. 6, a bonding adhesive 52 (for example, thermoplastic resin) may be coated on the surface of the first conductor layer 51a, and then the surface of the second conductor layer 51b is placed on the bonding adhesive 52 along the a direction, so as to achieve bonding between the first conductor layer 51a and the second conductor layer 51b, thereby obtaining the carrier 50. It will be appreciated that the a-direction is the stacking direction of the carrier 50.

Several ways of applying the bonding paste 52 on the surface of the first conductor layer 51a will be described below with reference to the drawings.

In some embodiments of the present application, a bonding glue 52 may be applied to the edge of the first conductor layer 51 a. Fig. 8 illustrates a schematic diagram of the application of a bonding adhesive 52 on the first conductor layer 51a in some embodiments of the present application. Fig. 9A illustrates an exploded view of carrier 50 according to fig. 8 in some embodiments of the present application. Fig. 9B illustrates a side view of carrier 50 according to fig. 8 in some embodiments of the present application.

Referring to fig. 8 to 9B, a bonding adhesive 52 is applied to an edge of the first conductor layer 51 a. That is, in the a direction (a direction perpendicular to the paper surface in fig. 8), the projection area of the bonding paste 52 in the first plane S1 is located at the edge of the projection area of the first conductor layer 51a in the first plane S1. Thereby, the bonding stability of the first conductor layer 51a and the second conductor layer 51b is ensured, and the difficulty of the bonding of the first conductor layer 51a and the second conductor layer 51b is reduced. Wherein the first plane S1 intersects the a direction. Illustratively, the first plane S1 is perpendicular to the a direction.

Illustratively, the bonding glue 52 may be applied at the peripheral edge of the first conductor 51a, with the distribution area of the bonding glue 52 being shaped like a "mouth". Alternatively, in other alternative implementations, the bonding adhesive 52 may be coated on a portion of the edge of the first conductor layer 51a, which is not limited in this application. For example, bonding glue 52 may be applied at opposite edges of the first conductor layer 51 a. For another example, bonding glue 52 may be applied to the adjacent two edges of the first conductor layer 51 a. For another example, the bonding paste 52 may be applied in the form of an array spot coating at the edge of the first conductor layer 51 a.

In other embodiments of the present application, the first conductor layer 51a may be coated with the bonding adhesive 52 at a position other than the edge, so that a ratio between a projected area of the bonding adhesive 52 in the first plane S1 and an area of a projected area of the first conductor layer 51a in the first plane S1 along the a direction is 0.8-1, for example, 0.8,0.9,1. Based on this, the coating range of the bonding adhesive 52 can be made larger, so that the strength of the carrier 50 is effectively improved, and the carrier 50 is ensured to have a better supporting effect.

Illustratively, fig. 10 shows a schematic illustration of the application of a bonding adhesive 52 on the first conductor layer 51a in some other embodiments of the present application. Fig. 11A illustrates an exploded view of carrier 50 according to other embodiments of the present application, in accordance with fig. 10. Fig. 11B illustrates a side view of carrier 50 according to fig. 10 in accordance with other embodiments of the present application. Referring to fig. 10 to 11B, the first conductor layer 51a is entirely coated with a bonding adhesive 52. That is, in the a direction (a direction perpendicular to the paper surface in fig. 10), the ratio between the projected area of the bonding paste 52 in the first plane S1 and the area of the projected area of the first conductor layer 51a in the first plane S1 is 1.

According to the circuit board forming method, the carrier 50 can play a supporting role in the process of forming the circuit board (such as the circuit board 40 shown in fig. 3), so that the pressing difficulty in the manufacturing process is effectively reduced, and the problems of board damage or warping and the like are avoided. Meanwhile, the first conductor layer 51a and the second conductor layer 51b are bonded by the bonding paste 52, so that the bonding stability between the first conductor layer 51a and the second conductor layer 51b can be ensured.

S120: a build-up structure 43 is formed on a surface of at least one of the first and second conductor layers 51a, 51b facing away from the bond paste 52.

With continued reference to fig. 6, in some embodiments of the present application, a first build-up structure 43a may be formed on a surface of the first conductor layer 51a facing away from the bonding adhesive 52, and a second build-up structure 43b may be formed on a surface of the second conductor layer 51b facing away from the bonding adhesive 52, while two circuit boards are fabricated, so as to further increase the fabrication efficiency. In other embodiments of the present application, the first build-up structure 43a may also be formed on the surface of the first conductor layer 51a facing away from the bonding glue 52.

For ease of description, an exemplary structure and formation of the build-up structure 43 will be described below with reference to fig. 7 by taking the first build-up structure 43a as an example.

Referring to FIG. 7, the first build-up structure 43a may include n metal layers and n insulating layers (n.gtoreq.1). For example, referring to fig. 7, the first build-up structure 43a includes a metal layer 41a, a metal layer 41b, a metal layer 41c, a metal layer 41d, and a metal layer 41e, with a total of five metal layers. The first build-up structure 43a further includes an insulating layer 42a, an insulating layer 42b, an insulating layer 42c, an insulating layer 42d, and an insulating layer 42e, which are five insulating layers in total.

The metal layers 41a to 41e and the insulating layers 42a to 42e are alternately stacked in order along the a direction, and the insulating layer 42a faces the first conductor layer 51a, so as to avoid mutual interference between the first conductor layer 51a and each metal layer.

The metal layers 41 a-41 d are formed with circuit patterns 41 a-41 d, respectively. The circuit patterns 411a to 411d may be sequentially connected to each other through the metallized vias 412a to 412 c. Thereby meeting the requirements of subsequent circuit design.

It should be noted that, in some embodiments of the present application, the metal layer 41e is not formed with a wire pattern, so as to reduce the molding difficulty of the first build-up structure 43a and improve the yield. In other embodiments, the metal layer 41e may also have a circuit pattern formed thereon, which is not limited in this application.

The first build-up structure 43a may be formed by alternately laminating the lamination insulating layer 42 and the metal layer 41 in this order on the first conductor layer 51a, for example. Alternatively, in other alternative implementations, the first build-up layer structure 43a may be formed by sequentially alternately stacking the lamination insulating layer 42 and the stacked structure on the first conductor layer 51 a. Wherein the laminated structure may include a plurality of metal layers 41, and an insulating layer 42 is provided between adjacent metal layers 41.

It is understood that the structure and the formation of the second build-up structure 43b are similar to those of the first build-up structure 43a, and will not be described herein.

S130: the first conductor layer 51a and the second conductor layer 51b are debonded to obtain a prefabricated panel 60, wherein the prefabricated panel 60 comprises a build-up structure 43 and a conductor layer connected to the build-up structure 43.

For example, as shown in fig. 7, the first conductor layer 51a and the second conductor layer 51b are debonded by a temporary bonding and debonding technique. The first conductor layer 51a and the first build-up structure 43a may together constitute a first preformed sheet 60a. The second conductor layer 51b and the second build-up structure 43b may together form a second preformed sheet 60b.

Several ways of debonding the first conductor layer 51a and the second conductor layer 51b will be described below with reference to the accompanying drawings.

In some embodiments of the present application, the first conductor layer 51a and the second conductor layer 51b may be thermally debonded. Fig. 12A illustrates a schematic diagram of debonding a first conductor layer 51a and a second conductor layer 51b in some embodiments of the present application. Referring to fig. 12A, a heat source 70 is disposed adjacent the bond paste 52. Illustratively, the heating temperature of the heat source 70 is less than 240 ℃, e.g., 200 ℃,210 ℃,220 ℃, etc. The bonding glue 52 is heated by the heat source 70, so that the bonding glue 52 is softened, and then a shearing force is applied to the first conductor layer 51a and the second conductor layer 51b, so that the first conductor layer 51a and the second conductor layer 51b are separated, the mechanical stress required to be overcome in the separation process can be effectively reduced, and the difficulty in separation between the first conductor layer 51a and the second conductor layer 51b is reduced.

For example, when the edge of the first conductor layer 51a is coated with the bonding adhesive 52, the heat source 70 may be provided around the bonding adhesive 52. When the first conductor layer 51a is entirely coated with the bonding adhesive 52, the heat source 70 may be disposed opposite to the bonding adhesive 52 in the a direction.

It is understood that the present application is not limited thereto, and any arrangement of the heat source 70 that can function to soften the bonding adhesive 52 is within the scope of the present application.

In other embodiments of the present application, the first conductor layer 51a and the second conductor layer 51b may also be debonded by a laser. Fig. 12B is a schematic diagram illustrating debonding of a first conductor layer 51a and a second conductor layer 51B in other embodiments of the present application. Referring to fig. 12B, photon energy is deposited on the photosensitive responsive material layer 81 by laser passing through the transparent carrier 80, thereby inducing rapid decomposition, vaporization or even plasma formation of the bonding paste 52 to lose adhesiveness. Meanwhile, the rapidly released decomposed gas also increases the separation pressure of the interface of the photosensitive response material layer 81, thereby further promoting the automatic separation of the first conductor layer 51a and the second conductor layer 51b, and effectively reducing the mechanical stress to be overcome in the separation process.

In other embodiments of the present application, the first conductor layer 51a and the second conductor layer 51b may also be de-bonded by chemical etching (or dissolution) according to the dissolution characteristics of the bonding adhesive 52 in a specific solvent. Specifically, the bonding part between the first conductor layer 51a and the second conductor layer 51b through the bonding glue 52 is placed into a solvent for soaking or smeared with the solvent, and after a period of time, the bonding glue 52 is gradually dissolved, so that the debonding of the first conductor layer 51a and the second conductor layer 51b is realized, the mechanical stress required to be overcome in the separation process is effectively reduced, and the difficulty of separation between the first conductor layer 51a and the second conductor layer 51b is reduced.

S140: from the prefabricated panel 60, the circuit board 40 is obtained.

In some embodiments of the present application, the first prefabricated panel 60a and the second prefabricated panel 60b are processed separately, and two circuit boards may be obtained. For convenience of description, the first prefabricated panel 60a will be described as an example.

With continued reference to fig. 3 and 7, the first preformed sheet 60a is formed from the first conductor layer 51a and the first build-up structure 43 a. Wherein the first conductor layer 51a and the metal layer 41e of the first build-up structure 43a serve as both surfaces of the first preformed sheet 60a, respectively. First, the first conductor layer 51a may be subjected to a resist residue removal treatment. For example, the bonding paste 52 remaining on the first conductor layer 51a is removed by using a bonding paste cleaning agent. The surface of the first prefabricated panel 60a is then treated to obtain the circuit board 40.

Specifically, the circuit pattern 411 may be formed on the surface of the first prefabricated panel 60a where the circuit pattern 411 is not formed, to obtain the circuit board 40. For example, neither the first conductor layer 51a nor the metal layer 41e forms a wiring pattern. A wiring pattern 411 is formed on the first conductor layer 51a and the metal layer 41e, respectively, to obtain the circuit board 40. At this time, the first conductor layer 51a and the metal layer 41e serve as both surfaces of the circuit board 40, respectively.

In the present embodiment, the circuit pattern 411 is formed on the surface of the first prefabricated panel 60a on which the circuit pattern 411 is not formed, so as to obtain the circuit board 40, but this is merely an exemplary illustration of the technical solution of the present application, and other modifications may be made by those skilled in the art. For example, in other embodiments, the surface of the first prefabricated panel 60a where the circuit pattern 411 is not formed may be etched away to obtain the circuit board 40.

As another example, in other embodiments, the build-up structure may be further formed on the surface of the first prefabricated panel 60a on which the circuit pattern 411 is formed, so as to obtain a greater number of layers of the circuit boards 40. The specific implementation process of forming the build-up structure on the surface of the first prefabricated panel 60a on which the circuit pattern 411 is formed is similar to the specific implementation process of forming the first build-up structure 43a described above, and will not be described herein.

According to the forming method of the circuit board 40, the first conductor layer 51a and the second conductor layer 51b are bonded and unbonded through the temporary bonding and unbonded technology, so that the mechanical stress required to be overcome in the separation process of the first conductor layer 51a and the second conductor layer 51b can be reduced, the stripping difficulty of the first conductor layer 51a and the second conductor layer 51b is reduced, the forming difficulty of the circuit board 40 is further reduced, and the yield of the circuit board 40 is improved.

In addition, the first conductor layer 51a and the second conductor layer 51b not only can play a supporting role in the process of forming the circuit board 40, but also can be used as a composition structure of the circuit board 40, thereby avoiding wasting the carrier 50 and reducing the manufacturing cost of the circuit board 40. For example, as shown in fig. 4A and 4B, the carrier 50″ of the prior art only plays a supporting role and cannot be reused, and one carrier 50″ is wasted per molded circuit board 40″. In this application, after the first conductor layer 51a and the second conductor layer 51b are de-bonded, the first conductor layer 51a and/or the second conductor layer 51b may be used as the metal layer 41 in the circuit board 40, which effectively solves the problem of material waste and reduces the manufacturing cost of the circuit board 40.

The following describes the specific implementation procedure of step S120 with reference to the accompanying drawings.

In some embodiments of the present application, the build-up structures 43 with different layers may be formed by alternately stacking insulating layers and metal layers on the surface of the first conductor layer 51a and/or the second conductor layer 51b facing away from the bonding glue 52. Since the step of disposing the metal layers is repeated, for convenience of description and understanding below, description will be made below taking as an example that two metal layers and two insulating layers are alternately stacked on the side of the first conductor layer 51a facing away from the bonding paste 52.

Fig. 13 illustrates a flow chart of forming a first build-up structure 43a on a first conductor layer 51a in some embodiments of the present application. Fig. 14A illustrates a schematic diagram of forming a first build-up structure 43a on a first conductor layer 51a in some embodiments of the present application. Fig. 14B illustrates a second schematic diagram of forming a first build-up structure 43a on the first conductor layer 51a in some embodiments of the present application. Fig. 14C illustrates a third schematic view of forming a first build-up structure 43a on a first conductor layer 51a in some embodiments of the present application.

Referring to fig. 13, step S120 may include the sub-steps of:

s121a: the metal layer 41a is pressed onto the side of the first conductor layer 51a facing away from the bonding glue 52 by means of the insulating layer 42 a.

As shown in fig. 14A, in some implementations, an insulating layer 42a (as a first insulating layer) may be first provided on a surface of the first conductor layer 51a (as a first metal layer) facing away from the bonding adhesive 52. Then, a metal layer 41a (as a second metal layer) is provided on the surface of the insulating layer 42a facing away from the first conductor layer 51a. Finally, a force is applied to the metal layer 41a so that the metal layer 41a can be pressed onto the first conductor layer 51a.

In alternative other implementations, insulating layer 42a may be provided on metal layer 41a first. The metal layer 41a and the insulating layer 42a are provided on the first conductor layer 51a, and the surface of the metal layer 41a on which the insulating layer 42a is provided faces the first conductor layer 51a.

S122a: a wiring pattern 411a is formed on the metal layer 41a.

Referring to fig. 14B, in some embodiments of the present application, a circuit pattern 411a may be formed on the metal layer 41a by a masking (masking) Process or a modified Semi-Additive Process (MSAP) Process, etc., which is not limited in this application.

The metal layer 41a may be selected to have different thickness according to different processes. Illustratively, the thickness of the metal layer 41a may be 1 μm to 15 μm. For example, the thickness of the metal layer 41a may be 12 μm so as to make the line pattern 411a on the metal layer 41a by a masking process, and for another example, the thickness of the metal layer 41a may also be 3 μm so as to make the line pattern 411a on the metal layer 41a by a modified half-additive process.

S123a: the metal layer 41b is pressed onto the surface of the metal layer 41a facing away from the bonding glue 52 by the insulating layer 42 b.

Wherein the metal layer 41b serves as a third metal layer and the insulating layer 42b serves as a second insulating layer. Step S123a is similar to step S121a described above, and specific reference may be made to fig. 14A and the related description thereof, which are not repeated here.

S124a: a wiring pattern 411b is formed on the metal layer 41b.

Step S124a is similar to step S122a, and specific reference is made to fig. 14B and the related description thereof, which are not repeated here.

S125a: a metallized via 412a is fabricated on metal layer 41a, insulating layer 42b, and metal layer 41b.

Referring to fig. 14C, a via may be drilled in the metal layer 41a, the insulating layer 42b, and the metal layer 41b, and then a conductive metal may be plated on the wall of the via by electroless plating or electroplating, to form a metallized via 412a. The metallized via 412a communicates between the metal layer 41a and the metal layer 41b through the insulating layer 42 b. Based on this, the wiring pattern 411a on the metal layer 41a and the wiring pattern 411b on the metal layer 41b can be conducted through the metallized via 412a to form a circuit.

Thus, the metal layer 41a, the metal layer 41b, the insulating layer 42a, and the insulating layer 42b can be formed as the constituent structure of the first build-up structure 43 a.

It is understood that the structural form and the forming process of the first build-up structure 43a are merely exemplary descriptions of the technical solutions of the present application, and other modifications can be made by those skilled in the art. For example, in the present embodiment, the first build-up structure 43a includes two metal layers (i.e., the metal layer 41a and the metal layer 41 b) and two insulating layers (i.e., the insulating layer 42a and the insulating layer 42 b), so that the first build-up structure 43a can be formed on the first conductor layer 51a by performing steps S121a to S125 a.

In other embodiments, some steps may be repeated or skipped according to actual requirements to form the first build-up structure 43a with different layers and structures.

For example, the steps S123a to S125a may be repeated to form the first build-up structure 43a with more layers. For example, the first build-up structure 43a shown in fig. 7 includes metal layers 41 a-41 e, which are five metal layers in total. Accordingly, steps S121 a-S125 a may be performed to provide the metal layers 41a and 41b, and steps S123 a-S125 a may be repeated to provide the metal layers 41 c-41 e.

Illustratively, referring to steps S123 a-S125 a, first, the metal layer 41c is laminated on the metal layer 41b through the insulating layer 42c, then the circuit pattern 411c is formed on the metal layer 41c, and finally the metallized via 412b is formed on the metal layer 41b, the insulating layer 42c and the metal layer 41c to conduct the metal layer 41b and the metal layer 41c.

Accordingly, the specific process of disposing the metal layer 41d and the metal layer 41e may refer to steps S123a to S125a, which are not described herein.

As another example, the first build-up structure 43a may also include a metal layer (e.g., metal layer 41 a) and an insulating layer (e.g., insulating layer 42 a). Therefore, steps S121a and S122a may be performed without performing steps S123a to S125a.

For another example, when the last metal layer is pressed, the step of manufacturing the circuit pattern and/or the metallized via hole can be omitted, so that the molding difficulty is reduced. Illustratively, the first build-up structure 43a shown in FIG. 7 includes metal layers 41 a-41 e. After performing step S123a to press the last metal layer 41e on the metal layer 41d, the overall thickness of the first build-up structure 43a is thicker, and the difficulty of fabricating the circuit pattern and the metallized via hole is greater. Therefore, step S124a and step S125a may not be performed, so as to further reduce the molding difficulty of the first build-up structure 43a and improve the yield.

For another example, in the present application, the execution sequence between step S124a and step S125a may be adjusted according to actual needs, which is not specifically limited in the present application.

In some embodiments of the present application, the aperture of each of the metallized vias (e.g., metallized vias 412 a-412 c shown in fig. 7) in the first build-up structure 43a formed by the method described above is gradually increased or gradually decreased along the a direction. That is, the aperture of the buried holes (e.g., metallized vias 412 a-412 c shown in fig. 7) in the final molded circuit board gradually increases or gradually decreases in the a direction.

In alternative other implementations, the first build-up structure 43a may also be formed by providing a laminated structure on the first conductor layer 51 a. The laminated structure includes metal layers and insulating layers alternately laminated in this order. Wherein, the inner metal layer is formed with circuit patterns. At least one of the outer metal layers is formed with a wiring pattern. The outer metal layer on which the wiring pattern is formed is provided so as to face the first conductor layer 51 a. The manner of disposing the laminated structure on the first conductor layer 51a is similar to the manner of disposing the multi-layer metal layer on the first conductor layer 51a, and the foregoing steps S121a to S125a may be referred to, and will not be repeated herein.

It will be appreciated that the above embodiment describes the specific molding process of the circuit board 40 by taking the first conductor layer 51a as a metal layer as an example. In other embodiments, the first conductor layer 51a may also be a copper-clad plate. Fig. 15 shows a schematic structural view of a first conductor layer 51a in other embodiments of the present application.

The first conductor layer 51a shown in fig. 15 is different in layer structure of the first conductor layer 51a from the embodiment in which the first conductor layer 51a is a metal layer shown in fig. 8 to 11B described above. Specifically, in fig. 15, the first conductor layer 51a includes three layers of a metal layer 41a, an insulating layer 42a, and a metal layer 41f, which are stacked in this order. It is understood that the structure of the second conductor layer 51b is identical to the structure of the first conductor layer 51a described above. For example, the second conductor layer 51b includes a metal layer 41g, an insulating layer 42f, and a metal layer 41h, which are stacked in this order.

A method of forming a circuit board when the first conductor layer 51a is a copper-clad plate in the present embodiment will be briefly described below.

In connection with fig. 3, 6, 7 and 15, in some embodiments of the present application, a method of molding a circuit board includes disposing a carrier. In the carrier 50, the metal layer 41f in the first conductor layer 51a and the metal layer 41g in the second conductor layer 51b are bonded by the bonding paste 52.

A build-up structure 43 is formed on a surface of at least one of the metal layer 41a of the first conductor layer 51a and the metal layer 41h of the second conductor layer 51b facing away from the bond paste 52. The metal layer 41f and the metal layer 41g are debonded to obtain the prefabricated panel 60. For example, the first preformed sheet 60a is formed by the first conductor layer 51a and the first build-up structure 43a together. Wherein the metal layer 41f of the first conductor layer 51a and the metal layer 41e of the first build-up structure 43a serve as both surfaces of the first preformed sheet 60a, respectively.

Further, the circuit board 40 is obtained from the prefabricated panel 60. For example, the metal layer 41f of the first conductor layer 51a may be subjected to a resist removing treatment. The surface of the first prefabricated panel 60a is then treated to obtain the circuit board 40.

Notably, since the copper-clad plate itself has two metal layers (e.g., the metal layer 41a and the metal layer 41f, or the metal layer 41g and the metal layer 41 h). Thus, in some implementations, before forming the build-up structure 43, a circuit pattern may be first formed on the metal layer (e.g., the metal layer 41a, the metal layer 41 h) of the first conductor layer 51a and/or the second conductor layer 51b itself, and then insulating layers and other metal layers may be alternately stacked on the metal layer (e.g., the metal layer 41a, the metal layer 41 h) to form the build-up structure 43. Thus, the step of pressing the metal layer is reduced while the strength of the carrier 50 is ensured, and the molding efficiency of the build-up structure 43 is improved.

For convenience of description, the first build-up structure 43a is formed on the metal layer 41a of the first conductor layer 51a will be described below as an example.

Specifically, fig. 16 shows a flowchart of forming the first build-up structure 43a on the first conductor layer 51a in other embodiments of the present application. Referring to fig. 16, step S120 may include the sub-steps of:

s121b: a wiring pattern 411a is formed on the metal layer 41 a.

S122b: the metal layer 41b is pressed onto the surface of the metal layer 41a facing away from the bonding glue 52 by the insulating layer 42 b.

S123b: a wiring pattern 411b is formed on the metal layer 41 b.

S124b: a metallized via 412a is fabricated on metal layer 41a, insulating layer 42b, and metal layer 41 b.

The steps S121 b-S124 b are the same as the steps S122 a-S125 a, and reference may be made to the steps S122 a-S125 a for details which will not be described herein.

It can be understood that the method shown in fig. 16 is different from the method shown in fig. 13 in that the method shown in fig. 16 is to form the first build-up structure 43a on the metal layer 41a of the first conductor layer 51a, without first providing a metal layer on the first conductor layer 51a, and it can be understood that the step S121a is skipped, thereby further improving the forming efficiency of the first build-up structure 43a.

Similarly, in alternative other implementations, the first build-up layer 43a may be formed by providing a stacked structure on the metal layer 41a of the first conductor layer 51 a. The laminated structure includes metal layers and insulating layers alternately laminated in this order. Wherein, the inner metal layer is formed with circuit patterns. At least one of the outer metal layers is formed with a wiring pattern. The outer metal layer having the wiring pattern formed thereon is provided so as to face the metal layer 41a of the first conductor layer 51 a. The manner of disposing the stacked structure on the metal layer 41a of the first conductor layer 51a is similar to the manner of disposing a plurality of metal layers on the metal layer 41a of the first conductor layer 51a, and the foregoing steps S121b to S125b may be referred to specifically, and will not be described herein.

The application also provides a circuit board forming method. The method provides a carrier comprising at least one conductor layer and a reinforcement layer arranged in a stack. The conductor layer and the reinforcing layer are bonded and unbuckled by a temporary bonding and unbuckling technology. Under the condition that the conductor layer is bonded with the reinforcing layer, a build-up structure is formed on the conductor layer, and then the conductor layer and the reinforcing layer are unbonded to separate the conductor layer and the reinforcing layer, so that a prefabricated plate is obtained, and a circuit board is obtained according to the prefabricated plate. The circuit board forming method effectively reduces the mechanical stress between the conductor layer and the reinforcing layer in the separation process, so that the forming difficulty of the circuit board is reduced, and the technical scheme is introduced by combining the drawings. The following description will be made taking the conductor layer as an example. It will be appreciated that in other embodiments the conductor layer may be a single layer.

Fig. 17 shows a second flowchart of a molding method of the circuit board 40 in the embodiment of the present application. As shown in fig. 17, the molding method specifically includes the steps of:

s210: the carrier 50 is arranged, and the carrier 50 includes a first conductor layer 51a, a reinforcing layer 53, and a second conductor layer 51b which are laminated in this order, and the surfaces of the first conductor layer 51a and the reinforcing layer 53 facing each other are bonded by a bonding adhesive 52, and the surfaces of the second conductor layer 51b and the reinforcing layer 53 facing each other are bonded by the bonding adhesive 52.

Fig. 18 shows a schematic view of forming a carrier 50 in an embodiment of the present application. For example, as shown in fig. 18, bonding glue 52 may be coated on two surfaces of the reinforcing layer 53, and then the first conductor layer 51a and the second conductor layer 51b may be placed on two surfaces of the reinforcing layer 53, so that the first conductor layer 51a and the second conductor layer 51b are bonded to the reinforcing layer 53, respectively, to obtain the carrier 50. Wherein, the reinforcing layer 53 can further improve the overall strength of the carrier 50, so that the carrier 50 can better play a supporting role.

The specific implementation process of coating the bonding adhesive 52 on the reinforcing layer 53 is identical to the specific implementation process of coating the bonding adhesive 52 on the first conductor layer 51a, and specific reference may be made to fig. 8 to 11B and related descriptions thereof, which are not repeated herein. Illustratively, the reinforcing layer 53 is a prepreg.

S220: a build-up structure 43 is formed on a surface of at least one of the first and second conductor layers 51a, 51b facing away from the bond paste 52.

S230: the conductor layer connected with the build-up structure 43 and the reinforcing layer 53 are debonded to obtain the prefabricated panel 60, wherein the prefabricated panel 60 comprises the build-up structure 43 and the conductor layer connected with the build-up structure 43.

S240: from the prefabricated panel 60, the circuit board 40 is obtained.

Steps S220 to S240 are the same as steps S120 to S140, and are not described herein.

The above molding method is different from the molding method shown in fig. 5 in that the carrier 50 has a different structure, and the carrier 50 in the molding method shown in fig. 17 further includes a reinforcing layer 53 in addition to the first conductor layer 51a and the second conductor layer 51b, thereby further improving the overall strength of the carrier 50 and enabling the carrier 50 to perform a better supporting function.

In the same way, in the above molding method, the first conductor layer 51a and the second conductor layer 51b are bonded and unbonded with the reinforcing layer 53 by the temporary bonding and unbonding technology, so that the mechanical stress required to be overcome in the separation process can be reduced, the difficulty in stripping the first conductor layer 51a and the second conductor layer 51b is reduced, the molding difficulty of the circuit board 40 is further reduced, and the yield of the circuit board 40 is improved.

The application also provides a circuit board forming method. The carrier provided by the method comprises two conductor layers which are arranged in a stacked manner. The two opposite surfaces of the two conductor layers are fixedly connected through the connecting part, under the condition that the two conductor layers are fixedly connected, a layer-adding structure is formed on at least one conductor layer, and then the connecting part is cut off to separate the two conductor layers, so that a prefabricated plate is obtained, and a circuit board is obtained according to the prefabricated plate. The circuit board forming method provided by the application effectively avoids the problem that mechanical stress exists between two conductor layers in the separation process, and further reduces the forming difficulty of the circuit board, and the technical scheme is introduced below with reference to the accompanying drawings.

Fig. 19 shows a flowchart three of a molding method of the circuit board 40 in the embodiment of the present application. As shown in fig. 19, the molding method specifically includes the steps of:

s310: the carrier 50 is arranged, the carrier 50 includes a first conductor layer 51a and a second conductor layer 51b which are laminated, and the opposite surfaces of the first conductor layer 51a and the second conductor layer 51b are fixedly connected by a connecting portion 54, and the connecting portion 54 is provided at an edge of the first conductor layer 51 a.

Fig. 20 shows a schematic view of the connection portion 54 in the embodiment of the present application. Referring to fig. 20, in the a direction (a direction perpendicular to the paper surface in fig. 20), the projection area of the connection portion 54 on the first plane S1 is located at the edge of the projection area of the first conductor layer 51a on the first plane S1.

In some embodiments of the present application, as shown in fig. 20, along the direction a (the direction perpendicular to the paper surface in fig. 20), the ratio between the projected area of the connection portion 54 in the first plane S1 and the projected area of the first conductor layer 51a in the first plane S1 is 0.2-0.5, for example, 0.2,0.3,0.4. In this way, the cut-out portion (i.e., the region S2 to be processed, described below) can be reduced, unnecessary waste is avoided, and at the same time, stability of bonding between the first conductor layer 51a and the second conductor layer 51b can be ensured, thereby enabling the carrier 50 to provide a supporting force better.

The specific method for disposing the connection portion 54 at the edge of the first conductor layer 51a may refer to the specific method for disposing the bonding adhesive 52 at the edge of the first conductor layer 51a, and may refer to fig. 8 to 9B and the related descriptions thereof, which are not repeated herein. Illustratively, the connection 54 may be a bonding adhesive or prepreg.

S320: the build-up structure 43 is formed on a surface of at least one of the first conductor layer 51a and the second conductor layer 51b facing away from the connection portion 54.

Step S320 is the same as step S120, and is not described herein.

S330: the connection portion 54 is cut out to obtain a prefabricated panel 60, wherein the prefabricated panel 60 includes the build-up structure 43 and the conductor layer connected with the build-up structure 43.

Fig. 21 shows a schematic view of a cut-away connection 54 in an embodiment of the present application. Illustratively, referring to fig. 21, the region S2 to be processed may be cut away for the purpose of cutting away the connection portion 54, thereby separating the first conductor layer 51a and the second conductor layer 51b to obtain the prefabricated panel 60.

The area to be processed S2 may be an area occupied by the connection portion 54, and an area occupied by a projection of the connection portion 54 on each layer structure (for example, the build-up structure 43, the first conductor layer 51a, and the second conductor layer 51 b) in the a direction. For example, the region S2 to be processed may be a region surrounded by a rectangular broken line in fig. 21.

By cutting away the connection portion 54, the problem of mechanical stress that the first conductor layer 51a and the second conductor layer 51b need to overcome in the separation process can be avoided, thereby reducing the difficulty of separation between the first conductor layer 51a and the second conductor layer 51 b.

In some embodiments of the present application, the connection portion 54 may be cut by mechanical milling or laser cutting, etc., which is not limited in this application.

S340: from the prefabricated panel 60, the circuit board 40 is obtained.

Step S340 is the same as step S140, and is not described herein.

The molding method of the circuit board 40 is different from the molding method shown in fig. 5 in that the first conductor layer 51a and the second conductor layer 51b are separated, and the molding method shown in fig. 19 realizes the separation of the first conductor layer 51a and the second conductor layer 51b by cutting the connection portion 54, so that the problem of mechanical stress generated in the separation process can be avoided, the difficulty of stripping the first conductor layer 51a and the second conductor layer 51b is reduced, the molding difficulty of the circuit board 40 is further reduced, and the yield of the circuit board 40 is improved.

In summary, the circuit board provided by the application has the advantage of compact structure, and is favorable for realizing the light and thin electronic equipment. According to the circuit board forming method, the mechanical stress required to be overcome in the separation process of the layer structure (such as the first conductor layer and the second conductor layer, the first conductor layer and the reinforcing layer) in the carrier can be reduced by changing the structure of the carrier or changing the separation mode of the carrier, the separation difficulty is reduced, the forming difficulty of the circuit board is further reduced, and the yield of the circuit board is improved.

Secondly, the layer structure (for example, the first conductor layer and the second conductor layer) in the carrier can also be used as a component structure of the circuit board after being separated, so that waste of materials can be avoided, and the manufacturing cost of the circuit board is reduced.

Finally, the circuit board forming method can be applied to the scene (for example, embedded circuit technology (embedded trace substrate, ETS)) which needs various strippable carriers, and the embedding of the outer layer circuit is realized, so that the application range is wide.

The foregoing describes embodiments of the present application in terms of specific embodiments, and other advantages and effects of the present application will be readily apparent to those skilled in the art from the disclosure herein. While the description of the present application will be presented in conjunction with some embodiments, it is not intended that the features of this application be limited to only this embodiment. Rather, the purpose of the description presented in connection with the embodiments is to cover other alternatives or modifications, which may be extended by the claims based on the present application. The present application may be practiced without these specific details. Furthermore, some specific details are omitted from the description in order to avoid obscuring the focus of the application. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other.

In the description of the present application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "outer," "inner," "circumferential," "radial," "axial," and the like indicate orientations or positional relationships based on the orientations or positional relationships illustrated in the drawings, merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.

In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "mounted," "connected," and "attached" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

Claims

1. A method of forming a circuit board, comprising:

arranging a carrier, wherein the carrier comprises two conductor layers which are stacked, and the opposite surfaces of the two conductor layers are bonded through bonding glue;

forming a build-up structure on the surface of at least one conductor layer, which is opposite to the bonding glue;

debonding the two conductor layers to obtain a prefabricated plate, wherein the prefabricated plate comprises a layer-adding structure and a conductor layer connected with the layer-adding structure;

and obtaining the circuit board according to the prefabricated plate.

2. The method of claim 1, wherein the conductor layers comprise a first metal layer, the forming a build-up structure on a surface of at least one of the conductor layers facing away from the bond paste comprising:

laminating a second metal layer on one side of the first metal layer, which is opposite to the bonding glue, through a first insulating layer;

And manufacturing a circuit pattern on the second metal layer.

3. The method as recited in claim 2, further comprising: and pressing the third metal layer on one side of the second metal layer, which is opposite to the bonding glue, through the second insulating layer.

4. A method according to claim 3, further comprising:

and manufacturing a circuit pattern on the third metal layer, and manufacturing a metallized via hole on the second metal layer, the second insulating layer and the third metal layer, wherein the metallized via hole passes through the second insulating layer to be communicated with the second metal layer and the third metal layer.

5. The method of claim 1, wherein the conductor layer comprises a first metal layer, a first insulating layer, and a second metal layer disposed in a stacked order in a direction away from the bond paste;

the forming a build-up structure on the surface of at least one of the conductor layers facing away from the bonding glue comprises:

manufacturing a circuit pattern on the second metal layer;

pressing a third metal layer on one side of the second metal layer, which is opposite to the bonding glue, through a second insulating layer;

6. The method of claim 1, wherein the means for debonding the two conductor layers comprises any one of: thermal decomposition, laser bonding and chemical bonding.

7. A method of forming a circuit board, comprising:

arranging a carrier, wherein the carrier comprises at least one conductor layer and a reinforcing layer which are overlapped, and the surfaces of the conductor layer and the reinforcing layer which are opposite are bonded through bonding glue;

forming a build-up structure on the surface of the conductor layer facing away from the bonding adhesive;

debonding the conductor layer and the reinforcing layer to obtain a prefabricated plate, wherein the prefabricated plate comprises the build-up structure and the conductor layer connected with the build-up structure;

and obtaining the circuit board according to the prefabricated plate.

8. The method of claim 7, wherein the number of conductor layers is two, and the reinforcement layer is disposed between the two conductor layers along the lamination direction of the carrier.

9. The method of claim 7, wherein the reinforcing layer is a prepreg.

10. The method according to claim 1 or 7, characterized in that the ratio between the projected area of the bonding glue in a first plane and the projected area of the conductor layer in the first plane is 0.8-1 along the lamination direction of the carrier, wherein the first plane intersects the lamination direction of the carrier.

11. Method according to claim 1 or 7, characterized in that the projection area of the bonding glue in a first plane is located at the edge of the projection area of the conductor layer in the first plane in the direction of lamination of the carrier, wherein the first plane intersects the direction of lamination of the carrier.

12. A method of forming a circuit board, comprising:

arranging a carrier, wherein the carrier comprises two conductor layers which are overlapped, the opposite surfaces of the two conductor layers are connected through a connecting part, and along the overlapping direction of the carrier, a projection area of the connecting part in a first plane is positioned at the edge of a projection area of the conductor layer in the first plane, and the first plane is intersected with the overlapping direction of the carrier;

forming a build-up structure on the surface of at least one of the conductor layers facing away from the connection portion;

cutting off the connecting part to obtain a prefabricated plate, wherein the prefabricated plate comprises a layer-adding structure and a conductor layer connected with the layer-adding structure;

and obtaining the circuit board according to the prefabricated plate.

13. The method of claim 12, wherein said resecting said connection comprises: and cutting off the area occupied by the connecting part, and along the superposition direction of the carrier, the area occupied by the projection of the connecting part on the conductor layer and the build-up structure.

14. The method according to claim 12, wherein a ratio between an area of projection of the connection portion in the first plane and an area of projection of the conductor layer in the first plane is 0.2 to 0.5 in a lamination direction of the carrier.

15. The method of claim 12, wherein the connection comprises a prepreg or a bonding adhesive.

16. The method of claim 1, 7 or 12, wherein the conductor layer is a metal layer or a copper-clad plate.

17. A circuit board, characterized in that the circuit board is molded by the circuit board molding method according to any one of claims 1 to 16.

18. The circuit board of claim 17, wherein the circuit board comprises a buried via, and wherein a diameter of the buried via gradually increases or gradually decreases in a thickness direction of the circuit board.

19. The utility model provides a circuit board, its characterized in that, the circuit board includes metal level, insulating layer and buries the hole, the metal level with the insulating layer is the alternate lamination in proper order sets up, buries the hole intercommunication two the metal level, the aperture of buries the hole is followed the thickness direction of circuit board increases gradually or reduces gradually.