TW201417663A - Method for manufacturing package board - Google Patents

Abstract

A method for manufacturing package board includes steps below. First, a first copper film, a first release film, an adhesive sheet, a second release film and a second copper film are provided. Second, the first copper film, the first release film, the adhesive sheet, the second release film and the second copper film are laminated to form a whole substrate. A plurality of first pads and a plurality of second pads are formed by electric-plated. Third, a first dielectrical layer and a first conductive layer are laminated on one side of the whole substrate. A second dielectrical layer and a second conductive layer are laminated on the opposite side of the whole substrate. Fourth, a plurality of first blind via corresponding to the first pads and a first trace layer are formed, and a plurality of second blind via and a second trace layer are formed. Fifth, a first package substrate and a second package substrate are formed by cutting. Sixth, the first and second copper films are removed, a first package board and a second package board are obtained.

Description

Carrier plate manufacturing method

The present invention relates to the field of circuit board manufacturing technology, and in particular, to a method for manufacturing a carrier board.

The carrier board can provide electrical connection, protection, support, heat dissipation, assembly and other functions for the wafer to achieve multi-pin, reduce package volume, improve electrical performance and heat dissipation, ultra-high density or multi-chip modularization.

In the process of packaging the wafer by the carrier board, when the thickness of the carrier board is small, it is required to be supported by a rigid support board. In the prior art, the two substrates are usually fabricated simultaneously and simultaneously, and the support plate is disposed between the two substrates. In order to be able to separate the front and back wafer packages obtained after packaging, it is usually necessary to use a special copper foil as a part of the support plate to be connected to the carrier. The special copper foil is a structure in which a layer of a glue layer is sandwiched between two layers of copper foil, and the thickness of the two layers of copper foil is different. This copper foil is expensive and increases the cost of the production of the carrier sheet.

In view of this, it is necessary to provide a manufacturing method of the carrier board to reduce the manufacturing cost of the carrier board.

A manufacturing method of a carrier board, comprising the steps of: providing a first copper foil, a first release film, a film, a second release film and a second copper foil, wherein the film has a central area, and the first release film and The shape and size of the second release film correspond to the shape and size of the central region; and sequentially pressing the first copper foil, the first release film, the film, the second release film and the second copper foil into one whole The two sides of the central portion of the film are in contact with the first release film and the second release film to obtain a multi-layer substrate, and the multi-layer substrate includes a product area and a waste area surrounding the product area, and the product area is in the An orthographic projection of a copper foil surface is located within the orthographic projection of the central region on the surface of the first copper foil; a plurality of first electrical contact pads are electroplated on the surface of the first copper foil, and the second copper foil is Forming a plurality of second electrical contact pads on the surface; pressing the first dielectric layer and the first conductive layer on the plurality of first electrical contact pads and the first copper foil surface, in the plurality of the second The second contact layer and the second copper layer are pressed against the second dielectric layer and the second conductive layer; Forming a first conductive blind via in the dielectric layer and the first conductive layer, and forming a first conductive layer to form a third electrical contact pad, and forming a plurality of second conductive blinds in the second dielectric layer and the second conductive layer a hole, and forming a second conductive layer to form a plurality of fourth electrical contact pads; cutting along a boundary line between the product area and the waste area, and causing the first copper foil in the product area to be naturally separated from the first release film The second copper foil in the product area is naturally separated from the second release film, thereby obtaining the first carrier substrate and the second carrier substrate separated from each other; and removing the first copper foil from the first carrier substrate to obtain the first carrier The plate removes the second copper foil from the second carrier substrate to obtain a second carrier plate.

Compared with the prior art, the carrier plate provided by the technical solution is provided with a release film having a cross-sectional area smaller than that of the first copper foil and the second copper foil on both sides of the film during the manufacturing process, thereby forming and forming After the conductive lines, the film can be easily separated from the first carrier substrate and the second carrier substrate. Therefore, the manufacturing method of the carrier board provided by the technical solution can avoid the use of a special copper foil structure which is relatively expensive, thereby reducing the manufacturing cost of the carrier board.

The manufacturing method of the package substrate provided by the technical solution includes the following steps:

In the first step, referring to FIG. 1, a first copper foil 11, a second copper foil 12, a first release film 13, a second release film 14, and a film 15 are provided.

The first copper foil 11 and the second copper foil 12 are each a copper foil having a thickness of 5 μm to 20 μm. Preferably, the thickness of the first copper foil 11 and the second copper foil 12 are both 10 micrometers to 15 micrometers. The first release film 13 and the second release film 14 may be a PE release film or a PET release film or the like. Film 15 is a FR4 epoxy glass cloth semi-cured film.

The shapes and sizes of the first copper foil 11, the second copper foil 12, and the film 15 are the same. The shapes of the first release film 13 and the second release film 14 are the same as those of the first copper foil 11, and the sizes of the first release film 13 and the second release film 14 are smaller than the size of the first copper foil 11. Specifically, the cross-sectional areas of the first release film 13 and the second release film 14 are smaller than the cross-sectional area of the first copper foil 11. Film 15 includes a central region 151 and an edge region 152 that surrounds central region 151. The shape of the central portion 151 is the same as that of the first release film 13 and the second release film 14, and is equal in size.

Film 15 is a FR4 epoxy glass cloth semi-cured film.

In the second step, referring to FIG. 2, the first copper foil 11, the first release film 13, the film 15, the second release film 14, and the second copper foil 12 are laminated and laminated one at a time to obtain a multilayer substrate. 110.

When the first copper foil 11, the first release film 13, the film 15, the second release film 14, and the second copper foil 12 are stacked, the first copper foil 11, the first release film 13, the film 15, The centers of the second release film 14 and the second copper foil 12 are aligned with each other. Since the sizes of the first release film 13 and the second release film 14 are smaller than those of the first copper foil 11, the second copper foil 12, and the film 15, the first release film 13 and the second release film 14 are respectively associated with the film 15. The central area 151 corresponds. When the pressing is performed, both sides of the edge region 152 of the film 15 are bonded to the first copper foil 11 and the second copper foil 12, respectively, and the two sides of the central portion 151 of the film 15 are respectively associated with the first release film 13 and the first The two release films 14 are in contact with each other, and the central portion 151 of the film 15 is not in contact with the first copper foil 11 and the second copper foil 12.

The multilayer substrate 110 has opposing first and second surfaces 101, 102, wherein the first surface 101 is the surface of the first copper foil 11, and the second surface 102 is the surface of the second copper foil 12.

The multilayer substrate 110 has a product area 103 and a waste area 104 surrounding the product area 103. The cross-sectional area of the product region 103 is smaller than the cross-sectional area of the first release film 13. The orthographic projection of the product region 103 on the surface of the first copper foil 11 is located within the orthographic projection of the first release film 13 on the surface of the first copper foil 11.

It can be understood that when used to simultaneously fabricate a plurality of package substrates, the product region 103 may include a plurality of product units separated from each other, each product unit corresponding to a corresponding one of the package substrates.

Referring to FIG. 3, after the multilayer substrate 110 is formed by pressing, a step of forming a plurality of first tool holes 16 in the multilayer substrate 110 may be further included. The opened position of the formed first tool hole 16 corresponds to the edge area 152 of the film 15. That is, the first tool hole 16 penetrates the edge portion 152 of the film 15 and the first copper foil 11, the first release film 13, the second release film 14, and the second copper foil 12 corresponding to the edge region 152. The first tool hole 16 is used for positioning in the next step.

In the fourth step, referring to FIG. 4 to FIG. 6 , a plurality of first electrical contact pads 31 are formed on the surface of the first copper foil 11 , and a second electrical contact pad 32 is formed on the surface of the second copper foil 12 .

The forming of the plurality of first electrical contact pads 31 and the plurality of second electrical contact pads 32 may take the following methods:

First, a first photoresist pattern 41 is formed on the surface of the first copper foil 11, and a second photoresist pattern 42 is formed on the surface of the second copper foil 12. Specifically, the photoresist layer covering the entire first copper foil 11 and the second copper foil 12 may be formed by laminating a dry film or printing a liquid photosensitive ink. Then, a portion of the photoresist layer is selectively removed by exposure and development to form a first photoresist pattern 41 and a second photoresist pattern 42.

Then, a first electrical contact pad 31 is formed on the surface of the first copper foil 11 exposed from the first photoresist pattern 41 by electroplating, and a second copper is exposed from the second photoresist pattern 42. A second electrical contact pad 32 is formed on the surface of the foil 12.

Finally, the first photoresist pattern 41 and the second photoresist pattern 42 are removed. In this embodiment, the stripping liquid may be reacted with the first photoresist pattern 41 and the second photoresist pattern 42 such that the first photoresist pattern 41 is from the first copper foil 11 The surface is detached and the second photoresist pattern 42 is detached from the surface of the second copper foil 12.

The first electrical contact pads 31 and the second electrical contact pads 32 are both located within the product region 103.

In the fifth step, referring to FIG. 7, the first dielectric layer 51 and the first conductive layer 61 are laminated on the surface of the first copper foil 11 and the first electrical contact pad 31, and the second copper foil 12 and the second electrical layer are laminated. The second dielectric layer 52 and the second conductive layer 62 are laminated on the surface of the contact pad 32.

The first dielectric layer 51 and the first conductive layer 61 may be a single structure, that is, a single-sided copper-clad substrate composed of the first dielectric layer 51 and the first conductive layer 61. The second dielectric layer 52 and the second conductive layer 62 may also be a unitary structure, that is, a single-sided copper-clad substrate composed of the second dielectric layer 52 and the second conductive layer 62.

After the step, the second tool hole 17 may be formed in the first dielectric layer 51, the first conductive layer 61, the multilayer substrate 110, the second dielectric layer 52, and the second conductive layer 62 which are laminated together. The second tool hole 17 is located in the waste area 1104. The second tool hole 17 may coincide with the first tool hole 16. The second tool hole 17 is used for positioning during subsequent outer layer fabrication.

In the sixth step, referring to FIG. 8 and FIG. 10, a plurality of first conductive vias 53 are formed in the first conductive layer 61 and the first dielectric layer 51, and are disposed in the second conductive layer 62 and the second dielectric layer 52. Forming a plurality of second conductive vias 54 and forming a first conductive layer 61 to form a first conductive wiring layer 63, and forming a second conductive layer 62 to form a second conductive wiring layer 64. The first electrical contact pads 31 pass through A conductive blind via 53 and the first conductive trace layer 63 are electrically connected to each other, and the second electrical contact pad 32 is electrically connected to the second conductive trace layer 64 via the second conductive via 54.

The first conductive blind via 53 can be formed by the following method:

First, a first blind via 55 is formed in the first conductive layer 61 and the first dielectric layer 51 by laser ablation, and the first electrical contact pad 31 is exposed from the bottom of the first blind via 55.

Then, the conductive metal layer 56 is formed on the inner wall of the first blind via 55 and the first electrical contact pad 31 exposed from the first blind via 55, thereby obtaining the first conductive via 53. The conductive metal layer 56 can be formed by electroless copper plating and copper plating. It can be understood that the conductive metal layer 56 can also be formed on the entire first conductive layer 61 to increase the thickness of the first conductive layer 61.

The method of forming the second conductive via 54 may be the same as the method of forming the first conductive via 53.

The first conductive wiring layer 63 and the second conductive wiring layer 64 may be formed by an image transfer process and an etching process. In this embodiment, the first conductive circuit layer 63 includes a plurality of first conductive lines 631 and a plurality of third electrical contact pads 632. The first conductive line 631 is electrically connected between the first conductive blind via 53 and the third electrical contact pad 632. The second conductive circuit layer 64 includes a second conductive trace 641 and a fourth electrical contact pad 642. The second conductive line 641 is electrically connected between the second conductive blind via 54 and the fourth electrical contact pad 642. It can be understood that the number of the first conductive lines 631 and the number of the third electrical contact pads 632 can be set according to the wafer to be packaged, and the wafer to be packaged needs to be performed with the plurality of third electrical contact pads 632. When connected, the first conductive circuit layer 63 may be provided with a plurality of first conductive lines 631 and a plurality of third electrical contact pads 632. Similarly, the number of the fourth electrical contact pads 642 and the second conductive lines 641 may be plural.

In the seventh step, referring to FIG. 11 , a first solder resist layer 71 is formed on the first conductive trace 631 , and a first protective layer 72 is formed on the third electrical contact pad 632 . A second solder resist layer 81 is formed on the second conductive trace 641, and a second protective layer 82 is formed on the fourth electrical contact pad 642.

The first solder resist layer 71 and the second solder resist layer 81 can be formed by printing a liquid solder resist ink and then baking and curing. The first protective layer 72 and the second protective layer 82 may be formed by nickel plating gold.

In the eighth step, referring to FIG. 12 and FIG. 13, the annular slit 105 is cut along the boundary line between the product region 103 and the scrap region 104, thereby obtaining the first carrier substrate 100a and the second carrier substrate 100b which are separated from each other.

In the product area 103, the first release film 13 and the second release film 14 are in contact with the film 15, and the first copper foil 11 and the second copper foil 12 are not bonded to the film 15, when along the product area 103. When cutting with the boundary line of the scrap area 104, the first copper foil 11 is separated from the first release film 13, and the second release film 14 and the second copper foil 12 are separated from each other, thereby obtaining two first carriers separated from each other. The substrate 100a and the second carrier substrate 100b.

In the ninth step, referring to FIG. 14, the first copper foil 11 of the first carrier substrate 100a is removed, so that the first electrical contact pad 31 is exposed to obtain the first carrier plate 10a, and the second copper foil of the second carrier substrate 100b is removed. 12, the second electrical contact pad 32 is exposed to obtain the second carrier plate 10b.

In this step, the first copper foil 11 and the second copper foil 12 are removed by etching. When etching is performed, a portion of the first electrical contact pads 31 adjacent to the first copper foil 11 may also be removed, and a portion of the second electrical contact pads 32 adjacent to the second copper foil 12 may be removed to reduce The thickness of the first first electrical contact pad 31 and the second electrical contact pad 32.

It can be understood that when a plurality of circuit board units are included in the product area 103, after this step, a step of cutting may be further included to form each of the circuit board units correspondingly into one carrier board unit.

The manufacturing method of the carrier board provided by the technical solution may further include the step of performing electrical measurement on the obtained carrier boards 10a and 10b to detect the electrical performance of the obtained carrier board. Referring to FIG. 15 , the manufacturing method of the carrier board may further include the step of forming a third protective layer 90 on the exposed surface of the first electrical contact pad 31 and the second electrical contact pad 32 , the third protection. Layer 90 can be an organic solder mask (OSP).

In the manufacturing process of the carrier board provided by the technical solution, the release films 13 and 14 having a cross-sectional area smaller than that of the first copper foil 11 and the second copper foil 12 are disposed on both sides of the film 15, so that conductive is formed in the fabrication. After the line, the film can be easily separated from the first carrier substrate and the second carrier substrate. Therefore, the manufacturing method of the carrier board provided by the technical solution can avoid the use of a special copper foil structure which is relatively expensive, thereby reducing the manufacturing cost of the carrier board.

However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.

10a. . . First carrier board

10b. . . Second carrier

11. . . First copper foil

12. . . Second copper foil

13. . . First release film

14. . . Second release film

15. . . film

16. . . First tool hole

17. . . Second tool hole

31. . . First electrical contact pad

32. . . Second electrical contact pad

41. . . First photoresist pattern

42. . . Second photoresist pattern

51. . . First dielectric layer

52. . . Second dielectric layer

53. . . First conductive blind hole

54. . . Second conductive blind hole

61. . . First conductive layer

62. . . Second conductive layer

63. . . First conductive circuit layer

64. . . Second conductive circuit layer

71. . . First solder mask

72. . . First protective layer

81. . . Second solder mask

82. . . Second protective layer

100a. . . First carrier substrate

100b. . . Second carrier substrate

101. . . First surface

102. . . Second surface

103. . . Product area

104. . . Waste area

105. . . incision

110. . . Multilayer substrate

151. . . central area

152. . . Marginal zone

631. . . First conductive line

632. . . Third electrical contact pad

641. . . Second conductive line

642. . . Fourth electrical contact pad

90. . . Third protective layer

1 is a schematic cross-sectional view of a first copper foil, a first release film, a film, a second release film, and a second copper foil according to an embodiment of the present application.

2 is a schematic cross-sectional view showing a multilayer substrate obtained by pressing a first copper foil, a first release film, a film, a second release film, and a second copper foil according to an embodiment of the present invention.

3 is a cross-sectional view showing the first tool hole formed in the carrier substrate of FIG. 2.

4 is a cross-sectional view showing a first photoresist pattern formed on the first sputtered copper layer of FIG. 3 and a second photoresist pattern formed on the second sputtered copper layer.

FIG. 5 is a cross-sectional view showing the first electrical contact pad formed in the first photoresist pattern and the second electrical contact pad formed in the second photoresist pattern.

FIG. 6 is a cross-sectional view of FIG. 5 after removing the first photoresist pattern and the second photoresist pattern.

7 is a schematic cross-sectional view showing the first copper foil surface of FIG. 6 being pressed against the first dielectric layer and the first conductive layer and the second dielectric layer and the second conductive layer being pressed against the surface of the second copper foil.

8 and 9 are schematic cross-sectional views showing the formation of a first conductive via hole in the first dielectric layer and the first conductive layer of FIG. 7 and a second conductive via hole in the second dielectric layer and the second conductive layer.

FIG. 10 is a cross-sectional view showing the first conductive layer of FIG. 9 forming a first conductive circuit layer, and the second conductive layer being formed to form a second conductive circuit layer.

11 is a first solder resist layer formed on the first conductive line of FIG. 10, a first protective layer is formed on the third electrical contact pad, a second solder resist layer is formed on the second conductive trace, and a fourth solder contact pad is formed on the fourth conductive pad. Schematic diagram of the cross section after the second protective layer.

12 and 13 are schematic cross-sectional views showing the first carrier substrate and the second carrier substrate cut.

14 is a cross-sectional view showing the first carrier substrate in FIG. 13 with the first copper foil removed to obtain the first carrier, and the second carrier substrate to remove the second copper foil to obtain the second carrier.

15 is a cross-sectional view showing the first carrier and the second carrier of FIG. 14 after forming a third protective layer.

10a. . . First carrier board

10b. . . Second carrier

31. . . First electrical contact pad

32. . . Second electrical contact pad

53. . . First conductive blind hole

54. . . Second conductive blind hole

71. . . First solder mask

72. . . First protective layer

641. . . Second conductive line

642. . . Fourth electrical contact pad

90. . . Third protective layer

Claims (12)

A method for manufacturing a carrier board, comprising the steps of:
Providing a first copper foil, a first release film, a film, a second release film, and a second copper foil, the film having a central region, a shape and a size of the first release film and the second release film The shape and size of the central area correspond to each other;
Pressing the first copper foil, the first release film, the film, the second release film and the second copper foil as a whole, the two sides of the central portion of the film are separated from the first release film and the second release film The films are in contact with each other to obtain a multi-layer substrate comprising a product region and a waste region surrounding the product region, the orthographic projection of the product region on the surface of the first copper foil being located at the central projection of the central portion on the surface of the first copper foil within;
Forming a plurality of first electrical contact pads on the surface of the first copper foil, and forming a plurality of second electrical contact pads on the surface of the second copper foil;
Pressing the first dielectric layer and the first conductive layer on the surface of the plurality of first electrical contact pads and the first copper foil, and pressing the surface of the plurality of the second electrical contact pads and the second copper foil a second dielectric layer and a second conductive layer;
Forming a first conductive via hole in the first dielectric layer and the first conductive layer, and forming a first conductive layer to form a third electrical contact pad, and forming a plurality of layers in the second dielectric layer and the second conductive layer Two conductive blind holes, and the second conductive layer is formed to form a plurality of fourth electrical contact pads;
Cutting along the boundary line between the product area and the scrap area, and the first copper foil in the product area is naturally separated from the first release film, and the second copper foil in the product area is naturally separated from the second release film, thereby Obtaining a first carrier substrate and a second carrier substrate separated from each other; and removing the first copper foil from the first carrier substrate to obtain a first carrier plate, and removing the second copper foil from the second carrier substrate to obtain a second carrier plate . The method of fabricating a carrier board according to claim 1, wherein the plurality of first conductive blind vias are in one-to-one correspondence with the plurality of first electrical contact pads, and the plurality of second conductive blind vias and the plurality of second electrical Sexual contact points correspond one-to-one. The method of fabricating a carrier board according to claim 2, wherein, when the third electrical contact pad is formed, a plurality of first conductive lines are formed, the plurality of first conductive lines and the plurality of third electrical lines. The contact pads are electrically connected to each other, and each of the first electrical contact pads is electrically connected to each other through a corresponding first conductive blind hole, a corresponding first conductive line and a corresponding third electrical contact pad; When the four electrical contact pads are formed, a plurality of second conductive lines are formed, and the plurality of second conductive lines and the plurality of fourth electrical contact pads are electrically connected one by one, and each of the second electrical contact pads passes corresponding The second conductive blind via and the second conductive trace are electrically connected to the fourth electrical contact pad. The method for manufacturing a carrier board according to claim 3, wherein before the cutting along the boundary line between the product area and the scrap area, the method further comprises the steps of:
Forming a first solder resist layer on the first conductive wiring layer such that the first solder resist layer covers a surface of the plurality of first conductive traces and a surface of the first dielectric layer exposed from the first conductive trace layer, And exposing the plurality of third electrical contact pads; and forming a second solder resist layer on the second conductive circuit layer such that the second solder resist layer covers the surface of the plurality of second conductive lines and The second conductive circuit layer exposes a surface of the second dielectric layer and exposes the plurality of fourth electrical contact pads. The manufacturing method of the carrier board according to claim 4, wherein after the first solder resist layer is formed, a first protective layer is further formed on the surface of the third electrical contact pad, and after the second solder resist layer is formed, The fourth electrical contact pad surface forms a second protective layer. The method of fabricating a carrier sheet according to claim 1, wherein the first copper foil and the second copper foil each have a thickness of 10 micrometers to 15 micrometers. The method of manufacturing the carrier sheet according to claim 1, wherein the first release film and the second release film are a PE release film or a PET release film. The method of fabricating a carrier board according to claim 1, wherein the first copper foil is removed from the surface of the first dielectric layer by etching, and the second copper foil is etched from the second dielectric layer. Surface removal. The method of fabricating a carrier board according to claim 1, wherein after forming the multi-layer substrate, further comprising forming a first tool hole in the multi-layer substrate, the first tool hole being formed outside the product area of the multi-layer substrate. The manufacturing method of the carrier board according to claim 1, wherein the product area of the multi-layer substrate comprises a plurality of product units, and the manufacturing method of the carrier board further comprises cutting a plurality of first carrier boards to obtain The carrier board unit corresponding to each product unit. The method of fabricating a carrier board according to claim 1, further comprising forming a third protective layer on the surface of the exposed first electrical contact pad and the second electrical contact pad. The method of fabricating a carrier board according to claim 1, wherein the first dielectric layer and the first conductive layer are laminated on the plurality of first electrical contact pads and the first copper foil surface, in the plurality of After the second electrical contact pad and the second copper foil surface are pressed against the second dielectric layer and the second conductive layer, the first electrical layer, the first conductive layer, the multilayer substrate, and the second dielectric layer are further laminated A second tool hole is formed in the dielectric layer and the second conductive layer, and the second tool hole is located outside the product area.