TWI434386B - Method of fabricating package structure - Google Patents

Description

Method of manufacturing package structure

The invention relates to a method for manufacturing a package structure, in particular to a method for forming a package structure having an external electrical connection point.

The conventional semiconductor package structure uses a lead frame as a wafer carrier on which a semiconductor wafer is attached, and the lead frame has a wafer holder and a plurality of pins formed around the wafer holder. The semiconductor wafer is fixed on the wafer holder, and the semiconductor wafer and the lead are electrically connected by a bonding wire, and then the semiconductor wafer, the wafer holder, the bonding wire and the inner portion of the lead are covered with the packaging material to form the wire. Semiconductor package structure.

There are many types of semiconductor package structures using lead frames as wafer carriers, such as QFP (Quad Flat Package), QFN (Quad-Flat Non-leaded), SOP (Small Outline Package), or DIP (Dual in -line Package), etc., in order to improve the heat dissipation efficiency of the semiconductor package structure and the small size requirement of the Chip Scale Package (CSP), the QFN semiconductor package structure or the exposed pad type exposed at the bottom of the wafer holder is currently used. Pad) The semiconductor package structure is the mainstream of the package.

For the QFN semiconductor package structure, it is characterized in that no external pins are provided, that is, pins which are electrically connected to the outside in a conventional quadrilateral planar semiconductor package structure (QFP) are not formed, thereby reducing the semiconductor package. The size of the structure.

Please refer to the schematic diagram of a conventional QFN semiconductor package structure shown in FIGS. 1A and 1B, wherein the first FIG. 1A is a cross-sectional view, and the first FIG. B is a top view of FIG. 1A; The semiconductor wafer 12 is fixed on the lead frame wafer holder 10 of the eleventh, and the semiconductor wafer 12 is electrically connected to the lead 11 by the bonding wire 13 on the lead frame wafer holder 10, the semiconductor wafer 12, and the bonding wire 13 Forming the package material 14 and exposing the bottom surface of the lead frame wafer holder 10 and the lead 11 to the surface of the package material 14, so that the QFN semiconductor package structure is soldered by the exposed pin 11 (in the drawing) Not shown) is electrically connected to an external device such as a printed circuit board (not shown).

However, the conventional semiconductor package structure has the pins 11 formed only on the periphery thereof, and thus the arrangement and the number of the pins 11 are greatly limited, so that the applicable range is small.

Therefore, how to avoid the problem that the arrangement and the number of external electrical connection pins of the package structure in the prior art are limited and difficult to apply, has become a problem to be solved at present.

In view of the above-mentioned various deficiencies of the prior art, the main object of the present invention is to provide a method of fabricating a package structure having a preferred external electrical connection point.

To achieve the above and other objects, the present invention discloses a method for fabricating a package structure, comprising: providing a carrier unit having opposite surfaces, having a first metal layer on both surfaces thereof; forming a first layer on the first metal layer a second metal layer; forming a plurality of electrical contact pads on the second metal layer; forming a dielectric layer on the second metal layer and the electrical contact pads, and forming a circuit layer on the dielectric layer, and Forming a plurality of conductive blind holes electrically connected to the circuit layer and the electrical contact pads, and the circuit layer has a plurality of wire bonding pads, and each of the wire bonding pads of the partition has a plurality of wire bonding pads, wherein the dielectric layer The material of the layer may be ABF (Ajinomoto Build-up Film), BCB (Benzocyclo-buthene), LCP (Liquid Crystal Polymer), PI (Poly-imide), PPE (Poly (phenylene ether)), PTFE (Poly (tetra-tetra-) Fluoroethylene)), FR4, FR5, BT (Bismaleimide Triazine), aromatic nylon (Aramide), or mixed epoxy fiberglass (Glass fiber); forming an insulating protective layer on the dielectric layer and the wiring layer, and the insulating layer a plurality of openings are formed in the protective layer, A wire mat of each of the partitions is exposed to each of the openings to form a pair of upper and lower surface package substrates, wherein the material for forming the insulating protective layer may be ABF (Ajinomoto Build-up Film) or BCB (Benzocyclo- Buthene), LCP (Liquid Crystal Polymer), PI (Poly-imide), PPE (Poly (phenylene ether)), PTFE (Poly (tetra-fluoroethylene)), FR4, FR5, BT (Bismaleimide Triazine), aromatic nylon (Aramide) ), solder resist layer or mixed epoxy fiberglass (Glass fiber); along the upper and lower pairs of the entire surface of the package substrate edge and the inside of the first cutting, in order to become a plurality of upper and lower pairs of package substrate blocks, Each of the upper and lower pairs of package substrate blocks has upper and lower pairs of package substrate units arranged in an array of (m×n), wherein m and n are integers greater than 1; and the package substrates are respectively paired with each other The semiconductor wafer is connected to the unit, and the semiconductor wafer has an active surface and an inactive surface. The non-active surface is fixed on the insulating protective layer, and the active surface has a plurality of electrode pads, and each of the electrode pads is connected by a bonding wire. Corresponding to electrical connection to each a pad; forming a package on the semiconductor wafer, the insulating protective layer, the bonding pad and the bonding wire, and forming a package structure block having a plurality of upper and lower pairs of package structure units; the first metal layer is self-supporting Separating the cells to separate the upper and lower pairs of package structure blocks into two independent package structure blocks; removing the first metal layer and the second metal layer to expose the surface of the electrical contact pad; and the second time The package structure block is cut to separate into a plurality of package structure units.

In the above method of manufacturing the package structure, the process of the carrying unit may include: providing a carrier board having opposite surfaces; forming a peeling layer having an area smaller than the carrier board on both surfaces of the carrier board; An adhesive layer is formed on the surface of the plate and the peeling layer is not formed so that the adhesive layer surrounds the peeling layer; and the first metal layer is formed on the peeling layer and the adhesive layer. Alternatively, the process of the carrying unit may include: providing a carrier board having opposite surfaces; forming an adhesive layer on both surfaces of the carrier board; and uniformly covering the adhesive layer with the area smaller than the carrier board a release layer surrounding the adhesive layer; and forming the first metal layer on the release layer and the adhesive layer.

In the above method, the first cut cut edge can pass through the peeling layer.

According to the manufacturing method of the package structure, the process of the electrical contact pads may include: forming a resist layer on the second metal layer, and the middle resist layer forms a plurality of resistive opening, the exposed portion a second metal layer; forming the electrical contact pad on the second metal layer in each of the openings of the resist layer; and removing the resist layer.

In the above method, the dielectric layer and the circuit layer may be plural, and constitute a build-up structure, the build-up structure includes at least one dielectric layer, a circuit layer formed on the dielectric layer, and a plurality of layers. The conductive layer is electrically connected to the conductive layer and the conductive contact hole of the electrical contact pad, and the circuit layer of the outermost layer of the buildup structure has the wire pad of the partition.

In the above method, the composition may include forming a first surface treatment layer on the wire bonding pads, and the material forming the first surface treatment layer may be nickel/gold (Ni/Au), nickel/palladium (Ni/Pd). ), Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG), Tin (Sn), Silver (Ag), or Gold (Au).

In the above method for manufacturing the package structure, the second surface treatment layer may be formed on the exposed surface of each of the electrical contact pads, and the material forming the second surface treatment layer may be nickel/gold (Ni/Au). Nickel/palladium (Ni/Pd), Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG), Tin (Sn), Silver (Ag), or Gold (Au).

According to the above-mentioned manufacturing method, before the first cutting, the first protective film is formed on the insulating protective layer and the wire bonding pad, and after the first cutting, the first protective film is removed. And before the second cutting, the composite layer comprises forming a second protective film on the dielectric layer and the electrical contact pad, and after the second cutting, removing the second protective film.

In the method of fabricating the package structure described above, before the second cutting, the solder ball may be formed on each of the electrical contact pads.

As can be seen from the above, the method for manufacturing the package structure of the present invention is to first cut the upper and lower pairs of the full-size surface-encapsulated substrate into a plurality of upper and lower pairs of package substrate blocks, and the area of each of the upper and lower pairs of package substrate blocks is moderate and includes There are a plurality of package substrate units that are paired up and down; then, the semiconductor wafer is attached to each of the package substrate units and fixed and protected by the package material; finally, the plurality of package structure units are cut. Compared with the prior art, the manufacturing method of the package structure of the present invention forms a package structure having an array of dense electrical connection pads, so that the application range is wide, and the overall substrate area is effectively utilized; further, the manufacturing method of the present invention The package substrate manufacturing and the semiconductor chip package are integrated, and the semiconductor chip package can be performed on all the package substrate units in each of the package substrate blocks at one time to simplify the process steps and increase the productivity; further, the area of the package substrate block of the present invention Therefore, each of the package substrate units in each of the package substrate blocks can have process precisions and yields that are similar to each other. Therefore, the method for manufacturing the package structure of the present invention has a wide application range, high productivity, and good quality. The rate is more consistent and so on.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

2A to 2J are schematic cross-sectional views showing a method of fabricating the package structure of the present invention; wherein the 2A' diagram is another aspect of FIG. 2A, and the 2E' diagram is another 2E diagram. In the aspect, the 2F' diagram is a plan view of the 2Fth diagram.

As shown in Figs. 2A and 2A', a carrier unit 2 having opposite surfaces is provided, and a first metal layer 221 is provided on both surfaces of the carrier unit 2.

The process of the above-mentioned carrying unit 2 can be as shown in FIG. 2A, and a carrier board 20 having opposite surfaces is provided. Then, a peeling layer 211 having a smaller area than the carrier board 20 is formed on both surfaces of the carrier board 20. After that, an adhesive layer 212 is formed on the surface of the carrier 20 and the peeling layer 211 is not formed, so that the adhesive layer 212 surrounds the peeling layer 211; finally, the peeling layer 211 and the adhesive layer 212 are formed on the adhesive layer 212. A metal layer 221 .

Alternatively, the process of the above-mentioned carrying unit 2 can be as shown in FIG. 2A, providing a carrier 20 having opposite surfaces; an adhesive layer 212 is formed on both surfaces of the carrier 20; A peeling layer 211 having a smaller area than the carrier board 20 and surrounded by the adhesive layer 212 is completely disposed on the layer 212; and a first metal layer 221 is formed on the peeling layer 211 and the adhesive layer 212.

The peeling layer 211 may be a release film, and the material of the first metal layer 221 may be copper, and the first metal layer 221 may be a seed layer for providing a current conduction path in the electroplating process. The following embodiments are illustrated in Figure 2A.

As shown in FIG. 2B, a second metal layer 222 is formed on the first metal layer 221, and the second metal layer 222 may be a stop layer.

As shown in FIG. 2C, a resist layer 23 is formed on the second metal layer 222, and a plurality of resistive opening 230 and a second metal layer 222 of the exposed portion are formed in the resist layer 23; A metal layer 221 is used as a current conducting path for electroplating to form an electrical contact pad 24 on the second metal layer 222 of each of the resist layer openings 230.

As shown in FIG. 2D, the resist layer 23 is removed to expose the second metal layer 222 and the electrical contact pads 24.

As shown in FIG. 2E, a build-up structure 25 is formed on the second metal layer 222 and the electrical contact pad 24. The build-up structure 25 includes at least one dielectric layer 251 formed on the dielectric layer 251. a circuit layer 253, and a plurality of conductive vias 252 formed in the dielectric layer 251 and electrically connected to the circuit layer 253 and the electrical contact pads 24, and the circuit layer 253 of the outermost layer of the buildup structure 25 has a plurality of partitions The wire bonding pad 254s (shown only in FIG. 2F'), and the wire bonding pad 254s of each of the partitions have a plurality of wire bonding pads 254, and the material forming the dielectric layer 251 is ABF (Ajinomoto Build-up Film) and BCB (Benzocyclo). -buthene), LCP (Liquid Crystal Polymer), PI (Poly-imide), PPE (Poly (phenylene ether)), PTFE (Poly (tetra-fluoroethylene)), FR4, FR5, BT (Bismaleimide Triazine), aromatic nylon ( Aramide), or a mixed epoxy glass fiber, and the dielectric layer 251 preferably has a higher glass transition temperature; and then, on the outermost layer of the buildup structure 25 Forming an insulating protective layer 26, and forming a plurality of openings 260 in the insulating protective layer 26 to The wire bonding pads 254s of the respective regions are respectively exposed to the openings 260; then, the first surface treatment layer 271 is formed on the wire bonding pads 254, and the upper and lower pairs of the full-surface package substrate 2a are formed to form the first surface. The material of the treatment layer 271 is nickel/gold (Ni/Au), nickel/palladium (Ni/Pd), electroless nickel/electroplated gold (ENERPIG), tin (Sn), silver (Ag). ), or gold (Au). Alternatively, as shown in FIG. 2E', in another aspect of FIG. 2E, a dielectric layer 251 is formed on the second metal layer 222 and the electrical contact pad 24, and the dielectric layer 251 is formed on the dielectric layer 251. A circuit layer 253 is formed thereon, and a plurality of conductive blind vias 252 electrically connected to the circuit layer 253 and the electrical contact pads 24 are formed in the dielectric layer 251, and the circuit layer 253 has a plurality of wire bonding pads 254s, each of which has a plurality of partitions. The wire bonding pad 254s of the partition has a plurality of wire bonding pads 254, and then an insulating protection layer 26 is formed on the dielectric layer 251 and the circuit layer 253, and a plurality of openings 260 are formed in the insulating protection layer 26 to make the respective regions The wire pad 254s is exposed to each of the openings 260, and then the first surface treatment layer 271 is formed on the wire bonding pads 254 to form a pair of upper and lower surface package substrates 2a. The following implementation is illustrated in Figure 2E.

As shown in FIGS. 2F and 2F', the 2F' is a plan view of FIG. 2F; as shown in the figure, the edge is cut along the edge and the inside of the pair of upper and lower aligned package substrates 2a, and The cutting edge 28 passes through the peeling layer 211 to form a plurality of upper and lower paired package substrate blocks 2b, and each of the upper and lower paired package substrate blocks 2b has an upper and lower paired package arranged in an (m×n) array. The substrate unit 2c; wherein m and n are all integers greater than 1, in the embodiment, m and n are 3 and 2, respectively, but not limited thereto. In addition, before the first cutting, the first protective film (not shown in the figure) is formed on the insulating protective layer 26 and the bonding pad 254 (or the first surface treatment layer 271) to avoid The insulating protective layer 26 and the wire bonding pad 254 (or the first surface treatment layer 271) are affected by liquid or dust during cutting, and after the first cutting, the first protective film is removed.

As shown in FIG. 2G, a semiconductor wafer 29 is attached to each of the pair of upper and lower package substrate units 2c, and the semiconductor wafer 29 has an active surface 29a and an inactive surface 29b. The non-active surface 29b is fixed to the insulation protection. On the layer 26, the active surface 29a has a plurality of electrode pads 291, and each of the electrode pads 291 is electrically connected to each of the bonding pads 254 by bonding wires 30; then, the semiconductor wafer 29 and the insulating protective layer 26 are provided. The wire pad 254 (or the first surface treatment layer 271) and the bonding wire 30 form a package material 31, and become a package structure block 2b' having a plurality of upper and lower pairs of package structure units 2c'.

As shown in FIG. 2H, the first metal layer 221 is separated from the carrier unit 2 to separate the upper and lower pairs of package structure blocks 2b' into two independent package structure blocks 2b", and each of the two The package structure block 2b" has package structure units 2c" arranged in an (m x n) array.

As shown in FIG. 2I, the first metal layer 221 and the second metal layer 222 are removed, and the surface of the electrical contact pad 24 is exposed, and a second surface treatment layer is formed on the exposed surface of each of the electrical contact pads 24. 272, and the material forming the second surface treatment layer 272 is nickel/gold (Ni/Au), nickel/palladium (Ni/Pd), and nickel-palladium immersion gold (Electroless Nickel/Electroless Palladium/Immersion Gold, ENEPIG). Tin (Sn), silver (Ag), or gold (Au).

As shown in Fig. 2J, a second crop is performed to separate the package structure block 2b" into a plurality of package structure units 2c". In addition, before the second cutting, the second protective film (not shown in the figure) is formed on the dielectric layer 251 and the electrical contact pad 24 (or the second surface treatment layer 272). The dielectric layer 25 and the electrical contact pad 24 (or the second surface treatment layer 272) are prevented from being affected by liquid or dust during cutting, and after the second cutting, the second protective film is removed. The electrical contact pad 24 (or the second surface treatment layer 272) can be directly used for electrical connection with a Land Grid Array (LGA) structure; or, before the second cutting And forming a solder ball (not shown in the figure) on each of the electrical contact pads 24 (or the second surface treatment layer 272) for subsequent electrical connection.

In the above method, the upper and lower pairs of the full-face package substrate may be separated into two independent full-page package substrates, and then cut into a plurality of package substrate blocks, and the other steps are the same as described above. Repeat them.

In summary, the method for manufacturing the package structure of the present invention first cuts the upper and lower pairs of the full-face package substrate into a plurality of upper and lower pairs of package substrate blocks, so that the area of the upper and lower pairs of package substrate blocks is moderate. And comprising a plurality of package substrate units in a pair of upper and lower layers; then, the semiconductor wafer is attached to each of the package substrate units and fixed and protected by the package material; finally, the plurality of package structure units are cut. Compared with the prior art, the manufacturing method of the package structure of the present invention forms a package structure having an array of dense electrical connection pads, so that the application range is wide, and the overall substrate area is effectively utilized; further, the method of the invention is integrated. Package substrate manufacturing and semiconductor chip packaging, and semiconductor chip packaging can be performed on all package substrate units in each package substrate block at a time to simplify the process steps and increase productivity; further, the area of the package substrate of the present invention is moderate Therefore, each of the package substrate units in each of the package substrate blocks can have process precisions and yields that are similar to each other. Therefore, the method for manufacturing the package structure of the present invention has a wide application range, high productivity, and yield. More consistent and other advantages.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

10. . . Lead frame wafer holder

11. . . Pin

12, 29. . . Semiconductor wafer

13. . . Welding wire

14. . . Packaging material

2. . . Bearer unit

2a. . . Upper and lower paired full-face package substrates

2b. . . Upper and lower paired package substrate blocks

2b’. . . Upper and lower paired package blocks

2b"...package block

2c. . . Upper and lower paired package substrate unit

2c’. . . Upper and lower pairs of package structural units

2c"...packaged structural unit

20. . . Carrier board

211. . . Peeling layer

212. . . Adhesive layer

221. . . First metal layer

222. . . Second metal layer

twenty three. . . Resistance layer

230. . . Resistive opening

twenty four. . . Electrical contact pad

25. . . Layered structure

251. . . Dielectric layer

252. . . Conductive blind hole

253. . . Circuit layer

254. . . Line mat

254s. . . Partitioning pad

26. . . Insulating protective layer

260. . . Opening

271. . . First surface treatment layer

272. . . Second surface treatment layer

28. . . Cutting edge

29a. . . Action surface

29b. . . Non-active surface

291. . . Electrode pad

30. . . Welding wire

31. . . Packaging material

m. . . Number of array rows of upper and lower paired package substrate blocks

n. . . Number of array columns of upper and lower paired package substrate blocks

1A and 1B are schematic views of a conventional package structure, wherein FIG. 1A is a cross-sectional view, and FIG. 1B is a plan view of FIG. 1A;

2A to 2J are schematic cross-sectional views showing a method of fabricating the package structure of the present invention, wherein the 2A' diagram is another aspect of FIG. 2A, and the 2E' diagram is another aspect of the 2E diagram, This 2F' diagram is a plan view of the 2Fth diagram.

2b’. . . Upper and lower paired package blocks

2b"...package block

2c"...packaged structural unit

20. . . Carrier board

211. . . Peeling layer

221. . . First metal layer

222. . . Second metal layer

twenty four. . . Electrical contact pad

25. . . Layered structure

251. . . Dielectric layer

252. . . Conductive blind hole

253. . . Circuit layer

254. . . Line mat

26. . . Insulating protective layer

260. . . Opening

271. . . First surface treatment layer

29. . . Semiconductor wafer

29a. . . Action surface

29b. . . Non-active surface

291. . . Electrode pad

30. . . Welding wire

31. . . Packaging material

Claims (15)

A method for fabricating a package structure includes: providing a carrier unit having opposite surfaces, having a first metal layer on both surfaces thereof; forming a second metal layer on the first metal layer; and forming the second metal layer on the first metal layer Forming a plurality of electrical contact pads thereon; forming a dielectric layer on the second metal layer and the electrical contact pads, forming a circuit layer on the dielectric layer, and forming a plurality of electrical connections in the dielectric layer a conductive blind hole of the layer and the electrical contact pad, and the circuit layer has a plurality of wire bonding pads, wherein each of the wire bonding pads of the partition has a plurality of wire bonding pads; an insulating protective layer is formed on the dielectric layer and the circuit layer, and Forming a plurality of openings in the insulating protective layer, so that the wire bonding pads of each of the partitions are correspondingly exposed to the respective openings, thereby forming a pair of upper and lower planar package substrates; and the edges of the upper and lower pairs of the packaged substrates are The first cutting is performed internally to form a plurality of upper and lower pairs of package substrate blocks, wherein the upper and lower pairs of package substrate blocks have upper and lower pairs of package substrate units arranged in an array of (m×n), wherein m and n are both An integer greater than 1; a semiconductor wafer is attached to each of the package substrate units, the semiconductor wafer has an active surface and an inactive surface, the non-active surface is fixed on the insulating protective layer, and the active surface has a plurality of electrode pads, And each of the electrode pads is electrically connected to each of the wire bonding pads by a bonding wire; forming a packaging material on the semiconductor wafer, the insulating protective layer, the wire bonding pad and the bonding wire, and forming a package structure unit having a plurality of upper and lower pairs a pair of upper and lower package structure blocks; separating the first metal layer from the carrier unit to separate the upper and lower pairs of package structure blocks into two independent package structure blocks, and each package structure block Having a package structure unit arranged in an array of (m×n); removing the first metal layer and the second metal layer to expose an electrical contact pad surface; and cutting the package structure block a second time to separate into a plurality Package structural unit. The method for manufacturing a package structure according to claim 1, wherein the process of the load bearing unit comprises: providing a carrier plate having opposite surfaces; and forming an area on both surfaces of the carrier plate that is smaller than the stripping of the carrier plate a layer; an adhesive layer is formed on the surface of the carrier plate and the peeling layer is not formed, so that the adhesive layer surrounds the peeling layer; and the first metal layer is formed on the peeling layer and the adhesive layer. The method for manufacturing a package structure according to claim 1, wherein the process of the load bearing unit comprises: providing a carrier plate having opposite surfaces; forming an adhesive layer on both surfaces of the carrier plate; A peeling layer having an area smaller than the carrying plate and surrounded by the adhesive layer is fully attached; and the first metal layer is formed on the peeling layer and the adhesive layer. The method of manufacturing a package structure according to claim 2 or 3, wherein the first cut cut edge passes through the peeling layer. The method of manufacturing the package structure of claim 1, wherein the process of the electrical contact pad comprises: forming a resist layer on the second metal layer, and forming a plurality of resistive opening in the resist layer; Exposing the second metal layer; forming the electrical contact pad on the second metal layer in each of the barrier layer openings; and removing the resist layer. The method for manufacturing a package structure according to claim 1, wherein the dielectric layer and the circuit layer are plural, and constitute a build-up structure, the build-up structure includes at least one dielectric layer formed on the dielectric a circuit layer on the layer, and a plurality of conductive blind holes formed in the dielectric layer and electrically connected to the circuit layer and the electrical contact pads, and the circuit layer of the outermost layer of the buildup structure has the wire pad of the partition . The method for manufacturing a package structure according to claim 1 is further included on the wire bonding pads to form a first surface treatment layer. The method for manufacturing a package structure according to claim 7, wherein the material for forming the first surface treatment layer is nickel/gold (Ni/Au), nickel/palladium (Ni/Pd), and nickel-palladium immersion gold (Electroless). Nickel/Electroless Palladium/Immersion Gold, ENEPIG), tin (Sn), silver (Ag), or gold (Au). The method for manufacturing a package structure according to claim 1, wherein the second surface treatment layer is formed on the exposed surface of each of the electrical contact pads. The method for manufacturing a package structure according to claim 9, wherein the material for forming the second surface treatment layer is nickel/gold (Ni/Au), nickel/palladium (Ni/Pd), and nickel-palladium immersion gold (Electroless) Nickel/Electroless Palladium/Immersion Gold, ENEPIG), tin (Sn), silver (Ag), or gold (Au). The method for manufacturing a package structure according to claim 1, wherein before the first cutting, the first protective film is formed on the insulating protective layer and the wire pad, and after the first cutting, The first protective film is removed. The method for manufacturing a package structure according to claim 1, wherein before the second cutting, a second protective film is formed on the dielectric layer and the electrical contact pad, and the second cutting is performed. Thereafter, the second protective film is removed. The method for manufacturing a package structure according to claim 1, wherein before the second cutting, a solder ball is formed on each of the electrical contact pads. The method for manufacturing a package structure according to claim 1, wherein the material forming the dielectric layer is ABF (Ajinomoto Build-up Film), BCB (Benzocyclo-buthene), LCP (Liquid Crystal Polymer), PI (Poly- Imide), PPE (Poly (phenylene ether)), PTFE (Poly (tetra-fluoroethylene)), FR4, FR5, BT (Bismaleimide Triazine), aromatic nylon (Aramide), or mixed epoxy fiberglass (Glass fiber). The method for manufacturing a package structure according to claim 1, wherein the material forming the insulating protective layer is ABF (Ajinomoto Build-up Film), BCB (Benzocyclo-buthene), LCP (Liquid Crystal Polymer), PI (Poly- Imide), PPE (Poly (phenylene ether)), PTFE (Poly (tetra-fluoroethylene)), FR4, FR5, BT (Bismaleimide Triazine), aromatic nylon (Aramide), solder mask or mixed epoxy glass fiber (Glass Fiber).