TWI405273B - Method of fabricating package structure - Google Patents

Abstract

A method for fabricating a package structure is proposed, comprising cutting a large package substrate plate into a plurality package substrate blocks each having a plurality of package substrate units; disposing a semiconductor chip on each of the substrate units and the chip being secured and protected by an encapsulant to form a plurality of package structure blocks; and cutting the package structure blocks into a plurality of package structure units. The moderate size of the substrate blocks of the invention enables substrate units to have higher precision and yield in production, and also permits the chip packaging prqcess to be performed on all units at one time, thereby integrating substrate fabrications and chip packaging to simplify manufacturing processes, increase overall yield while decreasing the costs as a result.

Description

Method of manufacturing package structure

The invention relates to a method for manufacturing a package structure, in particular to a method for manufacturing a package structure capable of improving overall productivity and reducing overall cost.

In order to meet the packaging requirements of semiconductor package high integration and miniaturization, and to provide package substrates for most active and passive components and circuit connections, it has gradually evolved from a single-layer board to a multi-layer board. In a limited space, the interlayer area can be used to expand the available wiring area on the board, and it can meet the requirements of integrated circuits with high electron density.

The conventional multilayer circuit board is composed of a core board and a line build-up structure symmetrically formed on both sides thereof, but the use of the core board will result in an increase in the length of the wire and the thickness of the overall structure, and it is difficult to meet the ever-increasing function and volume of the electronic product. However, the ever-shrinking demand has led to the development of circuit boards with no coreless structure to meet the trend of shortening the wire length and reducing the overall structural thickness, as well as the trend of high frequency and miniaturization.

In the current flip chip semiconductor package technology, the active surface of the semiconductor wafer is mounted on a package substrate, and the active surface of the semiconductor wafer is provided with a plurality of electrode pads on the top surface of the package substrate. The plurality of electrical contact pads are electrically connected to the package substrate by electrically connecting the electrode pads and the electrical contact pads by solder bumps.

Compared with the conventional wire bond technology, the flip chip technology is characterized in that the electrical connection between the semiconductor wafer and the package substrate is directly solder bump instead of the general gold wire, and the flip chip technology The advantage is that the package density can be increased to reduce the size of the package component; at the same time, the flip chip technology does not need to use a long length of gold wire, thereby reducing the impedance to improve the electrical function.

The conventional method for fabricating a flip-chip package structure first provides a full-face substrate body having a multi-layer line connection structure, and a plurality of bump pads on the outermost layer of the body of the full-surface substrate, and the substrate is An insulating protective layer is formed on the body, and a plurality of openings are formed in the insulating protective layer, so that the bump pads are correspondingly exposed to the openings, and a surface treatment layer is formed on the bump pads in the openings And forming a full-page package substrate; then, the full-size package substrate is cut into a plurality of package substrate units or a plurality of package substrate strips, and each of the package substrate strips has a plurality of package substrate units; Finally, it is transported to the packaging factory for subsequent crystallization, encapsulation, and/or singulation steps.

However, if the entire package substrate is diced into a plurality of package substrate units, and then the crystallization and packaging steps are performed, only a single package substrate unit is processed at a time, so that the productivity is low and the overall cost is high; After the whole-version package substrate is cut into a plurality of package substrate strips, and then the processes of crystallization, packaging, and singulation are performed, the package substrate strip must retain the frame for the process to be clamped, thereby occupying a large effective area. A waste of material costs.

On the other hand, as the overall thickness of the package substrate becomes thinner, processing steps such as crystallization or packaging of the package substrate unit or the package substrate strip will be more difficult.

However, if the entire package substrate is not first cut into a plurality of package substrate units or a plurality of package substrate strips, and the substrate is directly packaged by a full-face substrate for crystallization, packaging, and singulation, a larger process must be purchased. The overall cost of the device is increased. Moreover, the accuracy of the large-area alignment of the full-page package substrate is low, which tends to cause a large process error in the final package structure unit, thereby affecting the overall yield.

Therefore, how to avoid the problems that the manufacturing method of the package structure in the prior art has complicated steps, resulting in low productivity, waste of excessive effective area of the substrate, and an increase in overall cost has become a problem to be solved at present.

In view of the above-mentioned various deficiencies of the prior art, the main object of the present invention is to provide a method for manufacturing a package structure which can improve overall productivity and reduce overall cost.

To achieve the above and other objects, the present invention discloses a method for manufacturing a package structure, comprising: providing two carrier unit units each having opposite surfaces, and having a metal layer on one surface of each of the carrying units, the two carrying units a surface of the metal layer is bonded to the second adhesive layer; a plurality of electrical contact pads and a build-up structure are sequentially formed on each of the metal layers, the build-up structure comprising at least one dielectric layer formed on the dielectric layer a circuit layer on the electrical layer, and a plurality of conductive blind holes formed in the dielectric layer and electrically connected to the circuit layer and the electrical contact pads, and the circuit layer of the outermost layer of the buildup structure has a plurality of bump pads Forming an insulating protective layer on the outermost layer of the build-up structure, and forming a plurality of openings in the insulating protective layer, so that each of the bump pads is exposed to each of the openings, and plating is formed on each of the bump pads Metal bumps, which become upper and lower pairs of full-face package substrates; the second adhesive layer is removed to separate the upper and lower pairs of full-page package substrates into two independent full-page package substrates; Full face seal The edge of the substrate is internally and internally formed to form a plurality of package substrate blocks, and each of the package substrate blocks has a package substrate unit arranged in an array of (m×n), wherein m and n are integers greater than 1; A semiconductor wafer having an active surface is disposed on the metal bumps of the package substrate unit to form a package structure block having a plurality of package structure units, wherein the active surface has a plurality of electrode pads, and each of the electrode pads is Solder bumps are electrically connected to each of the bump pads; a package is formed on the insulating protective layer and the semiconductor wafers, and the package is filled between the semiconductor wafers and the insulating protective layer to Coating the solder bumps; separating the metal layer from the carrier unit; removing the metal layer; and cutting the package structure block a second time to separate into a plurality of package structure units.

In the manufacturing method of the above package structure, the process of the carrying unit may include: providing a carrier board having two surfaces; forming an adhesive layer on one surface of the carrier board; and uniformly covering the adhesive layer with an area smaller than The carrier plate is surrounded by a release layer surrounded by the adhesive layer; and a metal layer is formed on the release layer and the adhesive layer. Alternatively, the process of the carrying unit may include: providing a carrier board having two surfaces; forming a peeling layer having a smaller area than the carrier board on a surface of the carrier board; and forming a surface of the peeling layer and not forming An adhesive layer is formed on the surface of the release layer so that the adhesive layer surrounds the peeling layer; and a metal layer is formed on the peeling layer and the adhesive layer.

In the above method of manufacturing the package structure, the first cut cut edge can pass through the peeling layer.

According to the manufacturing method of the package structure, the first surface treatment layer is formed on each of the metal bumps, and the material forming the first surface treatment layer may be nickel/gold (Ni/Au) or nickel. Palladium immersion gold (Electroless Nickel/Electroless Palladium/Immersion Gold, ENEPIG), tin (Sn), silver (Ag), or gold (Au).

In the above method, before the second cutting, the solder ball is formed on each of the electrical contact pads.

As can be seen from the above, the method for manufacturing the package structure of the present invention is to first cut the upper and lower pairs of the full-size surface-encapsulated substrate into a plurality of upper and lower pairs of package substrate blocks, and the area of each of the upper and lower pairs of package substrate blocks is moderate and The package substrate unit has a plurality of upper and lower pairs; then, the semiconductor wafer is mounted on each of the package substrate units and fixed and protected by the package material; finally, the plurality of package structure units are cut. Compared with the prior art, the package structure of the present invention integrates package substrate manufacturing and semiconductor chip package, and can perform semiconductor chip packaging on all package substrate units in each package substrate block at a time to simplify steps and increase productivity. In addition, the carrier board is skillfully used in the manufacturing process of the present invention, so that it can be used for the packaging process of the ultra-thin substrate; further, the area of the package substrate in the present invention is moderate, so each of the package substrate blocks In addition to high process accuracy and yield, the package substrate unit also saves wiring costs and operating time and increases throughput.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

1A to 1H are schematic cross-sectional views showing a method of fabricating a package structure of the present invention; wherein the first A' is a plan view of Fig. 1A, and the first D' is a plan view of Fig. 1D.

As shown in FIGS. 1A and 1A', two carrier units 2 each having opposite surfaces are provided, and a metal layer 22 is provided on one surface of each of the carrier units 2, and the two carrier units 2 do not have a metal layer 22 The surfaces are joined by a second adhesive layer 212'.

The process of the above-mentioned carrying unit 2 can be as shown in FIG. 1A, and a carrier board 20 having two surfaces is provided; an adhesive layer 212 is formed on one surface of the carrier board 20; then, the adhesive layer 212 is fully attached. A peeling layer 211 having an area smaller than the carrier plate 20 and surrounded by the adhesive layer 212 is provided; then a metal layer 22 is formed on the peeling layer 211 and the adhesive layer 212.

Alternatively, the process of the above-mentioned carrying unit 2 can be as shown in FIG. 1A, providing a carrier plate 20 having two surfaces; forming a peeling layer 211 having a smaller area than the carrier plate 20 on one surface of the carrier plate 20; Next, an adhesive layer 212 is formed on the surface of the peeling layer 211 and the surface of the peeling layer 211 is not formed, so that the adhesive layer 212 surrounds the peeling layer 211; and the peeling layer 211 and the adhesive layer 212 A metal layer 22 is formed thereon.

The peeling layer 211 can be a release film, and the metal layer 22 can be made of copper, and the metal layer 22 can serve as a seed layer for the current conduction path in the electroplating process. The following is illustrated in Figure 1A.

As shown in FIG. 1B, a plurality of electrical contact pads 23 and a build-up structure 24 are sequentially formed on each of the metal layers 22. The build-up structure 24 includes at least one dielectric layer 241 formed on the dielectric layer 241. The upper circuit layer 243 and the plurality of conductive vias 242 formed in the dielectric layer 241 and electrically connected to the circuit layer 243 and the electrical contact pads 23; wherein the material forming the dielectric layer 241 may be ABF ( Ajinomoto Build-up Film), BCB (Benzocyclo-buthene), LCP (Liquid Crystal Polymer), PI (Poly-imide), PPE (Poly (phenylene ether)), PTFE (Poly (tetra-fluoroethylene)), FR4, FR5 , BT (Bismaleimide Triazine), aromatic nylon (Aramide), or mixed epoxy glass fiber (Glass fiber), and the outermost layer of the layered structure 24 243 has a plurality of bump pads 244; An insulating protective layer 25 is formed on the outermost layer of the build-up structure 24, and a plurality of openings 250 are formed in the insulating protective layer 25, so that the bump pads 244 are correspondingly exposed to the openings 250, respectively. The block pad 244 is plated to form the metal bumps 26, and becomes a pair of upper and lower surface package substrates 2a; A first surface treatment layer 27 is formed on each of the metal bumps 26. The material of the first surface treatment layer 27 may be nickel/gold (Ni/Au), nickel-palladium immersion gold (Electroless Nickel/Electroless Palladium/Immersion). Gold, ENEPIG), tin (Sn), silver (Ag), or gold (Au).

As shown in Fig. 1C, the second adhesive layer 212' is removed to separate the upper and lower paired full-size package substrates 2a into two separate full-size package substrates 2a'.

As shown in FIGS. 1D and 1D', the first 1D' is a plan view of the 1D view; as shown in the figure, the edge is cut along the edge and the inside of the full-width package substrate 2a', and the edge is cut. 28, through the peeling layer 211, to form a plurality of package substrate blocks 2b, and each of the package substrate blocks 2b has a package substrate unit 2c arranged in an (m×n) array; wherein m and n are integers greater than 1 In the present embodiment, m and n are 6 and 5, respectively, but are not limited thereto. In addition, before the first cutting, the first protective film may be formed on the insulating protective layer 25 and the metal bump 26 (or the first surface treatment layer 27 thereon) (not shown in the drawing) In order to prevent the insulating protective layer 25 and the metal bumps 26 (or the first surface treatment layer 27 thereon) from being affected by liquid or dust during cutting, and removing the first after the first cutting A protective film.

As shown in FIG. 1E, a semiconductor wafer 29 having an active surface 29a is attached to each of the package substrate units 2c to form a package structure block 2b' having a plurality of package structure units 2c', and the active surface 29a has A plurality of electrode pads 291 are formed, and each of the electrode pads 291 is electrically connected to each of the bump pads 244 by solder bumps 30. Then, a package 31 is formed on the insulating protective layer 25 and the semiconductor wafers 29 The package material 31 is filled between the semiconductor wafers 29 and the insulating protective layer 25 to cover the solder bumps 30.

The metal layer 22 is separated from the carrier unit 2 as shown in FIG. 1F.

As shown in FIG. 1G, the metal layer 22 is removed to expose the electrical contact pads 23, and a solder ball 32 or a second surface treatment layer is formed on each of the electrical contact pads 23 (not shown in the drawings). The material forming the second surface treatment layer may be nickel/gold (Ni/Au), electroless nickel/electroplated gold (ENEPIG), tin (Sn), silver (Ag). , or gold (Au).

As shown in Fig. 1H, a second cropping is performed to separate the package structure block 2b' into a plurality of package structure units 2c'. In addition, before the second cutting, the second protective film may be formed on the electrical contact pads 23 (or the solder balls 32 or the second surface treatment layer thereon) and the dielectric layer 241 (Fig. (not shown) to prevent the dielectric layer 241 and the electrical contact pads 23 (or the solder balls 32 or the second surface treatment layer thereon) from being affected by liquid or dust during cutting, and in the second After the second cutting, the second protective film is removed.

In summary, the package structure of the present invention firstly cuts the upper and lower pairs of package substrates into a plurality of package substrate blocks in pairs, and the area of each of the upper and lower pairs of package substrate blocks is moderate. And having a plurality of package substrate units having a plurality of upper and lower pairs; then, the semiconductor wafer is attached to each of the package substrate units and fixed and protected by the package material; finally, the plurality of package structure units are cut. Compared with the prior art, the package structure of the present invention integrates package substrate manufacturing and semiconductor chip package, and can perform semiconductor chip packaging on all package substrate units in each package substrate block at a time to simplify steps and increase productivity. In addition, the carrier board is skillfully used in the manufacturing process of the present invention, so that it can be used for the packaging process of the ultra-thin substrate; further, the area of the package substrate in the present invention is moderate, so each of the package substrate blocks In addition to high manufacturing precision and yield, the package substrate unit can also save wiring costs and operating time, and increase productivity.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

2. . . Bearer unit

2a. . . Upper and lower paired full-face package substrates

2a’. . . Full-page package substrate

2b. . . Package substrate block

2b’. . . Package structure block

2c. . . Package substrate unit

2c’. . . Package structure unit

20. . . Carrier board

211. . . Peeling layer

212. . . First adhesive layer

212’. . . Second adhesive layer

twenty two. . . Metal layer

twenty three. . . Electrical contact pad

twenty four. . . Layered structure

241. . . Dielectric layer

242. . . Conductive blind hole

243. . . Circuit layer

244. . . Bump pad

25. . . Insulating protective layer

250. . . Opening

26. . . Metal bump

27. . . First surface treatment layer

28. . . Cutting edge

29. . . Semiconductor wafer

29a. . . Action surface

291. . . Electrode pad

30. . . Solder bump

31. . . Packaging material

32. . . Solder ball

m. . . Number of array rows of package substrate blocks

n. . . Number of array columns of package substrate blocks

1A to 1H are schematic cross-sectional views showing a method of manufacturing the package structure of the present invention; wherein the first A' figure is another aspect of Fig. 1A, and the first D' figure is a plan view of Fig. 1D.

2a’. . . Full-page package substrate

2b. . . Package substrate block

2c. . . Package substrate unit

28. . . Cutting edge

m. . . Number of array rows of package substrate blocks

n. . . Number of array columns of package substrate blocks

Claims (9)

A method for manufacturing a package structure includes: providing two load-bearing units each having opposite surfaces, having a metal layer on one surface of each of the load-bearing units, and a second between the surfaces of the two load-bearing units not having a metal layer The adhesive layer is combined; a plurality of electrical contact pads and a build-up structure are sequentially formed on each of the metal layers, and the outermost surface of the build-up structure has a plurality of bump pads; and an insulating protective layer is formed on the outermost layer of the build-up structure And forming a plurality of openings in the insulating protective layer, so that the bump pads are correspondingly exposed to the openings; and each of the bump pads is plated with metal bumps to form a full-face package Substrate; removing the second adhesive layer to separate the upper and lower pair of full-face package substrates into two independent full-page package substrates; first cutting the edge and the inside of the full-size package substrate to form a plurality of packages The substrate block and each of the package substrate blocks have a package substrate unit arranged in an array of (m×n), wherein m and n are integers greater than 1; and the metal bumps of each of the package substrate units Connect a semiconductor wafer having an active surface to form a package structure block having a plurality of package structure units, wherein the active surface has a plurality of electrode pads, and each of the electrode pads is electrically connected to each of the bumps by solder bumps a solder pad; forming a package on the insulating protective layer and the semiconductor wafers; separating the metal layer from the carrying unit; removing the metal layer; and cutting the package structure block a second time to separate into a plurality of packages Structural units. The method for manufacturing a package structure according to claim 1, wherein the process of the load bearing unit comprises: providing a carrier plate having two surfaces; forming an adhesive layer on one surface of the carrier plate; and comprehensively forming the adhesive layer A release layer having an area smaller than the carrier plate and surrounded by the adhesive layer is attached; and the metal layer is formed on the release layer and the adhesive layer. The method of manufacturing the package structure of claim 1, wherein the process of the load bearing unit comprises: providing a carrier plate having two surfaces; forming a peeling layer having a smaller area than the carrier plate on a surface of the carrier plate; An adhesive layer is formed on a surface of the surface on which the peeling layer is formed and the peeling layer is not formed, so that the adhesive layer surrounds the peeling layer; and the metal layer is formed on the peeling layer and the adhesive layer. The method of manufacturing a package structure according to claim 2 or 3, wherein the first cut cut edge passes through the peeling layer. The method of fabricating a package structure according to claim 1, wherein the build-up structure comprises at least one dielectric layer, a circuit layer formed on the dielectric layer, and a plurality of layers formed in the dielectric layer and electrically And connecting the circuit layer and the conductive contact hole of the electrical contact pad, and the circuit layer of the outermost layer of the buildup structure has the bump pads. The method of fabricating the package structure of claim 1, wherein the package material is filled between the semiconductor wafer and the insulating protective layer to encapsulate the solder bumps. The method for manufacturing a package structure according to claim 1 is further comprising forming a first surface treatment layer on each of the metal bumps. The method for manufacturing a package structure according to claim 7 , wherein the material forming the first surface treatment layer is nickel/gold (Ni/Au), and electroless nickel/iridated Palladium/Immersion Gold (Electroless Nickel/Electroless Palladium/Immersion Gold, ENEPIG), tin (Sn), silver (Ag), or gold (Au). The method for manufacturing a package structure according to claim 1, wherein before the second cutting, a solder ball is formed on each of the electrical contact pads.