201115654 六、發明說明： 【發明所屬之技術領域】 本發明係有關一種封裝結構之製法，尤指一種能提高 整體產能與降低整體成本之封裝結構之製法。 【先前技術】 在現行覆晶式（flip chip )半導體封裝技術中，係於 半導體晶片的作用面上設有複數電極墊，並提供一頂面具 有複數電性接觸墊之封裝基板，且藉由焊料凸塊以對應電 性連接該些電極墊與電性接觸墊。 相較於傳統的打線接合（wire bond )技術，覆晶技術 之特徵在於半導體晶片與封裝基板間的電性連接係直接以 焊料凸塊為之而非一般之金線，而此種覆晶技術之優點在 於能提高封裝密度以降低封裝元件尺寸；同時，該種覆晶 技術不需使用長度較長之金線，而能降低阻抗，以提高電 性功能。 習知之覆晶式封裝結構之製法係先提供一核心板，再 於該核心板上形成增層結構，且該增層結構最外層具有複 數凸塊焊墊，於該增層結構上形成絕緣保護層，且該絕緣 保護層中形成複數開孔，以令各該凸塊焊墊對應外露於各 該開孔，並於該開孔中之凸塊焊墊上形成表面處理層，而 成為一整版面封裝基板（panel);接著，將該整版面封裝 基板切割成複數封裝基板單元（unit)或複數封裝基板條 (strip)，而各該封裝基板條具有複數封裝基板單元；最 後，再運送至封裝廠進行後續的置晶、封裝、及/或切單 3 111374 201115654 (singulation)等步驟。 惟，若將該整版面封裝基板切割成複數封裝基板單元 後，再進行置晶與封裝步驟，則一次僅有單一封裝基板單 元進行處理，因而產能較低且整體成本高；又若將該整版 面封裝基板切割成複數封裝基板條後，再進行置晶、封裝 與切單等步驟，則因為該封裝基板條所保留的邊框佔用不 少有效面積，因而形成整體成本的浪費。 另一方面，隨著封裝基板的整體厚度愈來愈薄，對於 封裝基板單元或封裝基板條進行置晶或封裝等加工步驟將 更加困難。 然而，若不先將整版面封裝基板切割成複數封裝基板 單元或複數封裝基板條，而直接以整版面封裝基板來進行 置晶、封裝、及切單等步驟，則必須購置較大之機台，因 而造成整體設備成本的上升；再者，整版面封裝基板的大 面積對位的精度較低，容易使得最終的封裝結構單元有較 大的誤差，進而影響整體良率。 因此，如何避免習知技術中之封裝結構之製法具有較 繁雜之步驟而導致產能低落及浪費過多基板的有效面積而 導致整體成本上升等問題，實已成為目前亟欲解決的課題。 【發明内容】 鑑於上述習知技術之種種缺失，本發明之主要目的係 提供一種能提高整體產能與降低整體成本之封裝結構之製 法。 為達上述及其他目的，本發明揭露一種封裝結構之製 4 111374 201115654 法，係包括：提供一承載單元，於其兩表面上均具有金屬 層；於各該金屬層上形成複數第一焊料凸塊；於各該金屬 層上形成第一介電層，且該第一介電層形成有外露各該第 一焊料凸塊上表面之開孔；於該第一介電層與第一焊料凸 塊上形成增層結構，該增層結構最外層具有複數電性連接 至各該第一焊料凸塊之電性接觸墊；於該增層結構最外層 上形成絕緣保護層，且該絕緣保護層中形成有複數絕緣保 護層開孔，以令各該電性接觸墊對應外露於各該絕緣保護 ®層開孔中，而成為上下成對的整版面封裝基板；裁切該上 下成對的整版面封裝基板，以成為複數上下成對的封裝基 板區塊，且各該上下成對的封裝基板區塊具有呈（mxn) 陣列排列的上下成對的封裝基板單元，其中，m與η皆為 大於1之整數；於各該電性接觸墊上形成焊球；將該金屬 層自該承載單元分離，以將該上下成對之封裝基板區塊分 離成獨立的兩個封裝基板區塊，各該封裝基板區塊具有呈 φ ( m X η )陣列排列的封裝基板單元；移除各該封裝基板區 塊上之金屬層，以露出該些第一焊料凸塊；於各該封裝基 板單元之該些第一焊料凸塊上接置半導體晶片，以成為具 有複數封裝結構單元的封裝結構區塊；於該第一介電層及 該些半導體晶片上形成封裝材，以及裁切該封裝結構區塊 以分離成複數封裝結構單元。 依上所述之封裝結構之製法，該承載單元之製程係可 包括：提供一具有相對兩表面之第一承載板；於該第一承 載板之兩表面上均形成面積小於該第一承載板之剝離層； 5 111374 201115654 於該第一承載板上且未形成該剝離層之表面形成黏著層， 以令該黏著層環繞該剝離層四周；以及於該剝離層與黏著 層上形成該金屬層。或者，該承載單元之製程係可包括： 提供一具有相對兩表面之第一承載板；於該第一承載板之 兩表面上均形成黏著層；於該黏著層上全面貼設有面積小 於該第一承載板且四周為該黏著層環繞之剝離層；以及於 該剝離層與黏著層上形成該金屬層。 於上述之封裝結構之製法中，復可包括於各該上下成 馨 對的封裝基板區塊之絕緣保護層上設置第二承載板，且該 第二承載板係罩設該些焊球，並於裁切該封裝結構區塊之 前，移除該第二承載板。 又於上述之封裝結構之製法中，該半導體晶片可具有 作用面，且該作用面上可具有複數電極墊，而各該電極墊 可藉由第二焊料凸塊以對應電性連接至各該第一焊料凸 塊。 依上所述之製法，該封裝材復可填入該些半導體晶片 鲁 與第一介電層之間，以包覆該些第二焊料凸塊。 又於上述之製法中，該增層結構係可包括電性連接至 該些第一焊料凸塊之第一線路層、形成於該第一介電層與 第一線路層上之至少一第二介電層、形成於該第二介電層 上之第二線路層、及複數形成於該第二介電層中並電性連 接該第二線路層與第一線路層之導電盲孔，且該增層結構 最外層之第二線路層復具有該些電性接觸墊。 前述之封裝結構之製法中，該些上下成對的封裝基板 6 111374 201115654 區塊之製程係可包括：沿該上下成對的整版面封裝基板的 邊緣與内部進行裁切，且裁切邊通過該剝離層，以成為該 些上下成對的封裝基板區塊。 依上所述之製法，復可包括於各該電性接觸墊上形成 表面處理層，且形成該表面處理層之材料可為鎳/金 (Ni/Au)、化鎳抱浸金（Electroless Nickel / Electroless Palladium / Immersion Gold，ENEPIG )、錫（Sn )、銀（Ag )、 或金（Au )。 ® 於上述之製法中，於裁切該上下成對的整版面封裝基 板之前，復可包括於該絕緣保護層與電性接觸墊上形成第 一保護膜，並於裁切後，移除該第一保護膜。 又依上述之封裝結構之製法，於裁切該封裝結構區塊 之前，復可包括於該些焊球與絕緣保護層上形成第二保護 膜，並於裁切後，移除該第二保護膜。 本發明復揭露另一種封裝結構之製法，係包括：提供 ^ 一承載單元，於其兩表面上具有金屬層；於各該金屬層上 形成複數第一焊料凸塊；於各該金屬層上形成第一介電 層，且該第一介電層形成有外露各該第一焊料凸塊上表面 之開孔；於該第一介電層與第一焊料凸塊上形成增層結 構，該增層結構最外層具有複數電性連接至各該第一焊料 凸塊之電性接觸墊；於該增層結構最外層上形成絕緣保護 層，且該絕緣保護層中形成有複數絕緣保護層開孔，以令 各該電性接觸墊對應外露於各該絕緣保護層開孔中，而成 為上下成對的整版面封裝基板；裁切該上下成對的整版面 7 111374 201115654 封裝基板，以成為複數上下成對的封裝基板區塊，且各該 上下成對的封裝基板&塊具有呈（m X η )陣列排列的上下 成對的封裝基板單元，其中，m與η皆為大於i之整數； 將該金屬層自該承載單元分離，以將該上下成對的封裝基 板區塊分離成獨立的兩個封裝基板區塊，各該封裝基板區 塊具有呈（mxn)陣列排列的封裝基板.單元；移除^該 裝基板區塊上之金屬層’且露出該㈣—焊料 該封農基板單元之該料―焊料凸塊 ^ ' 以成為具有複數封裝結構單元的封裝體晶片’ 介電層及該些半導體晶片上形成封裝於該第- 墊上形成焊球；以及裁切該封事檨；μ電性接觸 裝結構單元。 '裝遽塊以分離成複數封 兩表:：述承:Γ载單元之製程係可包括:提“有 面之弟一承载板；於該第一承 、有 形成面積小於該第一承载板 ，“表面上均 ^未形成該剝離層之表面形成黏著層 I載板上 該制離層四周；錢於關離層 二者層環繞 層。或者，該承载單元之製法係V包:者 黏著層;於該黏==:有_之兩〜^ 且四周為絲著層環.面積小於該卜承载板 層上形成該金屬層，以及於該剝離層與黏著 於上述之封裝結構之製法中，復可包括於各 、封裝基板區塊之絕緣保護層上設置第二承載板，成 Π1374 201115654 ^ I載板係罩設該些焊球，並於。 焊球之前，移除該第二承載板。$電性接觸塾上形成 又於上逑之封裝結構之製法中，诗 作用面，且該作用面上可具有複數=導體晶片可具有 可错由第二禅料凸塊以對應電性°墊’而各該電極塾 塊。 接至各該第一垾料凸 依上所迷之製法，該封裝材 ”第―介電層之間，以包覆該些第二煤：該些半導體晶片 又依上所迷之製法中，該增層&二凸塊。 至：該第-焊料凸塊之第一線路層：糸可包括電性連接 與第-線路層上之至少一第二介％㊉成於該弟-介電層 ^=_層、及複數形成電 連接該第二線^與第-線路層 電層中並電性 構最外層之第二線路層復具有該且該增層结 你於、+、 —苞性接觸墊。 ;1 a之封裝結構之製法中，誃此 板區塊之製法# π μ二上下成對的封裝基 的邊齡II包括：沿該上下成對的整版面封裝基板 、。卩進行裁切，且裁切邊通過該剝離層，以成為 該些上下成對的封裝基板區塊。 依上所述之封裝結構之製法，復可包括於各該電性接 觸墊上形成表面處理層，且形成該表面處理層之材料可為 錄/金（ISii/Au)、化鎳 J巴浸金（Electroless Nickel / Electroless Palladium / Immersion Gold，ENEPIG ) ' 錫（Sn)、銀（Ag )、 或金（Au )。 於上述之封裝結構之製法中，於裁切該上下成對的整 9 111374 201115654 版面封裝基板之前，復可包括於該絕緣保護層與電性接觸 墊上形成第一保護臈，並於裁切後，移除該第一保護膜。 又依上所述之製法，於裁切該封裝結構區塊之前，復 可包括於該些焊球與絕緣保護層上形成第二保護膜，並於 裁切後，移除該第二保護膜。 由上可知，本發明之封裝結構之製法係先將上下成對 的整版面封裝基板裁切成複數上下成對的封裝基板區塊， 各該上下成對的封裝基板區塊之面積適中且包括有複數上 下成對的封裝基板單元；接著，於各該封裝基板單元上接 置半導體晶片並以封裝材加以固定與保護，敢後裁切成 複數封裝結構單元。相較於習知技術，本發明之封裝結構 之製法係整合封裝基板製造及半導體晶片封裝，可一次對 各該封裝基板區塊中的全部封裝基板單元進行半導體晶片 封裝，以簡化製程並提高產能；再者，本發明之封裝基板 區塊之面積適中，所以，各該封裝基板區塊中的各該封裝 基板單元能具有較佳的精度，故，本發明之封裝結構之製 法具有產能較高且良率較高等優點。 【實施方式】 以下藉由特定的具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。 第一實施例 請參閱第1A至II圖，係為本發明封裝結構之製法之 第一實施例的剖視示意圖；其中，該第1A’圖係第1A圖的 10 111374 201115654 另一實施態樣，兮笛，^ ^ '^弟1D’圖係第1D圖的俯視圖。 • 如第1八及1A’圖所示，提供一承載單元2’於該承載201115654 VI. Description of the Invention: [Technical Field] The present invention relates to a method of manufacturing a package structure, and more particularly to a method for manufacturing a package structure capable of improving overall productivity and reducing overall cost. [Prior Art] In the current flip chip semiconductor packaging technology, a plurality of electrode pads are disposed on a working surface of a semiconductor wafer, and a package substrate having a plurality of electrical contact pads on the top surface is provided by The solder bumps are electrically connected to the electrode pads and the electrical contact pads. Compared with the conventional wire bond technology, the flip chip technology is characterized in that the electrical connection between the semiconductor wafer and the package substrate is directly solder bump instead of the general gold wire, and the flip chip technology The advantage is that the package density can be increased to reduce the size of the package component; at the same time, the flip chip technology does not need to use a long length of gold wire, but can reduce the impedance to improve the electrical function. The conventional method for fabricating a flip-chip package structure first provides a core plate, and then forms a build-up structure on the core plate, and the outermost layer of the build-up structure has a plurality of bump pads to form an insulation protection on the build-up structure. a plurality of openings are formed in the insulating protective layer, so that each of the bump pads is exposed to each of the openings, and a surface treatment layer is formed on the bump pads in the openings to form a full-faced surface a package substrate; then, the full-size package substrate is cut into a plurality of package substrate units or a plurality of package substrate strips, and each of the package substrate strips has a plurality of package substrate units; finally, transported to the package The factory performs subsequent steps of crystallization, encapsulation, and/or singulation 3 111374 201115654 (singulation). However, if the entire package substrate is diced into a plurality of package substrate units, and then the crystallization and packaging steps are performed, only a single package substrate unit is processed at a time, so that the productivity is low and the overall cost is high; After the layout of the package substrate is cut into a plurality of package substrate strips, the steps of crystallization, packaging, and singulation are performed, because the frame retained by the package substrate strip occupies a large effective area, thereby forming a waste of the overall cost. On the other hand, as the overall thickness of the package substrate becomes thinner, processing steps such as lithography or encapsulation of the package substrate unit or the package substrate strip are more difficult. However, if the entire package substrate is first cut into a plurality of package substrate units or a plurality of package substrate strips, and the substrate is directly packaged by the full-face substrate for the steps of crystallizing, packaging, and singulation, a larger machine must be purchased. Therefore, the overall equipment cost is increased; in addition, the precision of the large-area alignment of the full-page package substrate is low, which tends to cause a large error in the final package structure unit, thereby affecting the overall yield. Therefore, how to avoid the problem that the manufacturing method of the package structure in the prior art has complicated steps and causes the productivity to be low and the effective area of the substrate to be wasted, resulting in an increase in the overall cost has become a problem that is currently being solved. SUMMARY OF THE INVENTION In view of the above-described deficiencies of the prior art, it is a primary object of the present invention to provide a package structure that increases overall throughput and reduces overall cost. To achieve the above and other objects, the present invention discloses a method for manufacturing a package structure 4 111374 201115654, comprising: providing a carrier unit having a metal layer on both surfaces thereof; forming a plurality of first solder bumps on each of the metal layers a first dielectric layer is formed on each of the metal layers, and the first dielectric layer is formed with an opening exposing an upper surface of each of the first solder bumps; and the first dielectric layer and the first solder bump Forming a build-up structure on the block, the outermost layer of the build-up structure having a plurality of electrical contact pads electrically connected to each of the first solder bumps; forming an insulating protective layer on the outermost layer of the build-up structure, and the insulating protective layer Forming a plurality of insulating protective layer openings, so that the electrical contact pads are correspondingly exposed in the openings of the insulating protection layers, and become a pair of upper and lower surface-printed package substrates; cutting the upper and lower pairs The layout package substrate is a plurality of package substrate blocks that are paired up and down, and each of the upper and lower pairs of package substrate blocks has upper and lower pairs of package substrate units arranged in an (mxn) array, wherein m and n are both Big An integer of 1; forming a solder ball on each of the electrical contact pads; separating the metal layer from the carrying unit to separate the upper and lower pairs of package substrate blocks into two independent package substrate blocks, each of the packages The substrate block has a package substrate unit arranged in an array of φ ( m X η ); removing a metal layer on each of the package substrate blocks to expose the first solder bumps; and each of the package substrate units A semiconductor wafer is attached to the first solder bump to form a package structure block having a plurality of package structure units; a package material is formed on the first dielectric layer and the semiconductor wafers, and the package structure block is cut Separated into a plurality of package structure units. According to the method for manufacturing the package structure, the process of the carrying unit may include: providing a first carrier having two opposite surfaces; and forming an area smaller than the first carrier on both surfaces of the first carrier a peeling layer; 5 111374 201115654 forming an adhesive layer on the surface of the first carrier plate and not forming the peeling layer, so that the adhesive layer surrounds the peeling layer; and forming the metal layer on the peeling layer and the adhesive layer . Or the process of the carrying unit may include: providing a first carrier having two opposite surfaces; forming an adhesive layer on both surfaces of the first carrier; The first carrier plate is surrounded by a release layer surrounded by the adhesive layer; and the metal layer is formed on the release layer and the adhesive layer. In the above method for fabricating a package structure, the second carrier plate is disposed on the insulating protection layer of each of the upper and lower singulated package substrate blocks, and the second carrier plate covers the solder balls, and The second carrier board is removed prior to cutting the package structure block. In the above method for fabricating a package structure, the semiconductor wafer may have an active surface, and the active surface may have a plurality of electrode pads, and each of the electrode pads may be electrically connected to each of the second solder bumps. First solder bump. According to the above method, the package material is filled between the semiconductor wafer and the first dielectric layer to cover the second solder bumps. In the above method, the build-up structure may include a first circuit layer electrically connected to the first solder bumps, and at least a second formed on the first dielectric layer and the first circuit layer. a dielectric layer, a second circuit layer formed on the second dielectric layer, and a plurality of conductive blind holes formed in the second dielectric layer and electrically connected to the second circuit layer and the first circuit layer, and The second circuit layer of the outermost layer of the buildup structure has the electrical contact pads. In the above method of manufacturing the package structure, the process of the upper and lower pairs of package substrates 6 111374 201115654 may include: cutting the edges and the inside of the pair of upper and lower package substrates, and cutting the edges The peeling layer is used to form the upper and lower pairs of package substrate blocks. According to the above-mentioned manufacturing method, a surface treatment layer is formed on each of the electrical contact pads, and the material forming the surface treatment layer may be nickel/gold (Ni/Au) or nickel immersion gold (Electroless Nickel / Electroless Palladium / Immersion Gold, ENEPIG ), tin (Sn), silver (Ag), or gold (Au). In the above method, before the upper and lower pairs of the full-face package substrate are cut, the first protective film is formed on the insulating protective layer and the electrical contact pad, and after cutting, the first protective film is removed. A protective film. According to the manufacturing method of the package structure, before the cutting of the package structure block, the second protective film is formed on the solder balls and the insulating protective layer, and after the cutting, the second protection is removed. membrane. The present invention discloses a method for fabricating another package structure, comprising: providing a carrier unit having a metal layer on both surfaces thereof; forming a plurality of first solder bumps on each of the metal layers; forming on each of the metal layers a first dielectric layer, and the first dielectric layer is formed with an opening exposing an upper surface of each of the first solder bumps; forming a build-up structure on the first dielectric layer and the first solder bump The outermost layer of the layer structure has a plurality of electrical contact pads electrically connected to the first solder bumps; an insulating protective layer is formed on the outermost layer of the layered structure, and a plurality of insulating protective layer openings are formed in the insulating protective layer So that each of the electrical contact pads is exposed to each of the insulating protective layer openings to form a full-faced package substrate; the upper and lower pairs of full-faced faces 7 111374 201115654 package substrates are cut into plural a pair of upper and lower package substrate blocks, and each of the upper and lower pairs of package substrates & blocks have upper and lower pairs of package substrate units arranged in an array of (m X η ), wherein m and n are both integers greater than i Will The genus layer is separated from the carrying unit to separate the upper and lower pairs of package substrate blocks into two independent package substrate blocks, each of the package substrate blocks having a package substrate arranged in an (mxn) array. Dividing the metal layer on the substrate substrate and exposing the (four)-solder material of the agricultural substrate unit-solder bumps to form a dielectric wafer layer having a plurality of package structure units and the dielectric layers Forming a solder ball on the semiconductor wafer to form a solder ball; and cutting the sealing material; and electrically contacting the structural unit. 'Installation block to separate into two sets of two tables:: Describe: the process unit of the load carrying unit may include: a "faceted brother-loaded board; in the first bearing, the formed area is smaller than the first carrying board "On the surface, the surface of the release layer is not formed to form the adhesion layer I on the carrier layer around the separation layer; the Qian Yuguan layer is surrounded by layers. Alternatively, the method of manufacturing the carrier unit is V-package: the adhesive layer; in the adhesive ==: there are _ two to ^ and the periphery is a wire-layered ring. The area is smaller than the metal layer formed on the layer of the carrier layer, and The stripping layer and the method of bonding the above-mentioned package structure may further comprise a second carrier plate disposed on each of the insulating protective layers of the package substrate block, and the solder balls are covered by the carrier plate 1374 201115654 ^I. And. The second carrier plate is removed prior to soldering the ball. In the method of manufacturing the package structure formed on the electrical contact ,, the poetry action surface, and the action surface may have a complex number = the conductor wafer may have a second embossing bump to correspond to the electrical pad 'And each of the electrodes is a block. Connected to each of the first coatings according to the method of manufacturing, the package is between the first dielectric layers to cover the second coals: the semiconductor wafers are in accordance with the method of fabrication, The first layer of the first solder bump: the first circuit layer of the first solder bump: the germanium may include an electrical connection and at least one second dielectric layer on the first circuit layer The layer ^=_ layer, and the plurality of layers form a second line layer electrically connected to the second line and the first layer of the first layer and the second layer of the electrical layer, and the layer is formed by the +, - In the manufacturing method of the package structure of the 1 a, the method of manufacturing the plate block # π μ two pairs of the package base age II includes: a full-face package substrate along the upper and lower sides, 卩Cutting, and the cutting edge passes through the peeling layer to form the upper and lower pairs of package substrate blocks. According to the manufacturing method of the package structure, the surface layer is formed on each of the electrical contact pads. And the material forming the surface treatment layer may be recorded/gold (ISii/Au), nickel immersion gold (Electroless Nickel / Electroles) s Palladium / Immersion Gold, ENEPIG ) 'Sn (Sn), Silver (Ag), or Gold (Au). In the above-mentioned package structure method, before cutting the upper and lower pairs of the entire 9 111374 201115654 layout substrate The method further includes forming a first protective barrier on the insulating protective layer and the electrical contact pad, and removing the first protective film after cutting. Further cutting the package structure block according to the manufacturing method described above The second protective film is formed on the solder balls and the insulating protective layer, and the second protective film is removed after cutting. As can be seen from the above, the manufacturing method of the package structure of the present invention is first and foremost The pair of full-page package substrates are cut into a plurality of upper and lower pairs of package substrate blocks, and each of the upper and lower pairs of package substrate blocks has a moderate area and includes a plurality of upper and lower pairs of package substrate units; The semiconductor substrate is mounted on the package substrate unit and fixed and protected by the package material, and then cut into a plurality of package structure units. Compared with the prior art, the package structure of the present invention is integrated with the package substrate and The conductor chip package can perform semiconductor chip packaging on all the package substrate units in each package substrate block at a time to simplify the process and increase the productivity; further, the package substrate block of the present invention has a moderate area, so each package is Each of the package substrate units in the substrate block can have better precision. Therefore, the method for manufacturing the package structure of the present invention has the advantages of high productivity and high yield, etc. [Embodiment] Hereinafter, a specific embodiment will be described. Other embodiments of the present invention can be easily understood by those skilled in the art from the disclosure of the present specification. For the first embodiment, please refer to FIGS. 1A to II, which are the manufacturing method of the package structure of the present invention. A cross-sectional view of the first embodiment; wherein, the first 1A' is a top view of the first embodiment of FIG. 1A, FIG. 1A. • As shown in Figures 18 and 1A', a carrier unit 2' is provided on the carrier
- 單元2之兩表面上均I#A 、、 」具有金屬層22。 β上述之承載單元2之製程可如第1A圖所示，係提供 _ I載板2Ga ’於其兩表面上均形成面積小於該第一 承載板20a之剝離層. - 、 11 ’接著，於該第一承載板20a上 且未形成該剝離層2 ] 1 + ± 之表面形成黏著層212，以令該黏 著層212環繞該剝離層 龜 ^ 曰211四周；之後，再於該剝離層211 擊與黏著層212上形成金屬層。 或者外i之承载單元2之製程可如第1A,圖所示’ 係提供一第一承載板2〇 拉—々 ，於兩表面上均形成黏著層 212，接者’於各該龜签思 ^ j〇 ' θ 2上全面貼設有面積小於該第 一承載板20a且四周* ▲ » 911 為者層212環繞之剝離層211 , 於5亥剝邊層211與零占里思。μ，， 钿灕Μ 911 θ ~12上形成金屬層22。此外，該 剝难層211可為雄细聘· 息?? τ 、，形成該金屬層22之材料可為銅， 籲且.玄金屬層22可作為電 (seed layer) 〇 避衣私中电流傳導路#之晶種層 如第1B圖所示，於 料凸塊23。 、 μ金屬層22上形成複數第一焊 如第1C圖所糸，於 2Wa，且該第一介電層屬層22上形成第一介電層 23之上表面的開孔24仞也成有外露各該第一焊料凸塊 第-焊料凸塊23上形成增層妾=^該第一介電層24】a與 括電性連接至該些第一 ’该增層結構24係包 卜料凸掩23之第-線篇、 111374 11 201115654 形成於該第一介電層241a與第一線路層242a上之至少一 第二介電層241b、形成於該第二介電層2仙上之第二線 路層242b、及複數形成於該第二介電層241b中並電性連 接該第二線路層242b與第一線路層242a之導電盲孔 243,且該增層結構24最外層之第二線路層2421?復具有複 數電性接觸墊244;然後，於該增層結構24最外層上形成 絶緣保護層25，且該絕緣保護層25中形成有複數絕緣保 A層開孔250 ’以令各該電性接觸墊244對應露出於各該 絕緣保諼層開孔250’而成為上下成對的整版面封裝基板 2a。此外’復可包括於各該電性接觸墊244上形成表面處 理層（未以圖式表示），且形成該表面處理層之材料可為 鎳/至（Ni/Au )、化鎳纪浸金（Eiectr〇iess Nickel / Electroless- I#A, "" has a metal layer 22 on both surfaces of unit 2. The process of the above-mentioned carrier unit 2 can be as shown in FIG. 1A, and the _I carrier plate 2Ga' is provided on both surfaces thereof to form a peeling layer smaller than the first carrier plate 20a. - , 11 ' Next, An adhesive layer 212 is formed on the surface of the first carrier 20a and the surface of the peeling layer 2 is not formed, so that the adhesive layer 212 surrounds the peeling layer of the turtle layer 211; and then the peeling layer 211 is hit. A metal layer is formed on the adhesive layer 212. Or the process of the carrying unit 2 of the outer i can be as shown in FIG. 1A, and the first carrier plate 2 is pulled and pulled, and the adhesive layer 212 is formed on both surfaces, and the picker is in each of the turtles. ^ j〇' θ 2 is fully attached with a peeling layer 211 which is smaller than the first carrier 20a and surrounded by * ▲ » 911 for the layer 212, and the stripping layer 211 and zero Zhanris. The metal layer 22 is formed on 911, θ ~12. In addition, the stripping layer 211 may be a male and female material, and the material forming the metal layer 22 may be copper, and the metal layer 22 may serve as a seed layer. The seed layer of the conductive path # is as shown in FIG. 1B, and is formed on the bump 23. Forming a plurality of first solders on the μ metal layer 22, as shown in FIG. 1C, at 2Wa, and forming an opening 24 on the upper surface of the first dielectric layer 23 on the first dielectric layer 22 Exposing each of the first solder bumps to the solder bumps 23 to form a build-up layer, and the first dielectric layer 24a is electrically connected to the first ones of the build-up structures 24 The first dielectric layer 241b formed on the first dielectric layer 241a and the first wiring layer 242a is formed on the second dielectric layer 2, and the first dielectric layer 241a is formed on the first dielectric layer 241a. a second circuit layer 242b, and a plurality of conductive vias 243 formed in the second dielectric layer 241b and electrically connected to the second circuit layer 242b and the first circuit layer 242a, and the outermost layer of the build-up structure 24 The second circuit layer 2421 has a plurality of electrical contact pads 244; then, an insulating protective layer 25 is formed on the outermost layer of the build-up structure 24, and a plurality of insulating A-layer openings 250' are formed in the insulating protective layer 25. Each of the electrical contact pads 244 is exposed to each of the insulating layer openings 250' to form a pair of upper surface package substrates 2a. In addition, a composite surface may be formed on each of the electrical contact pads 244 to form a surface treatment layer (not shown), and the material forming the surface treatment layer may be nickel/to (Ni/Au), nickel immersion gold (Eiectr〇iess Nickel / Electroless
Palladium / lmmersi〇n G〇ld，ENEpiG )、錫（％ )、銀（Ag )、 或金（Au )。 如第ID及ID’圖所示，該第id，圖係第id圖的俯視 圖’如圖所不’沿該上下成對的整版面封裝基板2a的邊緣 ，内。p進仃裁切’且裁切邊26通過該剝離層，以成為 複數上下成對_裝基板區塊2b，且各該上下成對的封裝 基板區塊2b θ ^ 〇 ( 、 ”肩王C m X η )陣列排列的上下成對的封裝 基板單元2c，甘i ^ ,、〒’ m與n皆為大於1之整數，於本實施 例中，m與 八 法 一一 刀別為6與5 ’但不以此為限。此外，於裁 # = β I成搿的整版面封裝基板2a之前，復可包括於該絕 緣保護層. ,.λ 一黾性接觸墊244上形成第一保護膜（未以圖 〉ί; y 5 j'» 'Pi. 避免該絕緣保護層25與電性接觸墊244 (或 12 111374 201115654 其上的表面處理層）於裁切時被液體或粉塵所影響，並於 裁切後，移除該第一保護膜。 如第1E圖所示，於各該電性接觸墊244上形成焊球 27，並於各該上下成對的封裝基板區塊2b之絕緣保護層 25上設置第二承載板20b，且該第二承載板20b係罩設該 些焊球27,俾於後續製程中保護該些焊球27,並提供足夠 支撑強度。 如第1F圖所示，將該金屬層22自該承載單元2分離， 以將該上下成對的封裝基板區塊2b分離成獨立的兩個封 裝基板區塊2b’，而各該封裝基板區塊2b’具有呈（m X η) 陣列排列的封裝基板單元2c’。 如第1G圖所示，移除各該封裝基板區塊2b’上之金屬 層22,以露出該些第一焊料凸塊23,並於各該封裝基板單 元2c’之該些第一焊料凸塊23上接置半導體晶片28,以成 為具有複數封裝結構單元2c”之封裝結構區塊2b”；其中， 春該半導體晶片28具有作用面28a，且該作用面28a上具有 複數電極墊281，而各該電極墊281藉由第二焊料凸塊29 以對應電性連接至各該第一焊料凸塊23，並藉由迴焊 (reflow)製程以達成電性連接；接著，於該第一介電層 241a及該些半導體晶片28上形成封裝材30，且該封裝材 30並填入該些半導體晶片28與第一介電層241a之間，以 包覆該些第二焊料凸塊29。 如第1H圖所示，移除該第二承載板20b，而露出該 些焊球2 7。 13 111374 201115654 如第II圖所示，裁切該封裝結構區塊2b”以分離成複 數封裝結構單元2c”。此外，於裁切該封裝結構區塊2b” 之前，復可包括於該些焊球27與絕緣保護層25上形成第 二保護膜（未以圖式表示），以避免該些焊球27與絕緣保 護層25於裁切時被液體或粉塵所影響，並於裁切後，移除 該第二保護膜。 第二實施例 請參閱第2A.至2F圖，係為本發明之封裝結構之製法 之第二實施例的剖視示意圖。 如第2A圖所示，提供一係如第1A至1D圖所述之上 下成對的封裝基板區塊2b，且各該上下成對的封裝基板區 塊2b具有呈（m X η )陣列排列的上下成對的封裝基板單 元2c;其中，m與η皆為大於1之整數。 如第2Β圖所示，於各該上下成對的封裝基板區塊2b 之絕緣保護層25上設置第二承載板20b。 如第2C圖所示，將該金屬層22自該承載單元2分 離，以將該上下成對的封裝基板區塊2b分離成獨立的兩個 封裝基板區塊2b’，而各該封裝基板區塊2b’具有呈（mx η) 陣列排列的封裝基板單元2c’。 如第2D圖所示，移除各該封裝基板區塊2b’上之金屬 層22,以露出該些第一焊料凸塊23，並於各該封裝基板單 元2c’之該些第一焊料凸塊23上接置半導體晶片28,以成 為具有複數封裝結構單元2c”的封裝結構區塊2b”，而該半 導體晶片28具有作用面28a，且該作用面28a上具有複數 14 111374 201115654 電極墊281，而各該電極墊281藉由第二焊料凸塊29以對 應電性連接至各該第一焊料凸塊23，並藉由廻焊（reflow) 製程以達成電性連接；接著，於該第一介電層241a及該些 半導體晶片28上形成封裝材30,且該封裝材30並填入該 些半導體晶片28與第一介電層241a之間，以包覆該些第 二焊料凸塊29。 如第2E圖所示，移除該第二承載板20b，並於各該 電性接觸墊244上形成焊球27。 ® 如第2F圖所示，裁切該封裝結構區塊2b”以分離成複 數封裝結構單元2c”。此外，於裁切該封裝結構區塊2b” 之前，復可包括於該些焊球27與絕緣保護層25上形成第 二保護膜（未以圖式表示），以避免該些焊球27與絕緣保 護層25於裁切時被液體或粉塵所影響，並於裁切後，移除 該第二保護膜。 本發明之製法中，亦可先將上下成對的整版面封裝基 鲁板分離成獨立的兩個整版面封裝基板，再將該整版面封裝 基板裁切成複數封裝基板區塊，而其他步驟同前面所述， 在此不加以贅述。 綜上所述，本發明之封裝結構之製法係先將上下成對 的整版面封裝基板裁切成複數上下成對的封裝基板區塊， 而各該上下成對的封裝基板區塊之面積適中且包括有複數 上下成對的封裝基板單元；接著，於各該封裝基板單元上 接置半導體晶片並以封裝材加以固定與保護；最後，裁切 成複數封裝結構單元。相較於習知技術，本發明之封裝結 15 111374 201115654 構之製法係整合封裝基板製造及半導體晶片封裝，可一次 對各該封裝基板區塊中的全部封裝基板單元進行半導體晶 片封裝，以簡化製程並提高產能；再者，本發明之封裝基 板區塊之面積適中，所以，各該封裝基板區塊中的各該封 裝基板單元能具有較佳的精度，故，本發明之封裝結構之 製法具有產能較高且良率較高等優點。 上述實施例係用以例示性說明本發明之原理及其功 效，而非用於限制本發明。任何熟習此項技藝之人士均可 在不違背本發明之精神及範疇下，對上述實施例進行修 改。因此本發明之權利保護範圍，應依後述之申請專利範 圍所列之技術思想及創新特徵。 【圖式簡單説明】 第1A至II圖係為本發明封裝結構之製法之第一實施 例的剖視示意圖，其中，該第1A’圖係第1A圖的另一實施 態樣，該第1D’圖係第1D圖的俯視圖；以及 第2A至2F圖係為本發明封裝結構之製法之第二實施 例的剖視示意圖。 【主要元件符號說明】 2 承載單元 20a 第一承載板 20b 第二承載板 211 剝離層 212 黏著層 22 金屬層 23 第一焊料凸塊 241a 第一介電層 2410 開孔 24 增層結構 242a 第一線路層 241b 第二介電層 16 111374 201115654 242b 第二線路層 243 導電盲孔 244 電性接觸墊 25 絕緣保護層 250 絕緣保護層開孔 26 裁切邊 27 焊球 28 半導體晶片 28a 作用面 281 電極塾 29 第二焊料凸塊 30 封裝材 2a 上下成對的整版面封裝基板 2b 上下成對的封裝基板區塊Palladium / lmmersi〇n G〇ld, ENEpiG), tin (%), silver (Ag), or gold (Au). As shown in the ID and ID' diagrams, the id of the figure id, the plan view of the id diagram is not shown along the edge of the pair of upper and lower encapsulation substrates 2a. The p-cutting is performed and the cutting edge 26 passes through the peeling layer to form a plurality of upper and lower pairs of the substrate substrate 2b, and each of the upper and lower paired package substrate blocks 2b θ ^ 〇 ( , " shoulder king C m X η ) array of upper and lower pairs of package substrate units 2c, gan i ^ , 〒 ' m and n are integers greater than 1, in this embodiment, m and eight methods one by one knife 6 5 'but not limited to this. In addition, before the full-face encapsulation substrate 2a of the # = = = = , , , , , = = = λ λ λ λ λ λ λ λ λ λ λ λ λ λ λ λ λ λ λ Film (not shown) y 5 j'» 'Pi. Avoid the insulating protective layer 25 and the electrical contact pad 244 (or the surface treatment layer on 12 111374 201115654) being affected by liquid or dust during cutting After the cutting, the first protective film is removed. As shown in FIG. 1E, solder balls 27 are formed on each of the electrical contact pads 244, and the package substrate blocks 2b are respectively paired with the upper and lower pairs. The second carrier plate 20b is disposed on the insulating protection layer 25, and the solder balls 27 are covered by the second carrier plate 20b to protect the solder balls 27 in a subsequent process, and Providing sufficient supporting strength. As shown in FIG. 1F, the metal layer 22 is separated from the carrying unit 2 to separate the upper and lower paired package substrate blocks 2b into two independent package substrate blocks 2b'. Each of the package substrate blocks 2b' has a package substrate unit 2c' arranged in an array of (m x η). As shown in FIG. 1G, the metal layer 22 on each of the package substrate blocks 2b' is removed to expose the The first solder bumps 23 are attached to the first solder bumps 23 of each of the package substrate units 2c' to form a package structure block 2b" having a plurality of package structure units 2c"; The semiconductor wafer 28 has an active surface 28a, and the active surface 28a has a plurality of electrode pads 281, and each of the electrode pads 281 is electrically connected to each of the first solder bumps by a second solder bump 29. And forming a package 30 on the first dielectric layer 241a and the semiconductor wafers 28, and filling the package 30 with the package material 30, and forming the package 30 by the reflow process. Between the semiconductor wafer 28 and the first dielectric layer 241a to cover the first Solder bumps 29. As shown in Fig. 1H, the second carrier 20b is removed to expose the solder balls 27. 7 111374 201115654 As shown in Fig. II, the package structure block 2b is cut to Separating into a plurality of package structure units 2c". Further, before the package structure block 2b" is cut, a second protective film (not shown) is formed on the solder balls 27 and the insulating protective layer 25. In order to prevent the solder balls 27 and the insulating protective layer 25 from being affected by liquid or dust during cutting, and removing the second protective film after cutting. SECOND EMBODIMENT Please refer to Figures 2A. to 2F for a cross-sectional view showing a second embodiment of the method of fabricating the package structure of the present invention. As shown in FIG. 2A, a package substrate block 2b is provided in an upper pair as described in FIGS. 1A to 1D, and each of the upper and lower paired package substrate blocks 2b has an array of (m X η ) arrays. The upper and lower pairs of package substrate units 2c; wherein m and n are both integers greater than one. As shown in Fig. 2, a second carrier 20b is provided on the insulating protective layer 25 of each of the pair of upper and lower package substrate blocks 2b. As shown in FIG. 2C, the metal layer 22 is separated from the carrying unit 2 to separate the upper and lower pairs of package substrate blocks 2b into two independent package substrate blocks 2b', and each of the package substrate regions The block 2b' has a package substrate unit 2c' arranged in an array of (mx η). As shown in FIG. 2D, the metal layer 22 on each of the package substrate blocks 2b' is removed to expose the first solder bumps 23, and the first solder bumps of the package substrate units 2c' are formed. The semiconductor wafer 28 is attached to the block 23 to form a package structure block 2b" having a plurality of package structure units 2c", and the semiconductor wafer 28 has an active surface 28a, and the active surface 28a has a plurality of 14 111374 201115654 electrode pads 281 And each of the electrode pads 281 is electrically connected to each of the first solder bumps 23 by the second solder bumps 29, and is electrically connected by a reflow process; A package material 30 is formed on a dielectric layer 241a and the semiconductor wafers 28, and the package material 30 is filled between the semiconductor wafers 28 and the first dielectric layer 241a to cover the second solder bumps. 29. As shown in Fig. 2E, the second carrier 20b is removed, and solder balls 27 are formed on each of the electrical contact pads 244. ® As shown in Fig. 2F, the package structure block 2b" is cut to be separated into a plurality of package structure units 2c". In addition, before the package structure block 2b" is cut, a second protective film (not shown) is formed on the solder balls 27 and the insulating protective layer 25 to avoid the solder balls 27 and The insulating protective layer 25 is affected by liquid or dust during cutting, and the second protective film is removed after cutting. In the manufacturing method of the present invention, the upper and lower pairs of the full-face encapsulating base plates may be separated first. The two full-page package substrates are separated into two, and the whole package substrate is cut into a plurality of package substrate blocks, and the other steps are the same as those described above, and are not described herein. In summary, the package structure of the present invention is described. The method of the first method is to cut the upper and lower pairs of the whole surface package substrate into a plurality of upper and lower pairs of package substrate blocks, and each of the upper and lower pairs of package substrate blocks has a moderate area and includes a plurality of upper and lower pairs of package substrates. Then, the semiconductor wafer is attached to each of the package substrate units and fixed and protected by the package material; finally, the plurality of package structure units are cut. Compared with the prior art, the package of the present invention 15 111374 20 1115654 The manufacturing method is integrated with the package substrate manufacturing and the semiconductor chip package, and the semiconductor chip package can be performed on all the package substrate units in the package substrate block at a time to simplify the process and increase the productivity; further, the package substrate area of the present invention The size of the block is moderate, so that each of the package substrate units in each of the package substrate blocks can have better precision. Therefore, the method for manufacturing the package structure of the present invention has the advantages of high productivity and high yield. The present invention is exemplified to exemplify the principles of the present invention and its effects, and is not intended to limit the present invention. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be based on the technical idea and innovative features listed in the scope of the patent application described below. [Simplified Description of the Drawings] Figs. 1A to II are cross-sectional views showing the first embodiment of the manufacturing method of the package structure of the present invention. FIG. 1A is a plan view showing a first embodiment of FIG. 1A, and FIG. 1D' is a plan view of FIG. 1D; and 2A; 2F is a schematic cross-sectional view of a second embodiment of the method for fabricating the package structure of the present invention. [Main element symbol description] 2 Carrying unit 20a First carrier plate 20b Second carrier plate 211 Release layer 212 Adhesive layer 22 Metal layer 23 First solder bump 241a first dielectric layer 2410 opening 24 buildup structure 242a first circuit layer 241b second dielectric layer 16 111374 201115654 242b second circuit layer 243 conductive blind via 244 electrical contact pad 25 insulating protective layer 250 Insulating protective layer opening 26 Cutting edge 27 Solder ball 28 Semiconductor wafer 28a Acting surface 281 Electrode 塾 29 Second solder bump 30 Package 2a Upper and lower paired full-face package substrate 2b Upper and lower paired package substrate block
2c 上下成對的封裝基板單元 m 上下成對的封裝基板區塊之陣列行數 η 上下成對的封裝基板區塊之陣列列數 2b’ 封裝基板區塊 2c’ 封裝基板單元 2b” 封裝結構區塊 2c” 封裝結構單元 17 1113742c Upper and lower paired package substrate unit m Number of array rows of upper and lower package substrate blocks η Number of arrays of package substrate blocks up and down 2b' Package substrate block 2c' Package substrate unit 2b" Package structure area Block 2c" package structure unit 17 111374