CN102339761B - Method for manufacturing packaged structures - Google Patents
Method for manufacturing packaged structures Download PDFInfo
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- CN102339761B CN102339761B CN201010228354.3A CN201010228354A CN102339761B CN 102339761 B CN102339761 B CN 102339761B CN 201010228354 A CN201010228354 A CN 201010228354A CN 102339761 B CN102339761 B CN 102339761B
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- layer
- base plate
- packaging
- insulating protective
- loading plate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention relates to a method for manufacturing packaged structures. The method comprises the following steps of: firstly, cutting a large-area whole-layout package substrate into a plurality of package substrate blocks, wherein each package substrate block comprises a plurality of package substrate units; next, arranging a semiconductor chip on each package substrate unit and fixing and protecting by using a packaging material so as to form a plurality of packaged structure blocks, wherein each packaged structure block comprises a plurality of packaged structure units; and finally cutting the packaged structure blocks into a plurality of packaged structure units. According to the invention, the area of the package substrate blocks is moderate, thus the alignment error for each package substrate unit in each package substrate block in a manufacture process is reduced; and the whole package substrate units in each package substrate block can be subjected to semiconductor chip package once, the manufacture of package substrates and the package of semiconductor chips are integrated, and the process for manufacture is simplified, so that the overall productivity and the percent of pass are enhanced and the overall cost is lowered.
Description
Technical field
The present invention relates to a kind of manufacture method of encapsulating structure, particularly a kind of manufacture method that can improve overall throughput and reduce the encapsulating structure of holistic cost.
Background technology
In existing routing engagement type (Wire Bond) semiconductor packaging, the non-acting surface of semiconductor chip is connect and put on a base plate for packaging, and the acting surface of this semiconductor chip is provided with multiple electronic padses, and this base plate for packaging connects to be put the surface of this semiconductor chip and has multiple wire pads, and by corresponding respectively this electronic pads and the wire pad of being electrically connected of bonding wire, make this semiconductor chip be electrically connected this base plate for packaging.
Existing base plate for packaging is by a core board and be symmetrically formed at the circuit layer reinforced structure of its both sides and formed, but because using core board will cause conductor length and overall structure thickness to increase, and be difficult to meet the demand that electronic product function constantly promotes and volume constantly dwindles, so develop the base plate for packaging of coreless layer (coreless) structure, to meet the trend requirement of shortening conductor length and reduction overall structure thickness and adapting to high frequency, microminiaturization.
In addition, the manufacture method of existing routing engagement type encapsulating structure is first to provide one to complete leading portion manufacturing process and had the justifying face substrate body of multilayer line syndeton, at its outermost layer circuit, there is multiple wire pads and insulating protective layer, and in this insulating protective layer, form multiple perforates, make respectively this wire pad correspondence of this layer reinforced structure expose to respectively this perforate, and respectively on this wire pad exposing, forming surface-treated layer, and form a justifying face base plate for packaging (panel); Then, this justifying face base plate for packaging is cut into multiple base plate for packaging unit (unit) or multiple base plate for packaging bar (strip), wherein respectively this base plate for packaging bar comprises multiple base plate for packaging unit; Finally, then be transported to that encapsulation factory carries out follow-up putting that crystalline substance, routing engage, encapsulation and/or cut the steps such as list (singulation).
But, if this justifying face base plate for packaging is cut into behind multiple base plate for packaging unit, then put crystalline substance, routing joint and encapsulation step, because once only can deal with for single package base board unit, thereby production capacity reduction, and increase holistic cost; Or, if this justifying face base plate for packaging is cut into after multiple base plate for packaging bars, then put crystalline substance, routing and engage, encapsulate and cut single stage, because the frame that this base plate for packaging bar retains takies many effective areas, thereby form the waste of material cost.
On the other hand, along with the integral thickness of base plate for packaging is more and more thin, it will be more difficult for base plate for packaging unit or base plate for packaging bar, putting the procedure of processings such as crystalline substance or encapsulation.
But, if first justifying face base plate for packaging is not cut into multiple base plate for packaging unit or multiple base plate for packaging bar, and directly with justifying face base plate for packaging, put crystalline substance, routing joint, encapsulation and cut the steps such as single, must purchase larger board, thereby cause the rising of integral device cost; Moreover the precision of the large area contraposition of justifying face base plate for packaging is lower, easily makes final encapsulating structure unit have larger fabrication error, and then affect overall acceptability rate.
Therefore, manufacture method how to avoid encapsulating structure of the prior art has the step of more complicated and causes production capacity low and waste the effective area of too much substrate and cause the problems such as holistic cost rising, has become the problem of desiring most ardently at present solution.
Summary of the invention
In view of the many disadvantages of above-mentioned prior art, main purpose of the present invention is to provide a kind of manufacture method that can improve overall throughput and reduce the encapsulating structure of holistic cost.
For achieving the above object, the present invention discloses a kind of manufacture method of encapsulating structure, comprise: a paired justifying face base plate for packaging is up and down provided, on its two relative outermost surfaces, all form multiple wire pads and insulating protective layer, and in this insulating protective layer, form multiple perforates, so that described wire pad correspondence is exposed to respectively this perforate; Separate this paired justifying face base plate for packaging up and down, and cut this justifying face base plate for packaging, to form multiple base plate for packaging blocks, and respectively this base plate for packaging block has relative first surface and second surface, at this first surface, there is described wire pad and insulating protective layer, and this second surface has multiple electric contact mats and dielectric layer, and described electric contact mat is embedded and exposes to this dielectric layer surface, and respectively this base plate for packaging block has and is (the base plate for packaging unit that m × n) matrix is arranged, wherein, m and n are the integer that is greater than 1; The second loading plate is set on described electric contact mat and dielectric layer; On the insulating protective layer of each this base plate for packaging unit, connect and put semiconductor chip, to form the encapsulating structure block with multiple encapsulating structures unit, and this semiconductor chip has relative acting surface and non-acting surface, on this acting surface, there are multiple electronic padses, and this non-acting surface is fixedly arranged on this insulating protective layer, and respectively this electronic pads is electrically connected to respectively this wire pad by bonding wire with correspondence; On this insulating protective layer, described bonding wire and described semiconductor chip, form encapsulation material; Remove this second loading plate; And cut this encapsulating structure block to be separated into multiple encapsulating structures unit.
According to the manufacture method of above-mentioned encapsulating structure, this up and down the manufacturing process of paired justifying face base plate for packaging can comprise: first loading plate with relative two surfaces is provided; On two surfaces of this first loading plate, all form the peel ply that area is less than this first loading plate; The surface that does not form this peel ply at this first loading plate forms adhesion layer, so that this adhesion layer is around this peel ply surrounding; On this peel ply and adhesion layer, form metal level; On this metal level, order forms multiple electric contact mats and layer reinforced structure, this layer reinforced structure comprises at least one dielectric layer, is formed on line layer and multiple conductive blind hole that is formed in this dielectric layer and is electrically connected this line layer and electric contact mat on this dielectric layer, and the outermost line layer of this layer reinforced structure also has described wire pad; And form this insulating protective layer on this layer reinforced structure outermost layer, and form described perforate in this insulating protective layer, make described wire pad correspondence be exposed to respectively this perforate.Or, this up and down the manufacturing process of paired justifying face base plate for packaging comprise: first loading plate with relative two surfaces is provided; On two surfaces of this first loading plate, all form adhesion layer; The area that is comprehensively sticked on this adhesion layer is less than this first loading plate and surrounding be this adhesion layer around peel ply; On this peel ply and adhesion layer, form metal level; On this metal level, order forms multiple electric contact mats and layer reinforced structure, this layer reinforced structure comprises at least one dielectric layer, is formed on line layer and multiple conductive blind hole that is formed in this dielectric layer and is electrically connected this line layer and electric contact mat on this dielectric layer, and the outermost line layer of this layer reinforced structure also has described wire pad; And form this insulating protective layer on this layer reinforced structure outermost layer, and form described perforate in this insulating protective layer, make described wire pad correspondence be exposed to respectively this perforate.
In addition, in above-mentioned manufacture method, the manufacturing process of described base plate for packaging block can comprise: along this, cut at the edge of paired justifying face base plate for packaging up and down, and cutting edge is by this peel ply; Remove this first loading plate and peel ply with by this up and down paired justifying face base plate for packaging be separated into independently two justifying face base plate for packaging; And cut this justifying face base plate for packaging, and remove this metal level, to form described base plate for packaging block.
According to above-mentioned manufacture method, after removing this second loading plate, also can be included in respectively and form soldered ball on this electric contact mat.
The present invention also discloses the manufacture method of another kind of encapsulating structure, comprise: a paired justifying face base plate for packaging is up and down provided, on its two relative outermost surfaces, all form multiple electric contact mats and insulating protective layer, and in this insulating protective layer, form multiple perforates, make respectively this electric contact mat correspondence be exposed to respectively this perforate; Separate this paired justifying face base plate for packaging up and down, and cut this justifying face base plate for packaging, to form multiple base plate for packaging blocks, at each this base plate for packaging block, there is relative first surface and second surface, this first surface has described electric contact mat and insulating protective layer, and this second surface has multiple wire pads and dielectric layer, and described wire pad is embedded and exposes to this dielectric layer surface, and respectively this base plate for packaging block has and is (the base plate for packaging unit that m × n) matrix is arranged, wherein, m and n are the integer that is greater than 1; The second loading plate is set on the insulating protective layer of this base plate for packaging block; On the dielectric layer of each this base plate for packaging unit, connect and put semiconductor chip, to form the encapsulating structure block with multiple encapsulating structures unit, and this semiconductor chip has relative acting surface and non-acting surface, on this acting surface, there are multiple electronic padses, and this non-acting surface is fixedly arranged on this dielectric layer, and respectively this electronic pads is electrically connected to respectively this wire pad by bonding wire with correspondence; On this dielectric layer, described bonding wire and described semiconductor chip, form encapsulation material; Remove this second loading plate; And cut this encapsulating structure block to be separated into multiple encapsulating structures unit.
From the above mentioned, this up and down the manufacturing process of paired justifying face base plate for packaging can comprise: first loading plate with relative two surfaces is provided; On two surfaces of this first loading plate, all form the peel ply that area is less than this first loading plate; The surface that does not form this peel ply at this first loading plate forms adhesion layer, so that this adhesion layer is around this peel ply surrounding; On this peel ply and adhesion layer, form metal level; On this metal level, order forms multiple wire pads and layer reinforced structure, this layer reinforced structure comprises at least one dielectric layer, is formed on line layer and multiple conductive blind hole that is formed in this dielectric layer and is electrically connected this line layer and wire pad on this dielectric layer, and the outermost line layer of this layer reinforced structure also has described electric contact mat; And form this insulating protective layer on this layer reinforced structure outermost layer, and form described perforate in this insulating protective layer, make respectively this electric contact mat correspondence be exposed to respectively this perforate.Or, this up and down the manufacturing process of paired justifying face base plate for packaging comprise: first loading plate with relative two surfaces is provided; On two surfaces of this first loading plate, all form adhesion layer; The area that is comprehensively sticked on this adhesion layer is less than this first loading plate and surrounding be this adhesion layer around peel ply; On this peel ply and adhesion layer, form metal level; On this metal level, sequentially form multiple wire pads and layer reinforced structure, this layer reinforced structure comprises at least one dielectric layer, is formed on line layer and multiple conductive blind hole that is formed in this dielectric layer and is electrically connected this line layer and wire pad on this dielectric layer, and the outermost line layer of this layer reinforced structure also has described electric contact mat; And form this insulating protective layer on this layer reinforced structure outermost layer, and form described perforate in this insulating protective layer, make described electric contact mat correspondence be exposed to respectively this perforate.
In addition, according to above-mentioned manufacture method, the manufacturing process of described base plate for packaging block can comprise: along this, cut at the edge of paired justifying face base plate for packaging up and down, and cutting edge is by this peel ply; Remove this first loading plate and peel ply with by this up and down paired justifying face base plate for packaging be separated into independently two justifying face base plate for packaging; And cut this justifying face base plate for packaging, and remove this metal level, to form described base plate for packaging block.
The manufacture method of encapsulating structure from the above mentioned, after removing this second loading plate, also can be included in respectively and form soldered ball on this electric contact mat.
As from the foregoing, the manufacture method of encapsulating structure of the present invention is: first justifying face base plate for packaging is cut into multiple base plate for packaging blocks, respectively this base plate for packaging block includes multiple base plate for packaging unit; Then, on each this base plate for packaging unit, connect and put semiconductor chip and fix and protect with encapsulation material; Finally, cut into multiple encapsulating structures unit.Compared with prior art, the manufacture method of encapsulating structure of the present invention is integrated base plate for packaging manufacture and semiconductor die package, can be once the whole base plate for packaging unit in each this base plate for packaging block be carried out to semiconductor die package, to simplify processing step and to improve production capacity; Moreover, the area of base plate for packaging block of the present invention is moderate, can dwindle respectively this base plate for packaging unit bit errors in manufacturing process in each this base plate for packaging block, so the manufacture method of encapsulating structure of the present invention has the advantages such as higher production capacity and qualification rate.
Accompanying drawing explanation
Figure 1A to Fig. 1 H is the cross-sectional schematic of the first embodiment of the manufacture method of encapsulating structure of the present invention; Wherein, Figure 1A ' is another form of implementation of Figure 1A, and Fig. 1 E ' is the vertical view of Fig. 1 E;
The cross-sectional schematic of the second embodiment of the manufacture method that Fig. 2 A to Fig. 2 H is encapsulating structure of the present invention.
[primary clustering symbol description]
20a the first loading plate
20b the second loading plate
211 peel plies
212 adhesion layers
22 metal levels
23,23 ' electric contact mat
24 layer reinforced structures
241 dielectric layers
242 conductive blind holes
243 line layers
244,244 ' wire pad
25 insulating protective layers
250 perforates
26 surface-treated layers
27 cutting edges
28 semiconductor chips
28a acting surface
The non-acting surface of 28b
281 electronic padses
29 bonding wires
30 encapsulation materials
31 soldered balls
2a paired justifying face base plate for packaging up and down
2a ' justifying face base plate for packaging
2b base plate for packaging block
200a first surface
200b second surface
The matrix line number of m base plate for packaging block
The matrix columns of n base plate for packaging block
2c base plate for packaging unit
2b ' encapsulating structure block
2c ' encapsulating structure unit
Embodiment
In order further to understand other advantage of the present invention and effect, below by particular specific embodiment explanation embodiments of the present invention.
The first embodiment
Figure 1A to Fig. 1 H is the cross-sectional schematic of the first embodiment of the manufacture method of encapsulating structure of the present invention; Wherein, Figure 1A ' is another form of implementation of Figure 1A, and Fig. 1 E ' is the vertical view of Fig. 1 E.
As shown in Figure 1A, the one first loading plate 20a with relative two surfaces is provided, on its two surface, all form the peel ply 211 that area is less than this first loading plate 20a, and this first loading plate 20a do not form this peel ply 211 surface form adhesion layer 212, make this adhesion layer 212 around these peel ply 211 surroundings, and form metal level 22 on this peel ply 211 and adhesion layer 212; Wherein, this peel ply 211 can be release film, and the material of this metal level 22 can be copper, and this metal level 22 can be used as the crystal seed layer as current conduction path in plating step (seed layer).
As Figure 1A ' is depicted as another form of implementation of Figure 1A, the one first loading plate 20a with relative two surfaces is provided equally, on its two surface, all form adhesion layer 212, and the area that is comprehensively sticked on this adhesion layer 212 to be less than this first loading plate 20a and surrounding be this adhesion layer 212 around peel ply 211, and form metal level 22 on this peel ply 211 and adhesion layer 212.Following manufacture method illustrates with Figure 1A.
As shown in Figure 1B, on this metal level 22, order forms multiple electric contact mats 23 and layer reinforced structure 24, this layer reinforced structure 24 comprises at least one dielectric layer 241, is formed on line layer 243 and multiple conductive blind hole 242 that is formed in this dielectric layer 241 and is electrically connected this line layer 243 and electric contact mat 23 on this dielectric layer 241, and the outermost line layer 243 of this layer reinforced structure 24 also has multiple wire pads 244; Then, on these layer reinforced structure 24 outermost layers, form insulating protective layer 25, and form multiple perforates 250 in this insulating protective layer 25, make described wire pad 244 correspondences be exposed to respectively this perforate 250; Then, on described wire pad 244, form surface-treated layer 26, thereby form paired up and down justifying face base plate for packaging 2a, the material of this surface-treated layer 26 is that nickel/gold (Ni/Au), change nickel palladium soak gold (Electroless Nickel/Electroless Palladium/Immersion Gold, ENEPIG), tin (Sn), silver (Ag) or gold (Au).
As shown in Figure 1 C, along this, cut at the edge of paired justifying face base plate for packaging 2a up and down, and cutting edge 27 is by this peel ply 211.
As shown in Fig. 1 D, remove this first loading plate 20a and peel ply 211 with by this up and down paired justifying face base plate for packaging 2a be separated into independently two justifying face base plate for packaging 2a '; If according to the structure shown in Figure 1A ', remove this first loading plate 20a, peel ply 211 and adhesion layer 212 to be separated into independently two justifying face base plate for packaging 2a '.
As shown in Fig. 1 E and 1E ', Fig. 1 E ' is the vertical view of Fig. 1 E, as shown in the figure, cut this justifying face base plate for packaging 2a ', and remove this metal level 22, to form multiple base plate for packaging block 2b, and respectively this base plate for packaging block 2b has relative first surface 200a and second surface 200b, this first surface 200a has described wire pad 244 and insulating protective layer 25, and this second surface 200b has described electric contact mat 23 and dielectric layer 241, and described electric contact mat 23 is embedded and exposes to this dielectric layer 241 surfaces, and respectively this base plate for packaging block 2b has and is (the base plate for packaging unit 2c that m × n) matrix is arranged, wherein, m and n are the integer that is greater than 1, in the present embodiment, m and n are respectively 6 and 5, but not as limit.
As shown in Fig. 1 F, the second loading plate 20b is set on described electric contact mat 23 and dielectric layer 241.
As shown in Figure 1 G, on the insulating protective layer 25 of each this base plate for packaging unit 2c, connect and put semiconductor chip 28, to form the encapsulating structure block 2b ' with multiple encapsulating structures unit 2c ', and this semiconductor chip 28 has relative acting surface 28a and non-acting surface 28b, on this acting surface 28a, there are multiple electronic padses 281, and this non-acting surface 28b is fixedly arranged on this insulating protective layer 25, and respectively this electronic pads 281 is electrically connected to respectively this wire pad 244 by bonding wire 29 with correspondence; Then, on this insulating protective layer 25, described bonding wire 29 and described semiconductor chip 28, form encapsulation material 30; Then, remove this second loading plate 20b, and respectively on this electric contact mat 23, forming soldered ball 31; Or, on this electric contact mat 23, do not form soldered ball 31, and be directly used in and the electric connection (not representing in accompanying drawing) of Background Grid array packages (Land grid array, be called for short LGA) structure.
As shown in Fig. 1 H, cut this encapsulating structure block 2b ' to be separated into multiple encapsulating structures unit 2c '.
The second embodiment
Fig. 2 A to Fig. 2 H is the cross-sectional schematic of the second embodiment of the manufacture method of encapsulating structure of the present invention.
As shown in Figure 2 A, the one first loading plate 20a with relative two surfaces is provided, on its two surface, all form the peel ply 211 that area is less than this first loading plate 20a, and this first loading plate 20a do not form this peel ply 211 surface form adhesion layer 212, make this adhesion layer 212 around these peel ply 211 surroundings, and form metal level 22 on this peel ply 211 and adhesion layer 212; Wherein, this peel ply 211 can be release film, and the material of this metal level 22 can be copper, and this metal level 22 is as the crystal seed layer of current conduction path in plating step.Similarly, another form of implementation of Fig. 2 A also can be as shown in Figure 1A ', and its details refers to the above-mentioned explanation about Figure 1A ', and not in this to go forth.
As shown in Figure 2 B, on this metal level 22, order forms multiple wire pads 244 ' and layer reinforced structure 24, this layer reinforced structure 24 comprises at least one dielectric layer 241, is formed on line layer 243 and multiple conductive blind hole 242 that is formed in this dielectric layer 241 and is electrically connected this line layer 243 and wire pad 244 ' on this dielectric layer 241, and the outermost line layer 243 of this layer reinforced structure 24 also has multiple electric contact mats 23 '; Then; on these layer reinforced structure 24 outermost layers, form this insulating protective layer 25; and in this insulating protective layer 25, form multiple perforates 250, make respectively this electric contact mat 23 ' correspondence be exposed to respectively this perforate 250, thereby form paired up and down justifying face base plate for packaging 2a.
As shown in Figure 2 C, along this, cut at the edge of paired justifying face base plate for packaging 2a up and down, and cutting edge 27 is by this peel ply 211, to remove this adhesion layer 212.
As shown in Figure 2 D, remove this first loading plate 20a and peel ply 211 with by this up and down paired justifying face base plate for packaging 2a be separated into independently two justifying face base plate for packaging 2a '.
As shown in Figure 2 E, cut this justifying face base plate for packaging 2a ', and remove this metal level 22, to form multiple base plate for packaging block 2b, and respectively this base plate for packaging block 2b has relative first surface 200a and second surface 200b, at this first surface 200a, there is described electric contact mat 23 ' and insulating protective layer 25, and this second surface 200b has described wire pad 244 ' and dielectric layer 241, and described wire pad 244 ' is embedded and exposes to this dielectric layer 241 surfaces, and respectively this base plate for packaging block 2b has and is (the base plate for packaging unit 2c that m × n) matrix is arranged, wherein, m and n are the integer that is greater than 1.
As shown in Figure 2 F, the second loading plate 20b is set on the insulating protective layer 25 of this base plate for packaging block 2b.
As shown in Figure 2 G, at the upper surface-treated layer 26 that forms of described wire pad 244 ', the material of this surface-treated layer 26 is that nickel/gold (Ni/Au), change nickel palladium soak gold (Electroless Nickel/ElectrolessPalladium/Immersion Gold, ENEPIG), tin (Sn), silver (Ag) or gold (Au); Also on the dielectric layer 241 of each this base plate for packaging unit 2c, connect and put semiconductor chip 28, to form the encapsulating structure block 2b ' with multiple encapsulating structures unit 2c ', and this semiconductor chip 28 has relative acting surface 28a and non-acting surface 28b, on this acting surface 28a, there are multiple electronic padses 281, and this non-acting surface 28b is fixedly arranged on this dielectric layer 241, and respectively this electronic pads 281 is electrically connected to respectively this wire pad 244 ' by bonding wire 29 with correspondence; Then, on this dielectric layer 241, described bonding wire 29 and described semiconductor chip 28, form encapsulation material 30; Then, remove this second loading plate 20b, and respectively on this electric contact mat 23 ', forming soldered ball 31; Or, on this electric contact mat 23 ', do not form soldered ball 31, and be directly used in and the electric connection (not representing with accompanying drawing) of Background Grid array packages (Land grid array, be called for short LGA) structure.
As shown in Fig. 2 H, cut this encapsulating structure block 2b ' to be separated into multiple encapsulating structures unit 2c '.
Another form of implementation of the present invention, also can first paired up and down justifying face base plate for packaging be cut into multiple paired base plate for packaging blocks up and down, again by respectively this up and down paired base plate for packaging block be separated into independently two base plate for packaging blocks, and other step is with noted earlier, not in this to go forth.
In sum, the manufacture method of encapsulating structure of the present invention first cuts into multiple base plate for packaging blocks by justifying face base plate for packaging, and respectively this base plate for packaging block includes multiple base plate for packaging unit; Then, on each this base plate for packaging unit, connect and put semiconductor chip and fix and protect with encapsulation material; Finally, cut into multiple encapsulating structures unit.Compared with prior art, the manufacture method of encapsulating structure provided by the invention is integrated base plate for packaging manufacture and semiconductor die package, can be once the whole base plate for packaging unit in each this base plate for packaging block be carried out to semiconductor die package, to simplify manufacturing process and to improve production capacity; Moreover, the area of base plate for packaging block of the present invention is moderate, can dwindle respectively this base plate for packaging unit bit errors in manufacturing process in each this base plate for packaging block, so the manufacture method of encapsulating structure of the present invention has the advantages such as higher production capacity and qualification rate.
Claims (12)
1. a manufacture method for semiconductor package, is characterized in that, this manufacture method comprises:
One paired justifying face base plate for packaging is up and down provided, on its two relative outermost surfaces, all forms multiple wire pads and insulating protective layer, and form multiple perforates in this insulating protective layer, make described wire pad correspondence be exposed to respectively this perforate;
Separate this paired justifying face base plate for packaging up and down, and cut this justifying face base plate for packaging, to form multiple base plate for packaging blocks, and respectively this base plate for packaging block has relative first surface and second surface, at this first surface, there is described wire pad and insulating protective layer, and this second surface has multiple electric contact mats and dielectric layer, and described electric contact mat is embedded and exposes to this dielectric layer surface, and respectively this base plate for packaging block has the base plate for packaging unit that is the arrangement of m × n matrix, wherein, m and n are the integer that is greater than 1;
The second loading plate is set on described electric contact mat and dielectric layer;
On the insulating protective layer of each this base plate for packaging unit, connect and put semiconductor chip, to form the encapsulating structure block with multiple encapsulating structures unit, and this semiconductor chip has relative acting surface and non-acting surface, on this acting surface, there are multiple electronic padses, and this non-acting surface is fixedly arranged on this insulating protective layer, and respectively this electronic pads is electrically connected to respectively this wire pad by bonding wire with correspondence;
On this insulating protective layer, described bonding wire and described semiconductor chip, form encapsulation material;
Remove this second loading plate; And
Cut this encapsulating structure block to be separated into multiple encapsulating structures unit.
2. the manufacture method of semiconductor package according to claim 1, is characterized in that, the manufacturing process of this upper and lower paired justifying face base plate for packaging comprises:
One first loading plate with relative two surfaces is provided;
On two surfaces of this first loading plate, all form the peel ply that area is less than this first loading plate;
The surface that does not form this peel ply at this first loading plate forms adhesion layer, so that this adhesion layer is around this peel ply surrounding;
On this peel ply and adhesion layer, form metal level;
On this metal level, order forms multiple electric contact mats and layer reinforced structure, this layer reinforced structure comprises at least one dielectric layer, is formed on line layer and multiple conductive blind hole that is formed in this dielectric layer and is electrically connected this line layer and electric contact mat on this dielectric layer, and the outermost line layer of this layer reinforced structure also has described wire pad; And
On this layer reinforced structure outermost layer, form this insulating protective layer, and form described perforate in this insulating protective layer, make described wire pad correspondence be exposed to respectively this perforate.
3. the manufacture method of semiconductor package according to claim 1, is characterized in that, the manufacturing process of this upper and lower paired justifying face base plate for packaging comprises:
One first loading plate with relative two surfaces is provided;
On two surfaces of this first loading plate, all form adhesion layer;
The area that is comprehensively sticked on this adhesion layer is less than this first loading plate and surrounding be this adhesion layer around peel ply;
On this peel ply and adhesion layer, form metal level;
On this metal level, order forms multiple electric contact mats and layer reinforced structure, this layer reinforced structure comprises at least one dielectric layer, is formed at line layer and multiple conductive blind hole that is formed in this dielectric layer and is electrically connected this line layer and electric contact mat on this dielectric layer, and the outermost line layer of this layer reinforced structure also has described wire pad; And
On this layer reinforced structure outermost layer, form this insulating protective layer, and form described perforate in this insulating protective layer, make described wire pad correspondence be exposed to respectively this perforate.
4. according to the manufacture method of the semiconductor package described in claim 2 or 3, it is characterized in that, the manufacturing process of described base plate for packaging block comprises:
Along this, cut at the edge of paired justifying face base plate for packaging up and down, and cutting edge is by this peel ply;
Remove this first loading plate and peel ply with by this up and down paired justifying face base plate for packaging be separated into independently two justifying face base plate for packaging; And
Cut this justifying face base plate for packaging, and remove this metal level, to form described base plate for packaging block.
5. the manufacture method of semiconductor package according to claim 1, is characterized in that, is also included on described wire pad and forms surface-treated layer.
6. the manufacture method of semiconductor package according to claim 1, is characterized in that, after removing this second loading plate, is also included in respectively and forms soldered ball on this electric contact mat.
7. a manufacture method for semiconductor package, is characterized in that, this manufacture method comprises:
One paired justifying face base plate for packaging is up and down provided, on its two relative outermost surfaces, all forms multiple electric contact mats and insulating protective layer, and form multiple perforates in this insulating protective layer, make respectively this electric contact mat correspondence be exposed to respectively this perforate;
Separate this paired justifying face base plate for packaging up and down, and cut this justifying face base plate for packaging, to form multiple base plate for packaging blocks, at each this base plate for packaging block, there is relative first surface and second surface, this first surface has described electric contact mat and insulating protective layer, and this second surface has multiple wire pads and dielectric layer, and described wire pad is embedded and exposes to this dielectric layer surface, and respectively this base plate for packaging block has the base plate for packaging unit that is the arrangement of m × n matrix, wherein, m and n are the integer that is greater than 1;
The second loading plate is set on the insulating protective layer of this base plate for packaging block;
On the dielectric layer of each this base plate for packaging unit, connect and put semiconductor chip, to form the encapsulating structure block with multiple encapsulating structures unit, and this semiconductor chip has relative acting surface and non-acting surface, on this acting surface, there are multiple electronic padses, and this non-acting surface is fixedly arranged on this dielectric layer, and respectively this electronic pads is electrically connected to respectively this wire pad by bonding wire with correspondence;
On this dielectric layer, described bonding wire and described semiconductor chip, form encapsulation material;
Remove this second loading plate; And
Cut this encapsulating structure block to be separated into multiple encapsulating structures unit.
8. the manufacture method of semiconductor package according to claim 7, is characterized in that, the manufacturing process of this upper and lower paired justifying face base plate for packaging comprises:
One first loading plate with relative two surfaces is provided;
On two surfaces of this first loading plate, all form the peel ply that area is less than this first loading plate;
The surface that does not form this peel ply at this first loading plate forms adhesion layer, so that this adhesion layer is around this peel ply surrounding;
On this peel ply and adhesion layer, form metal level;
On this metal level, order forms multiple wire pads and layer reinforced structure, this layer reinforced structure comprises at least one dielectric layer, is formed on line layer and multiple conductive blind hole that is formed in this dielectric layer and is electrically connected this line layer and wire pad on this dielectric layer, and the outermost line layer of this layer reinforced structure also has described electric contact mat; And
On this layer reinforced structure outermost layer, form this insulating protective layer, and form described perforate in this insulating protective layer, make respectively this electric contact mat correspondence be exposed to respectively this perforate.
9. the manufacture method of semiconductor package according to claim 7, is characterized in that, the manufacturing process of this upper and lower paired justifying face base plate for packaging comprises:
One first loading plate with relative two surfaces is provided;
On two surfaces of this first loading plate, all form adhesion layer;
The area that is comprehensively sticked on this adhesion layer is less than this first loading plate and surrounding be this adhesion layer around peel ply;
On this peel ply and adhesion layer, form metal level;
On this metal level, order forms multiple wire pads and layer reinforced structure, this layer reinforced structure comprises at least one dielectric layer, is formed on line layer and multiple conductive blind hole that is formed in this dielectric layer and is electrically connected this line layer and wire pad on this dielectric layer, and the outermost line layer of this layer reinforced structure also has described electric contact mat; And
On this layer reinforced structure outermost layer, form this insulating protective layer, and form described perforate in this insulating protective layer, make described electric contact mat correspondence be exposed to respectively this perforate.
10. the manufacture method of semiconductor package according to claim 8 or claim 9, is characterized in that, the manufacturing process of described base plate for packaging block comprises:
Along this, cut at the edge of paired justifying face base plate for packaging up and down, and cutting edge is by this peel ply;
Remove this first loading plate and peel ply with by this up and down paired justifying face base plate for packaging be separated into independently two justifying face base plate for packaging; And
Cut this justifying face base plate for packaging, and remove this metal level, to form described base plate for packaging block.
The manufacture method of 11. semiconductor packages according to claim 7, is characterized in that, is also included on described wire pad and forms surface-treated layer.
The manufacture method of 12. semiconductor packages according to claim 7, is characterized in that, after removing this second loading plate, is also included in respectively and forms soldered ball on this electric contact mat.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010228354.3A CN102339761B (en) | 2010-07-14 | 2010-07-14 | Method for manufacturing packaged structures |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010228354.3A CN102339761B (en) | 2010-07-14 | 2010-07-14 | Method for manufacturing packaged structures |
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| Publication Number | Publication Date |
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| CN102339761A CN102339761A (en) | 2012-02-01 |
| CN102339761B true CN102339761B (en) | 2014-05-07 |
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| CN201010228354.3A Expired - Fee Related CN102339761B (en) | 2010-07-14 | 2010-07-14 | Method for manufacturing packaged structures |
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| CN111238694B (en) * | 2020-02-06 | 2022-07-12 | 腾讯科技（深圳）有限公司 | Touch sensor, touch event detection method and device and intelligent robot |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1956635A (en) * | 2005-10-27 | 2007-05-02 | 全懋精密科技股份有限公司 | Structure of thin wire of multi-dielectric layer circuit board and its manufacturing method |
| CN1972554A (en) * | 2005-11-25 | 2007-05-30 | 全懋精密科技股份有限公司 | Thin circuit board structure |
| CN1980541A (en) * | 2005-12-07 | 2007-06-13 | 新光电气工业株式会社 | Method of manufacturing wiring substrate and method of manufacturing electronic component mounting structure |
| CN101471328A (en) * | 2007-12-25 | 2009-07-01 | 力成科技股份有限公司 | Substrate panel |
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2010
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1956635A (en) * | 2005-10-27 | 2007-05-02 | 全懋精密科技股份有限公司 | Structure of thin wire of multi-dielectric layer circuit board and its manufacturing method |
| CN1972554A (en) * | 2005-11-25 | 2007-05-30 | 全懋精密科技股份有限公司 | Thin circuit board structure |
| CN1980541A (en) * | 2005-12-07 | 2007-06-13 | 新光电气工业株式会社 | Method of manufacturing wiring substrate and method of manufacturing electronic component mounting structure |
| CN101471328A (en) * | 2007-12-25 | 2009-07-01 | 力成科技股份有限公司 | Substrate panel |
Non-Patent Citations (1)
| Title |
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| JP特开2007-158174A 2007.06.21 |
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