CN100562991C - Semiconductor package and forming method thereof - Google Patents

Semiconductor package and forming method thereof Download PDF

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Publication number
CN100562991C
CN100562991C CNB2007101008566A CN200710100856A CN100562991C CN 100562991 C CN100562991 C CN 100562991C CN B2007101008566 A CNB2007101008566 A CN B2007101008566A CN 200710100856 A CN200710100856 A CN 200710100856A CN 100562991 C CN100562991 C CN 100562991C
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substrate layer
chip
semiconductor package
connector
interconnecting construction
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CNB2007101008566A
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CN101170088A (en
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吴俊毅
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract

A kind of semiconductor package comprises: substrate layer, its composition comprise alloy 42 materials; Chip is attached on first side of substrate layer; And interconnecting construction, be positioned on the chip, wherein interconnecting construction comprises the lead of connector and connection chip.Therefore the invention has the advantages that alloy 42 materials and semiconductor chip have approximate thermal coefficient of expansion, the stress that imposes on chip by packaging body can reduce.

Description

Semiconductor package and forming method thereof
Technical field
The present invention is particularly to a kind of structure and method that embeds semiconductor chip to packaging body relevant for a kind of encapsulation of semiconductor chip.
Background technology
In semi-conductor industry, integrated circuit generally is formed on the wafer, wherein, a plurality of semiconductor chips on same wafer can form simultaneously, therefore, these semiconductor chips can cut out from wafer subsequently, yet because these semiconductor chip volumes are both little and frangible, therefore must be encapsulated earlier before using these chips.
Fig. 1 shows traditional packaging body, it comprises semiconductor chip 2, it can be attached on the package substrates 4 by projection (solderbumps) 6, and package substrates 4 comprises core layer 8 and a plurality of interconnection line layer that is built in core layer both sides about in the of 8, and chip 2 and core layer 8 are separated by interconnection line layer.Chip 2 is attached to a side of core layer 8, and at its relative opposite side, the tin ball 10 that then forms ball grid array (BGA) is to connect the electronic component of package substrates 4 to other, motherboard (motherboard) for example, the tin ball 10 of chip 2 and ball grid array carries out electric coupling by the metal wire and the connector of interconnection line layer.12 of connectors are formed in the core layer 8 and are electrically connected to opposite side with the side from core layer 8.
The problem of conventional package body is as follows.At first, the cost that forms projection is very high, and if the projection connection failure also make packaging technology suffer from high qualification rate loss easily.Secondly, the thermal coefficient of expansion that chip 2 generally has (CTE) is approximately 2.3 to 4.2, and on the other hand, core layer 8 is because generally by two Maleimides-triazine resin (Bismaleimide-Triazine; BT) form, its thermal coefficient of expansion is approximately 15, and therefore, under thermal cycle technology, unmatched thermal coefficient of expansion causes being applied to the stress on chip 2 and the projection 6, can make chip 2 generation warpages, and/or makes the projection connection failure.The 3rd, owing to use core layer 8, the thickness of packaging body can increase to some extent, can reach 2.3mm comprising BGA tin ball 10, package substrates 4, chip 2 in the gross thickness of interior whole packaging body, the thickness that this kind is blocked up does not also meet following specification demand, therefore needs a kind of encapsulating structure of novelty to solve the problems referred to above.
Summary of the invention
For achieving the above object, the present invention is proposed.
In view of this, embodiments of the invention disclose a kind of semiconductor package, comprising: substrate layer, its composition comprise alloy 42 materials; Chip is attached on first side of substrate layer; And interconnecting construction, be positioned on the chip, wherein interconnecting construction comprises the lead of connector and connection chip.
Aforesaid semiconductor package, it also comprises second substrate layer, and this second substrate layer composition comprises alloy 42 materials, is positioned on first side of this first substrate layer, and wherein this chip is formed in the opening of this second substrate layer.
Aforesaid semiconductor package, it also comprises extra electronic component, is attached on first side of this first substrate layer and is connected to this interconnecting construction.
Aforesaid semiconductor package, wherein this interconnecting construction comprises that connector is to be directly connected to this chip.
Aforesaid semiconductor package, wherein this first substrate layer does not contain interconnecting construction with respect to second side of this first side.
Another embodiment of the present invention discloses a kind of semiconductor package, comprising: first substrate layer, its composition comprise alloy 42 materials; Second substrate layer is attached on first side of first substrate layer; Opening is arranged in second substrate layer; Chip is arranged in opening, and is attached on first side of first substrate layer; First insulating barrier is positioned on the chip and second substrate layer; A plurality of first connectors are arranged in insulating barrier and entity contact chip; And interconnecting construction, be positioned on first insulating barrier, wherein, interconnecting construction comprises: second insulating barrier, a plurality of second connectors and lead are arranged in second insulating barrier, wherein have at least second connector and the lead of part to be connected to described first connector; Reach a plurality of ball grid array tin balls, be positioned at the upper surface of interconnecting construction.
Aforesaid semiconductor package, wherein this second substrate layer composition comprises alloy 42 materials.
Aforesaid semiconductor package, wherein this first insulating barrier comprises that ABF increases the tunic material.
Aforesaid semiconductor package, it also comprises extra electronic component, is attached on first side of this first substrate layer, and is connected to this interconnecting construction by the 3rd connector, wherein, being connected between this interconnecting construction and the 3rd connector do not contain projection.
Aforesaid semiconductor package, wherein this first substrate layer does not contain interconnecting construction with respect to second side of this first side.
Therefore the advantage of the embodiment of the invention is that alloy 42 materials and semiconductor chip have approximate thermal coefficient of expansion, and the stress that imposes on chip by packaging body can reduce.
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended accompanying drawing, be described in detail below.
Description of drawings
Fig. 1 shows traditional packaging body, and wherein interconnection line layer is formed at the both sides of core layer.
Fig. 2 to Figure 10 shows the manufacture process profile of the preferred embodiment of the present invention.
Wherein, description of reference numerals is as follows:
2 semiconductor chips, 6 projections, 4 package substrates
8 core layers, 10 ball grid array tin balls, 12 connectors
20 substrate layers, 24 substrate layers, 22 sticky materials
20 1, 20 2Core layer 26,28 openings 30 chips
32 electronic components, 34 insulating barriers, 38 openings
40 contact mats, 42 openings, 44 connectors
46 inculating crystal layers, 48 dry films, 50 conductive patterns
52 insulating barriers, 60 bump bond, 62 anti-welding cuticula
64 ball grid array tin ball P spacings
Embodiment
About the manufacturing of each embodiment and occupation mode for as detailed below.Yet, it should be noted that, various applicable inventive concept provided by the present invention is implemented according to this according to the various variations of particular content, and only is to be used for showing specifically using and making method of the present invention at this specific embodiment of discussing, rather than is used to limit scope of the present invention.
Present embodiment provides encapsulating structure of a kind of novelty and forming method thereof, and its manufacture process is shown in Fig. 2 to Figure 10.In addition, in various embodiment of the present invention and accompanying drawing, same-sign is in order to indicate identical or like.
Fig. 2 shows the structure of initial manufacturing process, and it comprises substrate layer 20, substrate layer 24 and sticky material 22.In an embodiment, the composition of substrate layer 20 comprises the core layer 20 that contains alloy 42 materials (alloy 42) 1, this material is a dilval, can be described in detail in following paragraph.In addition, two core layers 20 2Composition include copper product, it can be plated out at core layer 20 1Both sides, similarly, substrate layer 24 comprises the core layer 24 that contains alloy 42 materials (alloy 42) 1, in addition, two core layers 24 2Include copper product, it can be plated out at core layer 24 1Both sides.
Alloy 42 materials approximately comprise the nickel of 42% percentage by weight and the iron of 58% percentage by weight, refer to the shared percentage of nickel and number 42.The coefficient of elasticity of alloy 42 materials is about per square inch (PSI) 20.7E6 pound, and thermal coefficient of expansion (CTE) is about 4.0E-06/K to 4.7E-06/K, and thermal conductivity is about 16W/mk, and resistivity value is about 70 μ Ω cm.The thickness of substrate layer 20 can be 4 Mills (mil) substantially, and simultaneously, the thickness of substrate layer 24 can be 12 Mills (mil) substantially.Substrate layer 20 and substrate layer 24 not only can provide protection to the accompanying chip of subsequent technique, also can provide structural support.Substrate layer 20 and substrate layer 24 can pass through sticky material 22 gluings along with the mode of lamination (laminating press), for example be prepreg (prepreg; Preimpregnated fibres).Though substrate layer 20 and substrate layer 24 can be considered alloy 42 materials, yet it also allows slightly different composition, must identical thermal coefficient of expansion be arranged with alloy 42 materials.
Please refer to Fig. 3, opening 26 and 28 forms by substrate layer 24 and the sticky material 22 of removing part, and opening 26 is set and is used to place chip, so the size of opening 26 depends on the size of chip.28 of openings optionally form the electronic component that can be incorporated into packaging body to place, for example passive device such as electric capacity or resistance.In another embodiment, opening 26 and 28 also can be pre-formed to substrate layer 20 at attaching substrate layer 24.
In Fig. 4, chip 30 is placed in the opening 26 and is attached on the substrate layer 20, and preferred way is to starch as sticky material with for example silver.Electronic component 32 also can be placed in the opening 28 and be attached on the substrate layer 20.
Please refer to Fig. 5, insulating barrier 34 is formed on the previous structure, and insulating barrier 34 comprises organic material, and for example Japanese Ajinomoto company is supplied increases tunic material (ABF; Ajinomoto buildupfilm), however other general materials are prepreg (prepreg) or gum Copper Foil (RCC for example; Resincoated copper) also can use, in this example, insulating barrier 34 is to form with the ABF material, and this ABF material can be laminated on the structure of Fig. 4, and it is last and softening to form smooth upper surface that heat and pressure can be applied to this layer.This heat and pressure also can assist insulating barrier 34 to insert the space of 24 of chip 30 (or electronic component 32) and substrate layers, the result, thickness T 1 between the upper surface of the upper surface of chip 30 and insulating barrier 34 is preferably about 25 μ m to 35 μ m, most preferably then is about 30 μ m.
Form opening 38 subsequently and (be also referred to as bump bottom metal layer (under bump metallurgy) with the contact mat 40 that exposes at chip 30 upper surfaces; Or abbreviation UBM).Preferably, opening 38 forms by laser drill, and the insulating barrier 34 that wherein covers UBM 40 is given burn off.In addition, also can form opening 42 to expose contact mat (not shown) at electronic component 32 upper surfaces.
Fig. 6 shows by selectivity filled conductive material to opening 38 and 42 modes with formation connector 44 (by-vias).This electric conducting material can be general material commonly used, and for example in an embodiment, this electric conducting material comprises copper or copper alloy, yet other also can use as silver or aluminium.This fill method comprises electroless plating or electroplating technology, and connector 44 directly connects UBM 40 and is formed at interconnecting construction on the connector 44 at subsequent step, so projection (solder bumps) is unwanted.In addition, connector 44 also connects interconnecting construction and electronic component 32, and preferably, the upper surface of connector 44 is contour with the upper surface of insulating barrier 34 in fact, and perhaps, the upper surface of connector 44 is a shade below the upper surface of insulating barrier 34.
Please refer to Fig. 7, thin inculating crystal layer 46, preferred person comprises copper product, can be formed on the surface of insulating barrier 34 and connector 44, and wherein, electroless plating is preferred implementation method, and the preferred thickness of the inculating crystal layer 46 that this is thin is about less than 0.8 μ m.Dry film (dry film) 48 then is formed on the inculating crystal layer 46, carries out Patternized technique subsequently to form opening, to be inserted wherein by the follow-up metal wire that forms.The thickness preferred value of dry film 48 is that the thickness of the follow-up formed lead of foundation decides, and for example in an embodiment, the thickness T 2 of dry film 48 is between about 20 μ m and 25 μ m, is more preferably about 20 μ m.
See also Fig. 8, conductive pattern 50 is formed in the inculating crystal layer 46 not on the part that is covered by dry film 48, and it can comprise lead and conductive pad, and generation type for example is the selective electroplating method.The thickness that is preferably formed of conductive pattern 50 is the thickness of essence near dry film 48, and the preferred material of conductive pattern 50 is copper or copper alloy, yet, other general common metal materials for example silver, aluminium, and nickel etc. also can use.The upper surface of conductive pattern 50 is preferably contour with the upper surface of dry film 48 in fact, and perhaps, the upper surface of conductive pattern 50 also can be a shade below the upper surface of dry film 48.After forming conductive pattern 50, the part that is positioned under the dry film 48 in dry film 48 and the inculating crystal layer 46 is removed in the lump, for example in an embodiment, dry film 48 can be removed by alkaline solution, and the part that is positioned in the inculating crystal layer 46 under the dry film 48 then can fast-etching technology (flash etching) be removed.Because the relation of flanking effect (side effect), in fast-etching technology, conductive pattern 50 also can be removed thin layer.
Please refer to Fig. 9, follow the smooth formula of covering and form insulating barrier 52, it can select to use method identical with insulating barrier 34 essence and essence identical materials to form.Thickness T 3 preferred persons from the upper surface of conductive pattern 50 to the upper surface of insulating barrier 52 for example are about 30 μ m for approaching thickness T 1.
The technology that continues then is to form more interconnection line layer, comprises connector and conductive pattern, and its final structure is shown among Figure 10.For each interconnection line layer, its processing step can be identical with the formation method essence of connector 44 and conductive pattern 50, preferably, can form 3 to 5 layers interconnection line layer (comprising the interconnection line layer that is made of connector 44 and conductive pattern 50), wherein each interconnection line layer comprises the connector of one deck conductive pattern and below thereof.
In alternate embodiment, the method that other are known, for example embedding technology also can be used for forming interconnection line layer, generally speaking, embedding technology comprises the following step: at first form exhausted layer, formation is opened in the exhausted layer then, inserts opening with electric conducting materials such as copper or copper alloys again, carry out chemical mechanical milling tech to remove unnecessary electric conducting material, the remainder of this electric conducting material then forms connector and conductive pattern.
Refer again to Figure 10, bump bond (bump pads) 60 also can be formed in the interconnection line layer on upper strata.Then form anti-welding cuticula 62 (solder mask; Be also referred to as solder resist: solder resist), its thickness can be 20 μ m, form solder resist opening (SRO:solder resist opening) afterwards with the bump bond 60 under sudden and violent, ball grid array tin ball (BGA balls) 64 then is formed on the bump bond 60 subsequently.And about bump bond 60, anti-welding cuticula 62 and ball grid array tin ball 64 owing to be prior art, therefore will not describe in detail at this.Package substrates with chimeric chip is then passed through ball grid array tin ball 64 attached on the motherboard thereupon.
Using alloy 42 is that it has the thermal coefficient of expansion between 4.0E-06/K to 4.7E-06/K as the advantage of substrate layer, therefore can with thermal coefficient of expansion (between 2.3E-06/K to the 4.2E-06/K) matched well of chip.When thermal cycle (thermal cycle) technology, therefore the stress that imposes on chip by substrate layer 20 and 24 can reduce to minimum, by contrast, traditional core material layer generally comprises two Maleimides-triazine resin (Bismaleimide-Triazine; BT), its thermal coefficient of expansion is 15E-06/K, and therefore heavily stressed meeting is applied on the chip of the package substrates with BT resin core layer.Simulation result shows to have the traditional B T resin core layer package substrates of (thickness is about 100 μ m), will cause laminated sheet (laminate), increases the bent about 125 μ m of tunic material as ABF, and embodiments of the invention then have only bent about 40 μ m.Therefore the reliability of this packaging body is improved.
The embodiment of the invention also has some other advantage, and for example owing to removed core layer from package substrates, electronic signal can be more efficient through interconnection line layer, and the waste of the space of interconnection line layer is less.In view of the above, even the quantity of interconnection line layer can reduce to of the present invention 5 layers 3 layers from 8 layers of conventional package substrates.The thickness of whole base plate for packaging also can reduce between the Mill, for example about 26 Mill to 30 in view of the above.In addition, the mid portion from interconnection line layer removes electricity and the insertion loss (insertion losses) that core layer can reduce packaging body.
Another advantage of the embodiment of the invention is, because connector 44 directly connects chip 30, does not therefore need anti-solder flux, and the spacing P of chip 30 (please refer to Figure 10) also can reduce.In an embodiment, spacing P approximately is 120 μ m, and in traditional packaging body, because projection is used to connect chip and package substrates, so minimum spacing is at least also wanted 140 μ m.
Though the present invention with preferred embodiment openly as above; right its is not in order to limit the present invention; those skilled in the art; without departing from the spirit and scope of the present invention; when can doing a little change and modification, so protection scope of the present invention is as the criterion when looking the scope that appending claims defines.

Claims (10)

1. semiconductor package comprises:
First substrate layer, its composition comprise alloy 42 materials;
Chip is attached on first side of this first substrate layer; And
Interconnecting construction is positioned on this chip, and wherein this interconnecting construction comprises connector and connects the lead of this chip.
2. semiconductor package as claimed in claim 1, it also comprises second substrate layer, and this second substrate layer composition comprises alloy 42 materials, is positioned on first side of this first substrate layer, and wherein this chip is formed in the opening of this second substrate layer.
3. semiconductor package as claimed in claim 1, it also comprises extra electronic component, is attached on first side of this first substrate layer and is connected to this interconnecting construction.
4. semiconductor package as claimed in claim 1, wherein this interconnecting construction comprises that connector is to be directly connected to this chip.
5. semiconductor package as claimed in claim 1, wherein this first substrate layer does not contain interconnecting construction with respect to second side of this first side.
6. semiconductor package comprises:
First substrate layer, its composition comprise alloy 42 materials;
Second substrate layer is attached on first side of this first substrate layer;
Opening is arranged in this second substrate layer;
Chip is arranged in this opening, and is attached on first side of this first substrate layer;
First insulating barrier is positioned on this chip and second substrate layer;
A plurality of first connectors are arranged in this insulating barrier and entity and contact this chip; And
Interconnecting construction is positioned on this first insulating barrier, and wherein, this interconnecting construction comprises:
Second insulating barrier,
A plurality of second connectors and lead are arranged in this second insulating barrier, wherein have at least second connector and the lead of part to be connected to described first connector; And
A plurality of ball grid array tin balls are positioned at the upper surface of this interconnecting construction.
7. semiconductor package as claimed in claim 6, wherein this second substrate layer composition comprises alloy 42 materials.
8. semiconductor package as claimed in claim 6, wherein this first insulating barrier comprises and increases the tunic material.
9. semiconductor package as claimed in claim 6, it also comprises extra electronic component, is attached on first side of this first substrate layer, and is connected to this interconnecting construction by the 3rd connector, wherein, being connected between this interconnecting construction and the 3rd connector do not contain projection.
10. semiconductor package as claimed in claim 6, wherein this first substrate layer does not contain interconnecting construction with respect to second side of this first side.
CNB2007101008566A 2006-10-27 2007-04-20 Semiconductor package and forming method thereof Active CN100562991C (en)

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