CN100562991C - 半导体封装结构及其形成方法 - Google Patents

半导体封装结构及其形成方法 Download PDF

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CN100562991C
CN100562991C CNB2007101008566A CN200710100856A CN100562991C CN 100562991 C CN100562991 C CN 100562991C CN B2007101008566 A CNB2007101008566 A CN B2007101008566A CN 200710100856 A CN200710100856 A CN 200710100856A CN 100562991 C CN100562991 C CN 100562991C
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substrate layer
chip
semiconductor package
connector
interconnecting construction
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CN101170088A (zh
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吴俊毅
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体封装结构，包括：基板层，其成分包括合金42材料；芯片，附着于基板层的第一侧面上；及互连线结构，位于芯片上，其中互连线结构包括插塞及连接芯片的导线。本发明的优点在于合金42材料和半导体芯片有近似的热膨胀系数，因此由封装体施加给芯片的应力可以减少。

Description

半导体封装结构及其形成方法
技术领域
本发明有关于一种半导体芯片的封装，特别有关于一种嵌入半导体芯片至封装体的结构及方法。
背景技术
在半导体工业中，集成电路一般形成于晶片上，其中，在同一片晶片上的多个半导体芯片可同时形成，因此，这些半导体芯片随后可从晶片上切割出来，然而由于这些半导体芯片体积既小且易碎，因此在使用这些芯片之前必须先予以封装。
图1显示传统的封装体，其包括半导体芯片2，其可通过凸块(solderbumps)6附着于封装基底4上，封装基底4包括核心层8及多个建构在核心层8上下两侧的互连线层，芯片2和核心层8被互连线层所分隔。芯片2附着在核心层8的一侧，而在其相对的另一侧，则形成球栅阵列(BGA)的锡球10以连接封装基底4至其他的电子元件，例如主机板(motherboard)，芯片2和球栅阵列的锡球10通过互连线层的金属线和插塞进行电耦接。插塞12则形成于核心层8中以从核心层8的一侧电连接至另一侧。
传统封装体的问题如下。首先，形成凸块的成本很高，且如果凸块连接失败也容易使封装工艺遭遇到高的合格率损失。其次，芯片2一般具有的热膨胀系数(CTE)大约为2.3至4.2，另一方面，核心层8由于一般由双马来亚酰胺-三氮杂苯树脂(Bismaleimide-Triazine；BT)形成，其热膨胀系数大约为15，因此，在热循环工艺之下，不匹配的热膨胀系数所导致施加在芯片2和凸块6上的应力，会使得芯片2产生翘曲，及/或使得凸块连接失败。第三，由于使用核心层8，封装体的厚度会有所增加，其中包括BGA锡球10、封装基底4、芯片2在内的整个封装体的总厚度可达2.3mm，此种过厚的厚度并不符合未来的规格需求，因此需要一种新颖的封装结构来解决上述问题。
发明内容
为实现上述目的，提出本发明。
有鉴于此，本发明的实施例公开一种半导体封装结构，包括：基板层，其成分包括合金42材料；芯片，附着于基板层的第一侧面上；及互连线结构，位于芯片上，其中互连线结构包括插塞及连接芯片的导线。
如上所述的半导体封装结构，其还包括第二基板层，该第二基板层成分包括合金42材料，位于该第一基板层的第一侧面上，其中该芯片形成于该第二基板层的开口中。
如上所述的半导体封装结构，其还包括额外的电子元件，附着于该第一基板层的第一侧面上且连接到该互连线结构。
如上所述的半导体封装结构，其中该互连线结构包括插塞以直接连接到该芯片。
如上所述的半导体封装结构，其中该第一基板层相对于该第一侧面的第二侧面不含互连线结构。
本发明的另一实施例公开一种半导体封装结构，包括：第一基板层，其成分包括合金42材料；第二基板层，附着于第一基板层的第一侧面上；开口，位于第二基板层中；芯片，位于开口中，且附着于第一基板层的第一侧面上；第一绝缘层，位于芯片及第二基板层上；多个第一插塞，位于绝缘层中且实体性接触芯片；及互连线结构，位于第一绝缘层上，其中，互连线结构包括：第二绝缘层，多个第二插塞及导线，位于第二绝缘层中，其中至少有部分的第二插塞及导线连接到所述第一插塞；及多个球栅阵列锡球，位于互连线结构的上表面。
如上所述的半导体封装结构，其中该第二基板层成分包括合金42材料。
如上所述的半导体封装结构，其中该第一绝缘层包括ABF增层膜材料。
如上所述的半导体封装结构，其还包括额外的电子元件，附着于该第一基板层的第一侧面上，且通过第三插塞连接到该互连线结构，其中，该互连线结构和第三插塞间的连接不含凸块。
如上所述的半导体封装结构，其中该第一基板层相对于该第一侧面的第二侧面不含互连线结构。
本发明实施例的优点在于合金42材料和半导体芯片有近似的热膨胀系数，因此由封装体施加给芯片的应力可以减少。
为了让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举优选实施例，并配合所附附图，作详细说明如下。
附图说明
图1显示传统的封装体，其中互连线层形成于核心层的两侧。
图2至图10显示本发明优选实施例的制造过程剖面图。
其中，附图标记说明如下：
2  半导体芯片          6  凸块               4  封装基底
8  核心层              10 球栅阵列锡球       12 插塞
20 基板层              24 基板层             22 粘着材料
201、202 核心层        26、28 开口           30 芯片
32 电子元件            34 绝缘层             38 开口
40 接触垫              42 开口               44 插塞
46 籽晶层              48 干膜               50 导电图案
52 绝缘层              60 凸块接点           62 防焊护膜
64 球栅阵列锡球        P  间距
具体实施方式
有关各实施例的制造和使用方式为如下所详述的。然而，值得注意的是，本发明所提供的各种可应用的发明概念依具体内容的各种变化据以实施，且在此所讨论的具体实施例仅是用来显示具体使用和制造本发明的方法，而不是用于限定本发明的范围。
本实施例提供一种新颖的封装结构及其形成方法，其制造过程显示于图2至图10。此外，在本发明的各种实施例和附图中，相同符号用以指示相同或类似元件。
图2显示起始制造工艺的结构，其包括基板层20，基板层24以及粘着材料22。在实施例中，基板层20的成分包括含有合金42材料(alloy 42)的核心层201，此材料为镍铁合金，在以下段落中会予以详述。此外，两核心层202的成分包含有铜材料，其可电镀在核心层201的两侧，同样地，基板层24包括含有合金42材料(alloy 42)的核心层241，此外，两核心层242包含有铜材料，其可电镀在核心层241的两侧。
合金42材料大约包括42％的重量百分比的镍以及58％的重量百分比的铁，而编号42指镍所占的百分比。合金42材料的弹性系数约为每平方英寸(PSI)20.7E6磅，热膨胀系数(CTE)约为4.0E-06/K至4.7E-06/K，导热率约为16W/mk，以及电阻率值约为70μΩ·cm。基板层20的厚度大体可为4密尔(mil)，同时，基板层24的厚度大体可为12密尔(mil)。基板层20和基板层24不仅可以对后续工艺所附着的芯片提供保护，也可以提供结构性的支撑。基板层20和基板层24可以随着层压(laminating press)的方式而通过粘着材料22黏接，例如是半固化片(prepreg；preimpregnated fibres)。虽然，基板层20和基板层24可视为合金42材料，然而，其也允许有稍微不同的组成，但必须和合金42材料有相同的热膨胀系数。
请参考图3，开口26和28通过除去部分的基板层24和粘着材料22而形成，开口26设定用于放置芯片，因此开口26的大小取决于芯片的尺寸。开口28则可选择性的形成以放置可整合到封装体的电子元件，例如电容或电阻等被动元件。在另一实施例中，开口26和28也可以在贴附基板层24至基板层20之前预先形成。
在图4中，芯片30被放置在开口26内且附着于基板层20上，优选的做法是以例如银浆作为粘着材料。电子元件32也可被放置在开口28内且附着于基板层20上。
请参考图5，绝缘层34被形成在先前的结构上，绝缘层34包括有机材料，例如日本Ajinomoto公司所供应的增层膜材料(ABF；Ajinomoto buildupfilm)，然而，其他一般材料例如半固化片(prepreg)或是背胶铜箔(RCC；resincoated copper)亦可使用，在本例中，绝缘层34是以ABF材料形成，此ABF材料可被层压在图4的结构上，热和压力可以施加在此层上而软化以形成平坦的上表面。此热和压力也可以协助绝缘层34填入芯片30(或是电子元件32)和基板层24间的空间，结果，在芯片30的上表面和绝缘层34的上表面间的厚度T1优选为大约25μm至35μm，最优选则约为30μm。
随后形成开口38以暴露出在芯片30上表面的接触垫40(也称为凸块底金属层(under bump metallurgy)；或简称UBM)。优选地，开口38通过激光钻孔形成，其中覆盖UBM 40的绝缘层34被予以烧除。此外，也可形成开口42以暴露出在电子元件32上表面的接触垫(未显示)。
图6显示通过选择性填充导电材料至开口38和42以形成插塞44(by-vias)的方式。此导电材料可以是一般常用的材料，例如在实施例中，此导电材料包括铜或铜合金，然而，其他如银或铝亦可使用。此填充方法包括无电镀或电镀工艺，插塞44直接连接UBM 40以及在后续步骤形成于插塞44上的互连线结构，因此凸块(solder bumps)是不需要的。此外，插塞44也连接互连线结构和电子元件32，优选地，插塞44的上表面实质上和绝缘层34的上表面等高，或者，插塞44的上表面稍微低于绝缘层34的上表面。
请参考图7，薄的籽晶层46，优选者包括铜材料，可形成于绝缘层34和插塞44的表面上，其中，无电镀工艺是优选的实施方法，此薄的籽晶层46的优选厚度约为小于0.8μm。干膜(dry film)48接着形成于籽晶层46上，随后进行图案化工艺以形成开口，以由后续形成的金属线填入其中。干膜48的厚度优选值是依据后续所形成的导线的厚度来决定，例如在实施例中，干膜48的厚度T2是介于约20μm和25μm之间，更优选是约20μm。
请参阅图8，导电图案50形成在籽晶层46中未被干膜48覆盖的部分上，其可包括导线和导电垫，形成方式例如为选择性电镀法。导电图案50的优选形成厚度是实质接近干膜48的厚度，导电图案50的优选材料是铜或铜合金，然而，其他一般常用金属材料例如银、铝、及镍等亦可使用。导电图案50的上表面优选为实质上和干膜48的上表面等高，或者，导电图案50的上表面亦可稍微低于干膜48的上表面。在形成导电图案50之后，干膜48和籽晶层46中位于干膜48之下的部分被一并去除，例如在实施例中，干膜48可以碱性溶液去除，而籽晶层46中位于干膜48之下的部分则可以快速蚀刻工艺(flash etching)去除。由于侧面效应(side effect)的关系，在快速蚀刻工艺中，导电图案50也会被去除掉薄层。
请参考图9，接着坦覆式形成绝缘层52，其可选择使用和绝缘层34实质相同的方法和实质相同的材料形成。从导电图案50的上表面到绝缘层52的上表面的厚度T3优选者为逼近厚度T1，例如是大约30μm。
接续工艺则是形成更多的互连线层，包括插塞和导电图案，其最终结构显示于图10中。对每一互连线层而言，其工艺步骤可以和插塞44及导电图案50的形成方法实质相同，优选地，可以形成3到5层的互连线层(包括由插塞44和导电图案50构成的互连线层)，其中每一个互连线层包括一层导电图案及其下方的插塞。
在替代实施例中，其他已知的方法，例如嵌工艺亦可用于形成互连线层，一般而言，嵌工艺包括如下步：首先形成绝层，然后形成开口于绝层中，再以铜或铜合金等导电材料填入开口，执行化学机械研磨工艺以去除多余的导电材料，而此导电材料的剩余部分则形成插塞和导电图案。
请再参考图10，凸块接点(bump pads)60也可形成于上层的互连线层中。接着形成防焊护膜62(solder mask；也称作阻焊剂：solder resist)，其厚度可为20μm，之后形成阻焊剂开口(SRO：solder resist opening)以暴底下的凸块接点60，球栅阵列锡球(BGA balls)64随后则形成于凸块接点60上。而有关凸块接点60、防焊护膜62、和球栅阵列锡球64由于是现有技术，因此在此不予详述。具有嵌合的芯片的封装基底则随之通过球栅阵列锡球64附着在主机板上。
使用合金42作为基板层的优点是其具有介于4.0E-06/K至4.7E-06/K的热膨胀系数，因此可和芯片的热膨胀系数(介于2.3E-06/K至4.2E-06/K)良好匹配。在热循环(thermal cycle)工艺时，通过基板层20和24施加给芯片的应力因此可减到最小，相比之下，传统的核心层材料一般包括双马来亚酰胺-三氮杂苯树脂(Bismaleimide-Triazine；BT)，其热膨胀系数为15E-06/K，因此高应力会被施加到具有BT树脂核心层的封装基底的芯片上。仿真结果显示，具有传统BT树脂核心层(厚度约为100μm)的封装基底，将导致层压板(laminate)，如ABF增层膜材料 曲约125μm，而本发明的实施例则只有曲约40μm。此封装体的可靠度因此获得改善。
本发明实施例还具有其他一些优点，例如由于从封装基底中移除了核心层，电子信号经互连线层会更有效率，且互连线层的空间浪费较少。据此，互连线层的数量可以从传统封装基板的8层减少到本发明的5层甚或3层。整个封装基板的厚度也据此可减少到例如约26密尔至30密尔之间。此外，从互连线层的中间部分移除核心层可以减少封装体的电 和插入损失(insertion losses)。
本发明实施例的另一优点在于，由于插塞44直接连接芯片30，因此不需要防焊剂，芯片30的间距P(请参考图10)也可以减少。在实施例中，间距P大约是120μm，而在传统的封装体中，由于凸块被用来连接芯片和封装基底，所以最小的间距至少也要140μm。
虽然本发明已以优选实施例公开如上，然其并非用以限定本发明，本领域技术人员，在不脱离本发明的精神和范围内，当可作些许的变更与修饰，因此本发明的保护范围当视所附的权利要求书所界定的范围为准。

Claims (10)

1.一种半导体封装结构，包括：
第一基板层，其成分包括合金42材料；
芯片，附着于该第一基板层的第一侧面上；及
互连线结构，位于该芯片上，其中该互连线结构包括插塞及连接该芯片的导线。
2.如权利要求1所述的半导体封装结构，其还包括第二基板层，该第二基板层成分包括合金42材料，位于该第一基板层的第一侧面上，其中该芯片形成于该第二基板层的开口中。
3.如权利要求1所述的半导体封装结构，其还包括额外的电子元件，附着于该第一基板层的第一侧面上且连接到该互连线结构。
4.如权利要求1所述的半导体封装结构，其中该互连线结构包括插塞以直接连接到该芯片。
5.如权利要求1所述的半导体封装结构，其中该第一基板层相对于该第一侧面的第二侧面不含互连线结构。
6.一种半导体封装结构，包括：
第一基板层，其成分包括合金42材料；
第二基板层，附着于该第一基板层的第一侧面上；
开口，位于该第二基板层中；
芯片，位于该开口中，且附着于该第一基板层的第一侧面上；
第一绝缘层，位于该芯片及第二基板层上；
多个第一插塞，位于该绝缘层中且实体性接触该芯片；及
互连线结构，位于该第一绝缘层上，其中，该互连线结构包括：
第二绝缘层，
多个第二插塞及导线，位于该第二绝缘层中，其中至少有部分的第二插塞及导线连接到所述第一插塞；及
多个球栅阵列锡球，位于该互连线结构的上表面。
7.如权利要求6所述的半导体封装结构，其中该第二基板层成分包括合金42材料。
8.如权利要求6所述的半导体封装结构，其中该第一绝缘层包括增层膜材料。
9.如权利要求6所述的半导体封装结构，其还包括额外的电子元件，附着于该第一基板层的第一侧面上，且通过第三插塞连接到该互连线结构，其中，该互连线结构和第三插塞间的连接不含凸块。
10.如权利要求6所述的半导体封装结构，其中该第一基板层相对于该第一侧面的第二侧面不含互连线结构。
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