TWI405306B - 半導體封裝件、其製造方法及重佈晶片封膠體 - Google Patents

半導體封裝件、其製造方法及重佈晶片封膠體 Download PDF

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TWI405306B
TWI405306B TW098124858A TW98124858A TWI405306B TW I405306 B TWI405306 B TW I405306B TW 098124858 A TW098124858 A TW 098124858A TW 98124858 A TW98124858 A TW 98124858A TW I405306 B TWI405306 B TW I405306B
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dielectric layer
wafer
layer
active surface
encapsulant
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TW098124858A
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TW201104803A (en
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Hung Jen Yang
Chueh An Hsieh
Min Lung Huang
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Advanced Semiconductor Eng
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Description

半導體封裝件、其製造方法及重佈晶片封膠體
本發明是有關於一種半導體封裝件、其製造方法及重佈晶片封膠體，且特別是有關於一種具有對位結構的半導體封裝件、其製造方法及重佈晶片封膠體。
近年來電子裝置蓬勃的應用於日常生活中，業界無不致力發展微型且多功能之電子產品，以符合市場需求。
有別於傳統以單一晶片(die)為加工標的的封裝技術，重佈晶片之封膠體級封裝(Chip-redistribution Encapsulant Level Package)是以整片重佈晶片封膠體(Chip-redistribution Encapsulant)作為封裝處理的對象。換言之，相較於傳統之單一晶片封裝，重佈晶片封膠體級封裝是在尚未將個別的晶粒分離之前就對重佈晶片封膠體上之晶粒進行封裝。如此，將簡化晶片封裝之後段製程，同時可節省了封裝製程時間及成本。也就是說，在重佈晶片封膠體表面之元件、線路及其相關之前段製程完成後，即可直接對整片重佈晶片封膠體進行後段製程，接著再進行重佈晶片封膠體切割(saw)的步驟，以形成多個半導體封裝件。因此，重佈晶片之封膠體級封裝已然成為半導體封裝之趨勢。
在製作重佈晶片封膠體時，是將晶圓上的數個晶片切割下來，然後重新佈置在一載板上。該些晶片中包括數個具有電路功能的晶片及對位晶片(alignment die)。在後續的曝光製程中，曝光機台依據重佈晶片封膠體上對位晶片的對位標記將光罩定位於一曝光位置，以進行曝光製程，例如是形成第一介電層、圖案化導電層及第二介電層等結構的曝光製程。
然而，由於載板上的晶片是經過重新排列過，排列後的晶片會產生排列偏差。而光罩本身也會產生對位偏差，二者的堆疊偏差可達+/-10μm ，導致製作出來的圖案，例如是第一介電層、圖案化導電層及第二介電層的圖案產生嚴重的偏位。
因此，如何提升光罩與載體上晶片的對位精度，以符合在半導體封裝件的尺寸日益縮小的趨勢，實為本產業努力目標。
本發明係有關於一種半導體封裝件、其製造方法及重佈晶片封膠體。晶片在重佈於載板之後，於形成其中一層結構時，同時形成下一層結構所需的對位結構，以利光罩與重佈後的晶片進行精準地對位，製作出更精確的圖案。
根據本發明之第一方面，提出一種半導體封裝件。半導體封裝件至少包括一晶片、一封膠、一第一介電層、一圖案化導電層、至少一對位結構及一第二介電層。晶片具有一主動表面並包括數個接墊。接墊設於主動表面。封膠包覆於晶片之側壁，以暴露出主動表面。第一介電層形成於封膠及主動表面之上方，第一介電層具有數個第一開孔，第一開孔暴露出接墊。圖案化導電層形成於接墊之一部份及第一介電層。對位結構形成於第一介電層或圖案化導電層，對位結構重疊於封膠與主動表面中至少一者。第二介電層，形成於圖案化導電層之一部份。
根據本發明之第二方面，提出一種重佈晶片封膠體。重佈晶片封膠體至少包括數個晶片、一封膠、一第一介電層、一圖案化導電層、一第二介電層及數個對位結構。晶片包括一接墊並具有一主動表面，接墊設於主動表面。封膠包覆於晶片的側壁，以暴露出主動表面，封膠具有一封膠表面及至少一切割道，切割道位於相鄰之晶片之間。第一介電層形成於封膠表面及主動表面之上方，第一介電層具有數個第一開孔，第一開孔暴露出接墊。圖案化導電層形成於接墊之一部份及第一介電層。對位結構形成於第一介電層或圖案化導電層。對位結構重疊於封膠表面、主動表面與切割道中至少一者。第二介電層形成於圖案化導電層之一部份。
根據本發明之第三方面，提出一種半導體封裝件之製造方法。半導體封裝件之製造方法包括以下步驟。提供一具有一黏貼層的載板；重佈數個晶片於黏貼層上，晶片包括一接墊並具有一主動表面，接墊設於主動表面，主動表面面向黏貼層；以一封膠，包覆於晶片之側壁，使封膠及晶片形成一重佈晶片封膠體；移除載板及黏貼層，使重佈晶片封膠體暴露出晶片的主動表面；形成一第一介電層於封膠及主動表面之上方，第一介電層具有數個第一開孔，第一開孔暴露出接墊；形成一圖案化導電層於接墊之一部份及第一介電層；形成數個對位結構於第一介電層或圖案化導電層，對位結構重疊於封膠與主動表面中至少一者；形成一第二介電層於圖案化導電層之一部份，第二介電層具有數個第二開孔，第二開孔暴露出圖案化導電層之另一部份；形成數個銲球於該些第二開孔，以使銲球與圖案化導電層電性連接；以及，切割重佈晶片封膠體成為數個半導體封裝件。
為讓本發明之上述內容能更明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下：
以下係提出較佳實施例作為本發明之說明，然而實施例所提出的內容，僅為舉例說明之用，而繪製之圖式係為配合說明，並非作為限縮本發明保護範圍之用。再者，實施例之圖示亦省略不必要之元件，以利清楚顯示本發明之技術特點。
第一實施例
請參照第1圖，其繪示依照本發明第一實施例之半導體封裝件之示意圖。半導體封裝件100包括一晶片102、一封膠104、一第一介電層106、一圖案化導電層108、數個對位結構110、一第二介電層112及數個銲球114。
晶片102包括數個接墊116及一保護層124並具有一主動表面118。接墊116及保護層124皆設於主動表面118，接墊116從保護層124的保護層開孔(未標示)暴露出來。
第一介電層106形成於封膠104之一封膠表面126及主動表面118上方的保護層124。第一介電層106並具有數個第一開孔128，第一開孔128暴露出接墊116。
圖案化導電層108形成於接墊116之一部份及第一介電層106上。
封膠104包覆晶片102之側壁120及底面122，以暴露出主動表面118。銲球114透過圖案化導電層108與晶片102上的接墊116電性連接。部份數量的銲球114延伸至與封膠表面126重疊，可增加半導體封裝件100的輸出/輸入接點的數目。
第二介電層112則形成於圖案化導電層108之一部份。
於本實施例中，數個對位結構110形成於第一介電層106，並同時與封膠表面126及主動表面118重疊。然此非用以限制本發明，在其它實施態樣中，全部的對位結構110可與封膠表面126及主動表面118中其中一者重疊。或者，對位結構110的數量可以是一個，重疊於封膠表面126或主動表面118。或者，對位結構110的數量可以是二個以上，重疊於封膠表面126與主動表面118中至少一者。
對位結構110可提供用以形成圖案化導電層108的光罩對位之用，並可提升圖案化導電層108的尺寸精度。將於以下說明半導體封裝件的製造方法過程中說明對位結構110的形成過程及優點。
請參照第2圖，其繪示依照本發明第一實施例之半導體封裝件之製造方法流程圖。請同時參照第3A至3I圖，其繪示第1圖之半導體封裝件之製造示意圖。
然後，在步驟S202中，如第3A圖所示，提供一具有黏貼層130的載板132。
然後，在步驟S204中，如第3B圖所示，重佈數個晶片102於黏貼層130上。晶片102包括接墊116及保護層124(接墊116及保護層124未繪示於第3B圖)並具有主動表面118。接墊116設於主動表面118，主動表面118面向黏貼層130。此外，更重佈二對位晶片(未繪示)於黏貼層130上。
然後，在步驟S206中，如第3C圖所示，以封膠104包覆於晶片102的側壁120及底面122，使封膠104及晶片102形成一重佈晶片封膠體134。其中，封膠104具有一封膠表面126及一切割道136，切割道136位於相鄰之晶片102之間。而封膠表面126圍繞晶片102並位於切割道136與晶片102之間。
然後，如第3D圖所示，在步驟S208中，移除載板132及黏貼層130，使重佈晶片封膠體134暴露出晶片102的主動表面118。
第3D圖所示之主動表面118係朝下。然，透過倒置(invert)重佈晶片封膠體134的動作，可使主動表面118朝上，如第3E圖所示。
然後，在步驟S210中，如第3E圖所示，光罩對準曝光機(aligner)(未繪示)依據步驟S204中之該二對位晶片上的對位標記，將光罩定位於一曝光位置，以形成第一介電層106於封膠表面126及主動表面118上方的保護層124上。於本步驟S210中，可形成數個第一開孔128於第一介電層106上，以暴露出接墊116。
於本步驟S210中，在形成第一介電層106的同時亦形成對位結構110。也就是說，對位結構110與第一介電層106可於同一道曝光製程完成。因此，不須新增其它製程設備即可形成對位結構110，相當節省製程成本及製程時間。
對位結構110可與封膠表面126、主動表面118及切割道136中至少一者重疊。例如，全部的對位結構110可與封膠表面126、主動表面118及切割道136中其中一者重疊。或者，請參照第4圖，其繪示本發明另一實施例之形成有對位結構之重佈晶片封膠體的上視圖。該另一實施例中，對位結構110可以同時與封膠表面126、主動表面118及切割道136重疊。或者，在其它實施態樣中，對位結構110可與封膠表面126、主動表面118及切割道136中其中二者重疊。由上述可知，對位結構110的設置位置具有多種形式，只要能夠讓光罩進行對位，本發明之對位結構110的設置位置不受上述實施例所限制。
對位結構110是在晶片重佈後所形成，因此不會產生習知技藝中因晶片重佈而產生的排列偏差。並且，步驟S210中的對位結構110係利用光罩對準曝光機所形成，其精度可達+/-5μm 。因此，使後續製程中的光罩利用對位結構110所製作出的圖案尺寸係相當精確。
數個對位結構110可提供給用以形成下一道結構，例如是圖案化導電層108(繪示於第3F圖)的光罩定位之用。圖案化導電層108可使用例如是步進機(stepper)(未繪示)的曝光機台來進行光罩的定位。較佳但非限定地，對位結構110的數目至少五個，可增加步進機進行光罩對位的精確度。然，對位結構110的數目可視曝光機台的要求而定，不受本發明實施例所限制。
以下係介紹對位結構110的外型。請參照第3E圖中局部A及局部B之上視圖的放大示意圖。與主動表面118、封膠表面126及切割道136重疊的對位結構110(1)、110(2)及110(3)可包括四個凹槽138，該些凹槽138可依據一矩形的四個角排列。然此非用以限制本發明，請參照第5圖，其繪示依照本發明另一實施例之對位結構示意圖。該另一實施例中，與主動表面118、封膠表面126及切割道136重疊的對位結構可包括四個柱體140，該些柱體140可依據一矩形的四個角排列。
此外，請回到第3E圖，由於凹槽138貫穿第一介電層106，故可暴露出第一介電層106下方的結構，例如是封膠104及保護層124。
雖然本實施例的對位結構110的排列外型以第3E圖所繪示的外型為例作說明。然於其它實施態樣中，對位結構110的排列外型也可以是其它外型，只要能夠讓光罩順利對位的排列外型即可，對位結構110的的排列外型並不受本實施例所限制。
此外，雖然本實施例之對位結構110的數目以四個為例作說明，然於其它實施態樣中，對位結構110的數目可少於四個或多於四個。另，雖然本實施例之對位結構110的剖面形狀以八邊形為例作說明，然於其它實施態樣中，對位結構110的剖面形狀可以是任意外形，例如是矩形、圓形或三角形等。進一步地說，只要能夠讓光罩進行對位，本發明的對位結構110可以是柱體或凹槽且其剖面外形可以是任意形狀，而其數量亦不受上述實施例所限制。
然後，在步驟S212中，如第3F圖所示，形成圖案化導電層108於接墊116之一部份及第一介電層106。
在本步驟S212中，步進機依據該些對位結構110，將光罩定位在一曝光位置，以進行形成圖案化導電層108的曝光製程。
本實施例中，晶片於重佈後才形成對位結構110，因此不會產生習知技藝中因晶片重佈所產生的排列偏差。如此一來，在本步驟S212中，光罩依據晶片重佈後才形成的對位結構110來進行對位，使得第一介電層106之後所形成的結構，例如是圖案化導電層108及第二介電層112的尺寸相當精密。也就是說，本發明實施例可製作出更細的線寬及更小的線距的圖案化導電層108，使半導體封裝件100的尺寸縮小。
然後，在步驟S214中，如第3G圖所示，形成第二介電層112於圖案化導電層108之一部份。第二介電層112具有數個第二開孔142，第二開孔142暴露出圖案化導電層108之另一部份。
於本步驟S214中，可使用步進機，依據對位結構110將光罩定位在一曝光位置，以進行形成第二介電層112的曝光製程。當然，也可以使用光罩對準曝光機，依據對位晶片上的對位標記將光罩定位在一曝光位置，以進行形成第二介電層112的曝光製程。視對圖案尺寸的精度需求而定，可自由選擇利用對位結構110或對位晶片上的對位標記來定位光罩。
此外，由於第二介電層112之至少一部份填入凹槽138內，故第二介電層112的上表面具有一略微凹陷的凹陷區144，如第3G圖中局部C的放大示意圖所示。此外，若對位結構110為第5圖所示的柱體140，則第二介電層112之至少一部份填入的是第5圖中柱體140周圍的凹部，對應地第二介電層112的上表面亦具有相似於第3G圖之凹陷區144的凹陷結構(未繪示)。然此非用以限制本發明，當第二介電層112的厚度足夠厚時，從外觀上可能不會呈現凹陷外形。
然後，在步驟S216中，如第3H圖所示，形成數個銲球114於該些第二開孔142(繪示於第3G圖)，以使銲球114與圖案化導電層108電性連接。
然後，在步驟S218中，如第3I圖所示，沿著切割路徑P，切割形成有上述第一介電層106及第二介電層112的重佈晶片封膠體134成為數個半導體封裝件，例如是半導體封裝件100。
第二實施例
請參照第6圖，其繪示依照本發明第二實施例之半導體封裝件之示意圖。於第二實施例中，與第一實施例相同之處沿用相同標號，在此不再贅述。第二實施例之半導體封裝件200與第一實施例之半導體封裝件100不同之處在於，半導體封裝件200之對位結構202可形成於圖案化導電層204。
請參照第7圖，其繪示依照本發明第二實施例之半導體封裝件之製造方法流程圖。請同時參照第8A至8C圖，其繪示繪示第6圖之半導體封裝件之製造示意圖。
步驟S702至步驟S708為形成重佈晶片封膠體134的步驟，其與第2圖之步驟S202至步驟S208相似，在此便不再贅述。以下係從步驟S710開始說明。
在步驟S710中，如第8A圖所示，形成第一介電層206於封膠表面126及主動表面118上方的保護層124上。第一介電層206具有數個第一開孔128，以暴露出接墊116。
然後，在步驟S712中，如第8B圖所示，形成圖案化導電層204於接墊116之一部份及第一介電層206。
於本步驟S712中，可同時形成對位結構202，即對位結構202與圖案化導電層204於同一道曝光製程所形成。相似於第一實施例所揭露之對位結構110，對位結構202與封膠表面126、主動表面118及切割道136中至少一者重疊。
對位結構202的外型、數量係相似於第一實施例所揭露的對位結構110。例如，如第8B圖中局部D之放大示意圖所示，對位結構202可以是四個柱體140。然此非用以限制本發明，只要能夠讓後續製程的光罩進行對位，本實施例的對位結構202可以是柱體或凹槽且其剖面外形可以是任意形狀而其數量亦不受本實施例所限制。
由於對位結構202的形成，使得在形成下一道結構，例如是第二介電層(繪示於第8C圖)時，可使用步進機，依據數個對位結構202將光罩定位於一曝光位置。
然後，如第8C圖所示，在步驟S714中，形成第二介電層208於圖案化導電層204之一部份。第二介電層208具有數個第二開孔210，第二開孔210暴露出圖案化導電層204之另一部份。
在本步驟S714中，可使用步進機，依據該些對位結構202，將光罩定位在一曝光位置，以進行形成第二介電層208的曝光製程。
相似於第一實施例所揭露之對位結構110的優點，晶片於重佈後才形成對位結構202，因此不會產生習知技藝中因晶片重佈所產生的排列偏差。如此，在本步驟S714中，光罩依據晶片重佈後才形成的對位結構202來進行對位，使得圖案化導電層204之後所形成的結構，例如是第二介電層208的尺寸相當精密。也就是說，本發明之第二實施例中第二介電層208之第二開孔210的形成位置相當精確，可使接墊116精確地暴露出來，讓後續形成的銲球114確實地與圖案化導電層204電性連接。
接下來的步驟S716至步驟S718相似於第2圖之步驟S216至步驟S218，在此便不再贅述。
本發明上述實施例所揭露之半導體封裝件、其製造方法及重佈晶片封膠體，於晶片重佈後形成數個對位結構。曝光製程中的光罩可依據晶片重佈後才形成的對位結構來進行對位，因此不會產生習知技藝中因晶片重佈而產生的排列偏差。如此，後續形成的結構，例如是圖案化導電層及第二介電層的尺寸相當精密，可製作出更細的線寬及更小的線距的圖案化導電層，使半導體封裝件的尺寸縮小。
綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100、200．．．半導體封裝件
102．．．晶片
104．．．封膠
106、206．．．第一介電層
108、204．．．圖案化導電層
110、110(1)、110(2)、110(3)、202．．．對位結構
112、208．．．第二介電層
114．．．銲球
116．．．接墊
118．．．主動表面
120．．．側壁
122．．．底面
124．．．保護層
126．．．封膠表面
128．．．第一開孔
130．．．黏貼層
132．．．載板
134．．．重佈晶片封膠體
136．．．切割道
138．．．凹槽
140．．．柱體
142、210．．．第二開孔
144．．．凹陷區
A、B、C、D．．．局部
P．．．切割路徑
第1圖繪示依照本發明第一實施例之半導體封裝件之示意圖。
第2圖繪示依照本發明第一實施例之半導體封裝件之製造方法流程圖。
第3A至3I圖繪示第1圖之半導體封裝件之製造示意圖。
第4圖繪示本發明另一實施例之形成有對位結構之重佈晶片封膠體的上視圖。
第5圖繪示依照本發明另一實施例之對位結構示意圖。
第6圖繪示依照本發明第二實施例之半導體封裝件之示意圖。
第7圖繪示依照本發明第二實施例之半導體封裝件之製造方法流程圖。
第8A至8C圖繪示第6圖之半導體封裝件之製造示意圖。
100．．．半導體封裝件
102．．．晶片
104．．．封膠
106．．．第一介電層
108．．．圖案化導電層
110．．．對位結構
112．．．第二介電層
114．．．銲球
116．．．接墊
118．．．主動表面
120．．．側壁
122．．．底面
124．．．保護層
126．．．封膠表面
128．．．第一開孔

Claims (25)

  1. 一種半導體封裝件，至少包括：一晶片，具有一主動表面並包括複數個接墊，該些接墊設於該主動表面上；一封膠，係包覆於該晶片之側壁，以暴露出該主動表面；一第一介電層，形成於該封膠及該主動表面之上方，該第一介電層具有複數個第一開孔，該些第一開孔暴露出該些接墊；一圖案化導電層，形成於該接墊之一部份及該第一介電層上；至少一對位結構，形成於該第一介電層或該圖案化導電層，該至少一對位結構係重疊於該封膠與該主動表面中至少一者，該至少一對位結構至少包括一凹槽；以及一第二介電層，形成於該圖案化導電層之一部份，該第二介電層之至少一部份係填入該凹槽。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中該凹槽係貫穿該第一介電層並裸露出該封膠。
  3. 如申請專利範圍第1項所述之半導體封裝件，其中該晶片更包括：一保護層，形成於該晶片之該主動表面上，具有複數個暴露出該些接墊之保護層開孔。
  4. 如申請專利範圍第3項所述之半導體封裝件，其中該至少一對位結構至少包括一凹槽，其中該凹槽係貫 穿該第一介電層並裸露出該保護層。
  5. 如申請專利範圍第1項所述之半導體封裝件，其中該至少一對位結構至少包括四個凹槽，該些凹槽依據一矩形的四個角排列。
  6. 如申請專利範圍第1項所述之半導體封裝件，其中該至少一對位結構至少包括一柱體。
  7. 如申請專利範圍第1項所述之半導體封裝件，其中該至少一對位結構至少包括四個柱體，該些柱體依據一矩形的四個角排列。
  8. 如申請專利範圍第1項所述之半導體封裝件，其中該至少一對位結構至少包括一凹槽，該第二介電層之至少一部份係填入該凹槽，該第二介電層具有一凹陷區，該凹陷區位於該第二介電層中對應於該凹槽的上表面。
  9. 一種重佈晶片封膠體，至少包括：複數個晶片，各該些晶片分別具有一主動表面並包括複數個接墊，該些接墊設於該主動表面上；一封膠，係包覆於各該些晶片之側壁，以暴露出該些主動表面，該封膠具有一封膠表面及至少一切割道，該切割道位於相鄰之該些晶片之間；以及一第一介電層，形成於該封膠表面及該主動表面之上方，該第一介電層具有複數個第一開孔，該些第一開孔暴露出該些接墊；一圖案化導電層，形成於各該些接墊之一部份及該第一介電層上； 複數個對位結構，形成於該第一介電層或該圖案化導電層，該些對位結構係重疊於該封膠表面、該主動表面與該切割道中至少一者，該些對位結構至少包括一凹槽；以及一第二介電層，形成於該圖案化導電層之一部份，該第二介電層之至少一部份係填入該凹槽。
  10. 如申請專利範圍第9項所述之重佈晶片封膠體，其中該些對位結構的數量至少五個。
  11. 如申請專利範圍第9項所述之重佈晶片封膠體，其中該凹槽係貫穿該第一介電層並裸露出該封膠。
  12. 如申請專利範圍第9項所述之重佈晶片封膠體，其中各該些對位結構至少包括四個凹槽，該些凹槽依據一矩形的四個角排列。
  13. 如申請專利範圍第9項所述之重佈晶片封膠體，其中該晶片更包括：一保護層，形成於該晶片之該主動表面上，具有複數個暴露出該些接墊之保護層開孔。
  14. 如申請專利範圍第13項所述之重佈晶片封膠體，其中各該些對位結構至少包括一凹槽，其中該凹槽係貫穿該第一介電層並裸露出該保護層。
  15. 如申請專利範圍第9項所述之重佈晶片封膠體，其中各該些對位結構至少包括一柱體。
  16. 如申請專利範圍第9項所述之重佈晶片封膠體，其中各該些對位結構至少包括四個柱體，該些柱體依據一矩形的四個角排列。
  17. 如申請專利範圍第9項所述之重佈晶片封膠體，其中各該些對位結構至少包括一凹槽，該第二介電層之至少一部份係填入該凹槽，該第二介電層並具有一凹陷區，該凹陷區位於該第二介電層中對應於該凹槽的上表面。
  18. 一種半導體封裝件之製造方法，至少包括：提供一具有一黏貼層的載板；重佈複數個晶片於該黏貼層上，各該些晶片分別具有一主動表面並包括複數個接墊，該些接墊係設於該主動表面，各該主動表面係面向該黏貼層；以一封膠，包覆於該些晶片之側壁，使該封膠及該些晶片形成一重佈晶片封膠體；移除該載板及該黏貼層，使該重佈晶片封膠體暴露出各該些晶片之該主動表面；形成一第一介電層於該封膠及該主動表面之上方，該第一介電層具有複數個第一開孔，該些第一開孔暴露出該些接墊；形成一圖案化導電層於各該些接墊之一部份及該第一介電層上；形成複數個對位結構於該第一介電層或該圖案化導電層，其中該些對位結構係重疊於該封膠與該主動表面中至少一者，且各該些對位結構至少包括一凹槽；形成一第二介電層於該圖案化導電層之一部份，該第二介電層具有複數個第二開孔，該些第二開孔暴露出該圖案化導電層之另一部份，該第二介電層之至少一部 份係填入該凹槽；形成複數個銲球於該些第二開孔，以使該些銲球與該圖案化導電層電性連接；以及切割該重佈晶片封膠體成為複數個半導體封裝件。
  19. 如申請專利範圍第18項所述之製造方法，其中形成該些對位結構之該步驟及形成該第一介電層之該步驟係同時進行。
  20. 如申請專利範圍第18項所述之製造方法，其中形成該些對位結構之該步驟及形成該圖案化導電層之該步驟係同時進行。
  21. 如申請專利範圍第18項所述之製造方法，其中各該些對位結構的數量至少五個。
  22. 如申請專利範圍第18項所述之製造方法，其中各該些對位結構至少包括四個該凹槽，該四個凹槽依據一矩形的四個角排列。
  23. 如申請專利範圍第18項所述之製造方法，其中各該些對位結構至少包括一柱體。
  24. 如申請專利範圍第18項所述之製造方法，其中各該些對位結構至少包括至少四個柱體，該些柱體依據一矩形的四個角排列。
  25. 如申請專利範圍第18項所述之製造方法，其中各該些對位結構係利用步進機(stepper)所形成。
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