TWI606563B - 薄型晶片堆疊封裝構造及其製造方法 - Google Patents

薄型晶片堆疊封裝構造及其製造方法 Download PDF

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TWI606563B
TWI606563B TW105137133A TW105137133A TWI606563B TW I606563 B TWI606563 B TW I606563B TW 105137133 A TW105137133 A TW 105137133A TW 105137133 A TW105137133 A TW 105137133A TW I606563 B TWI606563 B TW I606563B
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wafer
package structure
stack package
layer
bonding
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TW105137133A
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TW201737442A (zh
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林俊德
林基正
朱哲民
黄建文
方立志
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力成科技股份有限公司
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Priority to US15/455,149 priority Critical patent/US20170287870A1/en
Publication of TW201737442A publication Critical patent/TW201737442A/zh
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Publication of TWI606563B publication Critical patent/TWI606563B/zh
Priority to US16/780,921 priority patent/US10950557B2/en

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Description

薄型晶片堆疊封裝構造及其製造方法
本發明係有關於半導體晶片封裝領域，特別係有關於一種薄型晶片堆疊封裝構造及其製造方法。
在先進的半導體晶片封裝產品發展路徑中，縮減整體構裝厚度與尺寸是必要且不可避免的。同時，也希望具備較低製造成本之構裝設計。在早期的半導體晶片封裝構造中，基板為必要元件，用以承載各式晶片。例如，習知ExPBA構裝設計的快閃記載體晶片與控制器晶片是並排地(side by side)黏貼於基板上表面，利用打線技術(wire bond)電性連接晶片至基板，最後在基板上表面上形成一模封膠體，以保護晶片；經過單體切割之後可製作完成構裝製造。然而，以目前架構下的之產品規格在其厚度與面積方面恐無法符合下一代未來產品的輕、薄、小面積之需求。
模封貫孔之形成方法係為鑽孔(drilling)，然而晶片接合墊之間距太小，在孔施作上極有可能造成模封貫孔之孔形破壞與孔連接。並且，依照晶片堆疊高度之不同，晶片接合墊至模封膠體表面的垂直距離亦為或長或短呈現不同，在模封貫孔之形成過程中，也需要有對應且準確的孔深度作配合，故晶片接合墊容 易遭受到損害。
為了解決上述之問題，本發明之主要目的係在於提供一種薄型晶片堆疊封裝構造及其製造方法，可以省略基板結構並準確地電性連接重配置線路層與晶片接合墊，具有整體封裝厚度減薄、降低模封貫孔形成對晶片的損害與一次模封多晶片之功效。
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種薄型晶片堆疊封裝構造，包含至少一第一晶片、複數個鑽孔停止件、一封膠體、一重配置線路層以及一保護層。該第一晶片係具有一第一主動面與一第一背面，該第一主動面上係設置有複數個第一接合墊。該些鑽孔停止件係形成於對應之該些第一接合墊上。該封膠體係密封該第一晶片，該封膠體係具有一接合表面以及複數個導通孔，該些導通孔係連通該接合表面至對應之該些鑽孔停止件，並且該些導通孔內係填充有導電物質，以形成複數個第一金屬柱。該重配置線路層係形成於該封膠體之該接合表面上，並且該重配置線路層之線路係電性耦合至該些第一金屬柱，以電性連接至該第一晶片。該保護層係覆蓋該重配置線路層，該保護層係具有複數個凹陷區，以局部顯露該重配置線路層。本發明另揭示上述薄型晶片堆疊封裝構造之製造方法。
本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。
在前述薄型晶片堆疊封裝構造中，每一鑽孔停止件係包含一柱型凸塊，該些鑽孔停止件之單位表面面積係大於該些第一接合墊之單位表面面積。
在前述薄型晶片堆疊封裝構造中，係可另包含複數個銲球，係可經由該保護層之該些凹陷區電性耦合至該重配置線路層。
在前述薄型晶片堆疊封裝構造中，係可另包含一遮蔽層，係可至少覆蓋該封膠體之複數個側面，該些側面係可圍繞在該接合表面之周邊。
在前述薄型晶片堆疊封裝構造中，係可另包含一第二晶片，係可設置於該第一晶片上，該第二晶片係可具有一第二主動面與一第二背面，該第二主動面上係可設置有複數個第二接合墊，該重配置線路層之線路係可更電性耦合至該些第二接合墊。
在前述薄型晶片堆疊封裝構造中，該第一晶片係可為複數個並為階梯式錯位堆疊而形成一扇出結構，以不遮蓋該些第一接合墊。
在前述薄型晶片堆疊封裝構造中，係可另包含至少一晶片貼附膜層，係可形成於該些第一晶片之間。
在前述薄型晶片堆疊封裝構造中，該導電物質係可不飽合填充於該些導通孔內，以使該些第一間隔體內具有空腔。
藉由上述的技術手段，本發明在一具體結構中可以省略基板構件，藉此約可降低30%之製造生產成本。再者，能夠縮減構裝厚度，因無基板與打線構件，故在整體構裝厚度可減薄超過50%。此外，當鑽孔停止件包含金屬柱型凸塊(stud bump)，可設置於例如快閃記憶體(Flash)之第一晶片上，柱型凸塊具有不同於晶片接合墊之金屬材質且接合於接合墊上，可作為鑽孔停止層(Stop layer)，防止鑽孔過程中造成金屬墊片的破壞，進而影響電性性能。
本發明之薄型晶片堆疊封裝構造中，該些晶片係為立體堆疊，在晶片堆疊之後，使用模封(molding)材料作為晶片保護之用途，在鑽孔與形成重配置線路層之前，密封複數個晶片只需要單次的模封(molding)製程，以達到降低封裝成本之目的。並且，因為晶片與重配置線路層之間的連接路徑縮短，具有提升電性訊號性能(performance)與低耗電之功效，更可以利用面板等級封裝製程(panel level packaging process)對該薄型晶片堆疊封裝構造進行製造生產，可降低製造生產成本。
10‧‧‧暫時載板
20‧‧‧切割膠帶
100‧‧‧薄型晶片堆疊封裝構造
110‧‧‧第一晶片
111‧‧‧第一主動面
112‧‧‧第一背面
113‧‧‧第一接合墊
114‧‧‧晶片貼附膜層
120‧‧‧鑽孔停止件
130‧‧‧封膠體
131‧‧‧接合表面
132‧‧‧導通孔
140‧‧‧第一金屬柱
141‧‧‧空腔
140A‧‧‧第二金屬柱
150‧‧‧重配置線路層
160‧‧‧保護層
161‧‧‧凹陷區
170‧‧‧銲球
180‧‧‧遮蔽層
190‧‧‧第二晶片
191‧‧‧第二主動面
192‧‧‧第二背面
193‧‧‧第二接合墊
第1圖：依據本發明之一具體實施例，一種薄型晶片堆疊封裝構造之截面與局部放大示意圖。
第2A至2L圖：依據本發明之一具體實施例，繪示該薄型晶片堆疊封裝構造之製造方法中之主要步驟之元件截面示意圖。
以下將配合所附圖示詳細說明本發明之實施例，然應注意的是，該些圖示均為簡化之示意圖，僅以示意方法來說明本發明之基本架構或實施方法，故僅顯示與本案有關之元件與組合關係，圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理，以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計，詳細之元件佈局可能更為複雜。
依據本發明之一具體實施例，一種薄型晶片堆疊封裝構造100舉例說明於第1圖之截面示意圖。該薄型晶片堆疊封裝構造100係包含至少一第一晶片110、複數個鑽孔停止件120、一封膠體130、一重配置線路層150以及一保護層160。
請參閱第1圖，該第一晶片110係具有一第一主動面111與一第一背面112，該第一主動面111上係設置有複數個第一接合墊113。其中，主動面係為晶片內積體電路之形成表面，接合墊係為積體電路之連接端點。在本實施例中，該第一晶片110係可為複數個並為階梯式錯位堆疊而形成一扇出晶片堆疊結構，以不遮蓋該些第一接合墊113。該第一晶片110係具體可為快閃記憶體晶片。利用黏接在晶片之間的一晶片貼附膜層114，兩個或兩個以上的該第一晶片110係可在模封之前堆疊組合一起。換言之，該薄型晶片堆疊封裝構造100係可另包含至少一晶片貼附膜層114，係可形成於該些第一晶片110之間，以達成晶片堆疊的 組合。當該第一晶片110的數量為兩個且晶片尺寸相同時，複數個第一晶片110的堆疊方式可為階梯狀堆疊、十字狀堆疊或L形堆疊；當該第一晶片110的數量為兩個以上且晶片尺寸相同時，複數個第一晶片110的堆疊方式可為階梯狀堆疊。
再請參閱第1圖，該些鑽孔停止件120係形成於對應之該些第一接合墊113上，並且該些鑽孔停止件120之單位表面面積係大於該些第一接合墊113之單位表面面積，每一鑽孔停止件120係包含一柱型凸塊(stud bump)。該些鑽孔停止件120係用以在鑽孔形成模封貫孔時防止對該些第一接合墊113的損害。而柱型凸塊的形成方法可以是打線接合，例如金線球端之打線形成；也可以是電鍍，例如銅柱電鍍。該些鑽孔停止件120之材質應包含導電金屬，並且該些鑽孔停止件120係應突出於對應之該第一主動面111上。具體地，該些鑽孔停止件120係覆蓋對應之該些第一接合墊113。即使在鑽孔作業中，該些鑽孔停止件120的局部移除也不會影響該些第一接合墊113之電性功能。
請參閱第1圖，該封膠體130係密封該第一晶片110，該封膠體130係具有一接合表面131以及複數個導通孔132，該些導通孔132係連通該接合表面131至對應之該些鑽孔停止件120，並且該些導通孔132內係填充有導電物質，以形成複數個第一間隔體140。該封膠體130係可利用模封方式形成，其係具有電絕緣性與熱固化特性，以密封並保護該第一晶片110。該封膠體130之厚度應大於該第一晶片110之晶片厚度或是大於包含該第 一晶片110之晶片堆疊厚度。該些第一金屬柱140係介設於該些鑽孔停止件120與該重配置線路層150之接合端之間。上述之導電物質係可不飽合填充於該些導通孔132內，以使每一之該些第一金屬柱140內各具有至少一空腔141，可用以增強該些第一間隔體140在孔內防止金屬斷裂之能力。該空腔141內係可存在有空氣。
再請參閱第1圖，該重配置線路層150係形成於該封膠體130之該接合表面131上，並且該重配置線路層150之線路係電性耦合至該些第一間隔體140，以電性連接至該第一晶片110。該重配置線路層150係為利用積體電路製程所形成之線路，在該重配置線路層150之底層係可包含一電鍍晶種層(seed layer)。此外，該重配置線路層150之線路結構係可省略習知基板結構的電鍍連接線。該重配置線路層150之線路厚度係可控制在不大於10微米。
請參閱第1圖，該保護層160係形成於該封膠體130之該接合表面131上並覆蓋該重配置線路層150，該保護層160係具有複數個凹陷區161，以局部顯露該重配置線路層150。更具體地，該薄型晶片堆疊封裝構造100係可另包含複數個銲球170，係可經由該保護層160之該些凹陷區161電性耦合至該重配置線路層150。該保護層160係不填入或微量填入至該些導通孔132內，以維持該些第一間隔體140之空腔結構。該保護層160之材質係為電絕緣的有機物質，例如聚亞醯胺(polyimide)。
此外，該薄型晶片堆疊封裝構造100係可另包含一遮蔽層180，係可至少覆蓋該封膠體130之複數個側面，該些側面係 可圍繞在該接合表面131之周邊。具體地，該遮蔽層180之材質係包含具有電磁干擾防護功能之遮蔽金屬。
在本實施例中，該薄型晶片堆疊封裝構造100係可另包含一第二晶片190，係可設置於該第一晶片110上，該第二晶片190係可具有一第二主動面191與一第二背面192，該第二主動面191上係可設置有複數個第二接合墊193。該第二晶片190係可為一控制器晶片。該封膠體130係更密封該第二晶片190。該重配置線路層150之線路係可更電性耦合至該些第二接合墊193。更具體地，複數個第二金屬柱140A係可設置於該些第二接合墊193，用以電性耦合該重配置線路層150。該封膠體130之上表面係可不與該第二晶片190之該第二主動面191在同一平面上，該封膠體130可更覆蓋於該第二晶片190之該第二主動面191。每一之該些第二金屬柱140A係可包含一柱型凸塊，其係介設於該些第二接合墊193與該重配置線路層150之間。
關於上述薄型晶片堆疊封裝構造100之製造方法係配合第2A至2L圖進一步說明如後。
請參閱第2A圖，提供至少一第一晶片110於一暫時載板10上，該第一晶片110係具有一第一主動面111與一第一背面112，該第一主動面111上係設置有複數個第一接合墊113。該暫時載板10係可為具有黏性的晶片在晶圓/面板上之承載系統，其主體材質係可為玻璃。請參閱第2B圖，在提供該第一晶片110之步驟中，該第一晶片110係為複數個並為階梯式錯位堆疊而形成一扇出 結構，以不遮蓋該些第一接合墊113。在提供該第一晶片110之步驟中，該些第一晶片110之間係形成有至少一晶片貼附膜層114。以上步驟可實施於晶圓等級，亦可實施於面板等級，其中所稱的「晶圓等級」表示該第一晶片110或是包含該第一晶片110之晶片堆疊體為複數個排列在該暫時載板10之一晶圓範圍內，再以晶圓型態進行後續構裝作業；其中所稱的「面板等級」表示該第一晶片110或是包含該第一晶片110之晶片堆疊體為複數個排列在該暫時載板10之一面板範圍內，再以面板型態進行後續構裝作業。
請參閱第2C圖，形成複數個鑽孔停止件120於對應之該些第一接合墊113上，並且該些鑽孔停止件120之單位表面面積係大於該些第一接合墊113之單位表面面積，每一鑽孔停止件120係包含一第一柱型凸塊。此外，在本步驟中，每一包含一第二柱型凸塊之複數個第二間隔體140A係可形成於該第二晶片190之該些第二接合墊193上。當該些鑽孔停止件120(或/與該些第二金屬柱140A)之形成方法係為打線形成，該些鑽孔停止件120(或/與該些第二金屬柱140A)之形成步驟係可實施於第一晶片110(或/與該第二晶片190)形成於該暫時載板10上之步驟之後。當該些鑽孔停止件120(或/與該些第二間隔體140A)之形成方法係為電鍍形成，該些鑽孔停止件120(或/與該些第二間隔體140A)之形成步驟係可實施於第一晶片110(或/與該第二晶片190)形成於該暫時載板10上之步驟之前。
請參閱第2D圖，形成一封膠體130於該暫時載板10 上，該封膠體130係密封該第一晶片110。在本實施例中，該第一晶片110為複數個，該封膠體130係密封該些複數個第一晶片110與該第二晶片190。該封膠體130之形成方式係選自於壓縮模封、轉移模封與層壓法之其中之一。該封膠體130之模封厚度係大於包含該第一晶片110與該第二晶片190之晶片堆疊高度，以覆蓋該第二晶片190之該第二主動面191。該封膠體130係具有一接合表面131，利用平坦化研磨技術，該些第二間隔體140A之上部端點係可顯露於該接合表面131。
請參閱第2E圖，形成複數個導通孔132於該封膠體130中，使得該些導通孔132係連通該封膠體130之該接合表面131至對應之該些鑽孔停止件120。該些導通孔132係以雷射鑽孔方式形成，該些鑽孔停止件120係在雷射鑽孔中被部份移除。或者，該些導通孔132亦能以深反應離子蝕刻(Deep Reactive-Ion Etching,DRIE)方式形成。
請參閱第2F圖，填充導電物質於該些導通孔132內，以形成複數個第一間隔體140。在同一製程中，形成一重配置線路層150於該封膠體130之該接合表面131上，並且該重配置線路層150之線路係電性耦合至該些第一間隔體140，以電性連接至該第一晶片110。
請參閱第2G圖，以有機沉積製程形成一保護層160於該封膠體130之該接合表面131上並覆蓋該重配置線路層150。其中，在填充該導電物質之步驟中，該導電物質係可不飽合填充於 該些導通孔132內，以使每一之該些第一間隔體140內具有一空腔141。
請參閱第2H圖，可利用曝光顯影技術，形成複數個凹陷區161於該保護層160中，以局部顯露該重配置線路層150。
請參閱第2I圖，在形成該保護層160之後，接合複數個銲球170於該封膠體130上，該些銲球170係經由該保護層160之該些凹陷區161電性耦合至該重配置線路層150。
請參閱第2J圖，移除該暫時載板10，其係先利用一切割膠帶20供該封膠體130之轉印貼附，再剝離該暫時載板10。
請參閱第2K圖，對該封膠體130實施一單體化切割步驟，以形成該封膠體130之複數個側面，該些側面係圍繞在該接合表面131之周邊。切單之後之封膠體130仍可附著於該切割膠帶20。
請參閱第2L圖，在移除該暫時載板10之後，另包含之步驟為：形成一遮蔽層180以至少覆蓋該封膠體130之複數個側面，該些側面係圍繞在該接合表面131之周邊。
本發明提供一種薄型晶片堆疊封裝構造及其製造方法，可以省略基板結構，並利用該些第一間隔體140準確地電性連接該重配置線路層150與在該些第一接合墊113上之該些鑽孔停止件120。本發明之薄型晶片堆疊封裝構造及其製造方法係具有整體封裝厚度減薄、降低模封貫孔形成對晶片的損害與一次模封多晶片之功效。
在一具體應用中，以電鍍形成之銅柱(Copper pillar) 或是打線形成之球端凸塊(Stud bump)等柱型凸塊預先形成於該第一晶片110上與該第二晶片190上，以分別構成上述之鑽孔停止件120與第二金屬柱140A。該第一晶片110與該第二晶片190係可堆疊設置於該暫時載板10所提供之一模封表面上，所形成之晶片堆疊組合係可利用該封膠體130予以密封保護，再利用鑽孔(Via formation)技術形成之該些第一間隔體140與利用重佈線(RDL)技術形成之該重配置線路層150，連接具體如快閃記憶體(Flash)之該第一晶片110與具體如控制器(controller)之該第二晶片190，以省略打線技術形成之垂直銲線，並可防止模封沖線的問題。
以上所揭露的僅為本發明實施例，不以此來限定本發明之權利範圍，因此依本發明權利要求所作的等同變化，仍屬本發明所涵蓋的範圍。
100‧‧‧薄型晶片堆疊封裝構造
110‧‧‧第一晶片
111‧‧‧第一主動面
112‧‧‧第一背面
113‧‧‧第一接合墊
114‧‧‧晶片貼附膜層
120‧‧‧鑽孔停止件
130‧‧‧封膠體
131‧‧‧接合表面
132‧‧‧導通孔
140‧‧‧第一金屬柱
141‧‧‧空腔
140A‧‧‧第二金屬柱
150‧‧‧重配置線路層
160‧‧‧保護層
161‧‧‧凹陷區
170‧‧‧銲球
180‧‧‧遮蔽層
190‧‧‧第二晶片
191‧‧‧第二主動面
192‧‧‧第二背面
193‧‧‧第二接合墊

Claims (16)

  1. 一種薄型晶片堆疊封裝構造，包含：至少一第一晶片，係具有一第一主動面與一第一背面，該第一主動面上係設置有複數個第一接合墊；複數個鑽孔停止件，係形成於對應之該些第一接合墊上，其中每一鑽孔停止件係包含一柱型凸塊，該些鑽孔停止件之單位表面面積係大於該些第一接合墊之單位表面面積；一封膠體，係密封該第一晶片，該封膠體係具有一接合表面以及複數個導通孔，該些導通孔係連通該接合表面至對應之該些鑽孔停止件，並且該些導通孔內係填充有導電物質，以形成複數個第一金屬柱；一重配置線路層，係形成於該封膠體之該接合表面上，並且該重配置線路層之線路係電性耦合至該些第一金屬柱，以電性連接至該第一晶片；以及一保護層，係覆蓋該重配置線路層，該保護層係具有複數個凹陷區，以局部顯露該重配置線路層。
  2. 如申請專利範圍第1項所述之薄型晶片堆疊封裝構造，另包含複數個銲球，係經由該保護層之該些凹陷區電性耦合至該重配置線路層。
  3. 如申請專利範圍第1項所述之薄型晶片堆疊封裝構造，另包含一遮蔽層，係至少覆蓋該封膠體之複數個側面，該些側面係圍繞在該接合表面之周邊。
  4. 如申請專利範圍第1項所述之薄型晶片堆疊封裝構造，另包 含一第二晶片，係設置於該第一晶片上，該第二晶片係具有一第二主動面與一第二背面，該第二主動面上係設置有複數個第二接合墊，該重配置線路層之線路係更電性耦合至在該些第二接合墊上之複數個第二間隔體。
  5. 如申請專利範圍第1項所述之薄型晶片堆疊封裝構造，其中該第一晶片係為複數個並為階梯式錯位堆疊而形成一扇出結構，以不遮蓋該些第一接合墊。
  6. 如申請專利範圍第5項所述之薄型晶片堆疊封裝構造，另包含至少一晶片貼附膜層，係形成於該些第一晶片之間。
  7. 如申請專利範圍第1至6項任一項所述之薄型晶片堆疊封裝構造，其中該導電物質係不飽合填充於該些導通孔內，以使該些第一金屬柱內具有空腔。
  8. 一種薄型晶片堆疊封裝構造之製造方法，包含：提供至少一第一晶片於一暫時載板上，該第一晶片係具有一第一主動面與一第一背面，該第一主動面上係設置有複數個第一接合墊；形成複數個鑽孔停止件於對應之該些第一接合墊上，並且該些鑽孔停止件之單位表面面積係大於該些第一接合墊之單位表面面積，每一鑽孔停止件係包含一柱型凸塊；形成一封膠體於該暫時載板上，該封膠體係密封該第一晶片；形成複數個導通孔於該封膠體中，使得該些導通孔係連通該封膠體之一接合表面至對應之該些鑽孔停止件； 填充導電物質於該些導通孔內，以形成複數個第一金屬柱；形成一重配置線路層於該封膠體之該接合表面上，並且該重配置線路層之線路係電性耦合至該些第一金屬柱，以電性連接至該第一晶片；形成一保護層於該封膠體之該接合表面上並覆蓋該重配置線路層；形成複數個凹陷區於該保護層中，以局部顯露該重配置線路層；以及移除該暫時載板。
  9. 如申請專利範圍第8項所述之薄型晶片堆疊封裝構造之製造方法，在形成該保護層之後，另包含：接合複數個銲球，該些銲球係經由該保護層之該些凹陷區電性耦合至該重配置線路層。
  10. 如申請專利範圍第8項所述之薄型晶片堆疊封裝構造之製造方法，在移除該暫時載板之後，另包含：形成一遮蔽層以至少覆蓋該封膠體之複數個側面，該些側面係圍繞在該接合表面之周邊。
  11. 如申請專利範圍第8項所述之薄型晶片堆疊封裝構造之製造方法，其中在提供該第一晶片之步驟中，另包含：設置一第二晶片於該第一晶片上，該第二晶片係具有一第二主動面與一第二背面，該第二主動面上係設置有複數個第二接合墊；另在形成該重配置線路層之步驟中，該重配置線路層之線路係更電性耦合至在該些第二接合墊上之複數個第二間隔體。
  12. 如申請專利範圍第8項所述之薄型晶片堆疊封裝構造之製造方法，其中在提供該第一晶片之步驟中，該第一晶片係為複數個並為階梯式錯位堆疊而形成一扇出結構，以不遮蓋該些第一接合墊。
  13. 如申請專利範圍第8項所述之薄型晶片堆疊封裝構造之製造方法，其中在提供該第一晶片之步驟中，該些第一晶片之間係形成有至少一晶片貼附膜層。
  14. 如申請專利範圍第8項所述之薄型晶片堆疊封裝構造之製造方法，其中該些導通孔係以雷射鑽孔方式形成，該些鑽孔停止件係在雷射鑽孔中被部份移除。
  15. 如申請專利範圍第8項所述之薄型晶片堆疊封裝構造之製造方法，其中該封膠體之形成方式係選自於壓縮模封、轉移模封與層壓法之其中之一。
  16. 如申請專利範圍第8至15項任一項所述之薄型晶片堆疊封裝構造之製造方法，其中在填充該導電物質之步驟中，該導電物質係不飽合填充於該些導通孔內，以使該些第一間隔體內具有空腔。
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