TWI729955B - 模組化堆疊式半導體封裝方法 - Google Patents

模組化堆疊式半導體封裝方法 Download PDF

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TWI729955B
TWI729955B TW109137337A TW109137337A TWI729955B TW I729955 B TWI729955 B TW I729955B TW 109137337 A TW109137337 A TW 109137337A TW 109137337 A TW109137337 A TW 109137337A TW I729955 B TWI729955 B TW I729955B
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layer
die
active surface
pad
redistribution
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TW109137337A
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TW202218065A (zh
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陳藝心
沈光仁
周佳仁
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力成科技股份有限公司
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Priority to TW109137337A priority Critical patent/TWI729955B/zh
Priority to CN202011442512.5A priority patent/CN114496810A/zh
Priority to US17/150,498 priority patent/US11488946B2/en
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Publication of TWI729955B publication Critical patent/TWI729955B/zh
Publication of TW202218065A publication Critical patent/TW202218065A/zh

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Abstract

本發明係一種模組化堆疊式半導體封裝方法，係提供一載板及多個相同晶片模組，於該載板上的多個元件區內分別形成一重佈線層；將該些晶片模組堆疊在該載板之各元件區的重佈線層上，並彼此電連接；於該載板上的該些重佈線層上形成一封膠層，以包覆該些晶片模組；移除該載板，使各該重佈線層的一表面外露，並於外露表面形成多個錫球；再沿著相鄰的元件區邊界切割該封膠層，以形成多個模組化堆疊式半導體元件；由於該些晶片模組均相同並且預設製成，於堆疊該些晶片模組時不因對位誤差而造成晶片模組內裸晶彼此之電連接瑕疵。

Description

模組化堆疊式半導體封裝方法
本發明係關於一種堆疊式半導體封裝方法，尤指一種模組化堆疊式半導體封裝方法。
現有堆疊式半導體封裝方法係主要預先準備好待封裝的裸晶，可於基板或第一載板上依序堆疊後一次性封膠，以單一封膠體包覆堆疊後的裸晶，構成堆疊式半導體封裝結構；亦或先在基板或第一載板上先固定第一層裸晶後即進行封膠，以第一層封膠體包覆第一層的裸晶，再於第一層封膠體上形成第一層線路層後，再於該第一層線路層上固定第二層裸晶，接著再進行封膠，以第二層封膠體包覆第二層的裸晶，如此重覆N次直到形成N層的堆疊式半導體封裝結構。
前揭二種常見的堆疊式半導體封裝方法，無論依序堆疊裸晶或依序形成多層半導體封裝體，因為該些裸晶分被分次設置在堆疊式半導體封裝結構的不同位置，容易因為對位誤差造成封裝良率降低，而有必要進一步改良之。
有鑑於堆疊式半導體封裝方法的缺點，本發明主要目的係提出一種模組化堆疊式半導體封裝方法，以克服前揭缺點。
欲達上述目的所使用的主要技術手段係令該模組化堆疊式半導體封裝方法包含以下步驟：(a)提供一第一載板及N*M個相同晶片模組；其中該第一載板具有M個元件區，各該晶片模組包含一堆疊裸晶組及一包覆該堆疊裸晶組的第一封膠體；(b)於該第一載板上的各元件區內形成一第一重佈線層；(c)將N個晶片模組堆疊在該第一載板之各元件區的第一重佈線層上，並彼此電連接；(d)於該第一載板上的該些第一重佈線層上形成一第二封膠層，以包覆該些晶片模組；(e)移除該第一載板，使各該第一重佈線層的一表面外露，並於外露表面形成多個錫球；以及(f)沿著相鄰的元件區邊界切割該第二封膠層，以形成多個N層的模組化堆疊式半導體元件。
由上述說明可知，本發明主要預先準備相同的晶片模組，各晶片模組已包含有多個相互堆疊的裸晶，以該些晶片模組進行堆疊封裝製程時，大幅減少因對位誤差而造成晶片模組內裸晶彼此之電連接瑕疵，提升堆疊多層之堆疊式半導體封裝方法的良率。
1、1a、1b:模組化堆疊式半導體元件
10:第一重佈線層
11:表面
20、20a~20d:晶片模組
21:第二重佈線組
211:第二接墊層
212:第一接墊層
22:第一封膠層
22’:第二封膠體
23:導電貫孔
231:端
30:裸晶組
30a~30d:裸晶
31a~31d:金屬接點
40:第二封膠層
40’:第二封膠體
50:第一載板
51:元件區
60:第二載板
61:模組區
圖1A至圖1K：本發明模組化堆疊式半導體封裝方法的第一實施例中不同步驟的剖面圖。
圖2A至圖2F：本發明模組化堆疊式半導體封裝方法的第二實施例中不同步驟的剖面圖。
圖3A至圖3F：本發明模組化堆疊式半導體封裝方法的第三實施例中不同步驟的剖面圖。
本發明係關於一種模組化堆疊式半導體封裝方法，以下謹以多個實施例配合圖式詳加說明之。
首先請參閱圖1A至圖1K所示，本發明模組化堆疊式半導體封裝方法的第一實施例包含以下步驟(a)至步驟(f)：
於步驟(a)中，如圖1E及圖1F所示，準備一第一載板50及N*M個相同晶片模組20；其中該第一載板50具有M個元件區51，而各該晶片模組20係主要由一第一封膠體22’包覆一堆疊裸晶組30。於本實施例，各該晶片模組20係由圖1A至圖1E所示的第一種製法所製成，誠如圖1A所示，係準備一第二載板60及多個相同的裸晶30a、30b，該第二載板60上包含有多個模組區61，各該模組區61內形成一第二重佈線層21，如圖1B所示，將部分裸晶30a的主動面上的金屬接點31a覆晶接合於該第二重佈線層21，將其餘裸晶30b的背面全面黏著於(即覆晶接合於)該第二重佈線層21上的該些裸晶30a的背面，其主動面的金屬接點31b則朝向遠離該第二重佈線層21，堆疊的二裸晶30a、30b的四側邊齊平； 如圖1C所示，於該些第二重佈線層21上形成一第一封膠層22，以包覆該些裸晶30a、30b；如圖1D所示，於各該模組區61內形成貫穿該第一封膠層22的至少一貫穿孔，於各該貫穿孔內填充金屬材質構成導電貫孔23，即各該導電貫孔係以電鍍於各該貫穿孔形成該金屬材質，研磨該第一封膠層22，使裸晶30b的主動面的金屬接點31b外露，與各該導電貫孔23的外露一端231構成各該晶片模組20的第一接墊層212；如圖1E所示，沿著相鄰模組區61邊界切割該第一封膠層22，形成多個相同晶片模組20，各該晶片模組20的第二重佈線層21外露的一表面為第二接墊層211。
於步驟(b)中，如圖1F所示，於該第一載板50上的各元件區51內形成一第一重佈線層10；於本實施例，該些第一重佈線層10係同時製成。
於步驟(c)中，如圖1F、圖1G及圖1H所示，將N個晶片模組20a~20d堆疊在該第一載板50之各元件區51的第一重佈線層10上，並彼此電連接。於本實施例中，將位在第一層的該些晶片模組20a的第一接墊層212係朝向該第一載板50，並分別與對應元件區51內的該第一重佈線層10電連接，此時位在該第一層的該些晶片模組20a的第二接墊層211係朝向遠離第一重佈線層10的方向；接著，再將同樣位在第二層的該些晶片模組20b的第一接墊層212分別朝向並電連接位在第一層的該些晶片模組20a的第二接墊層211；此時，位在第二層的該些晶片模組20b的第二接墊層211係朝向遠離第一重佈線層10的方向；接著再重覆此一步驟直到完成N層(N=4)堆疊，即將同樣位在第三層的該些晶片模組20c的第一接墊層212分別朝向並電連接位在第二層的該些晶片模組20b的第二接墊層211；此時，位在第三層的該些晶片模組20c的第二接墊層211係朝向遠離第一重佈線層10的方向；接者，將同樣位在第四層的該些晶片模組20d的第一接墊層212分別朝向並電連接位在第三層的該些晶片模組20c的第二接墊層 211；此時，位在第四層的該些晶片模組20d的第二接墊層211係朝向遠離第一重佈線層10的方向。
於步驟(d)中，如圖1I所示，於該第一載板50上的該些第一重佈線層10上形成一第二封膠層40，以包覆該些晶片模組20a~20d。
於步驟(e)中，移除該第一載板50，使各該第一重佈線層10的一表面11外露，並於外露表面11形成多個錫球12。
於步驟(f)中，如圖1I及圖1J所示，沿著相鄰的元件區51的邊界切割該第二封膠層40，以形成多個N層的模組化堆疊式半導體元件1；於本實施例，各該模組化堆疊式半導體元件1係堆疊四層晶片模組20a~20d，並以第二封膠體40’包覆；其中各該晶片模組20a~20d的堆疊裸晶組係包含二個相同裸晶30a、30b，係以背對背方式堆疊，其四側側邊齊平，如圖1E所示，其中一裸晶30b的主動面上金屬接點31b及該導電貫孔23的外露端231構成該第一接墊層212，另一裸晶30a的主動面上金屬接點31a係電連接該第二接墊層211由第二封膠體40’包覆。
請參閱圖2B至圖2F，為本發明模組化堆疊式半導體封裝方法的第二實施例，其與圖1F至圖1K所示的步驟(a)至步驟(f)大致相同，惟步驟(a)製作各該晶片模組不同，如圖2A所示，提供一第二載板60及多個裸晶30a、30b；其中該第二載板60係包含有多個模組區61；於該第二載板60的各該模組區61形成該第二重佈線層21；將部分裸晶30a的主動面上的金屬接點31a覆晶接合於該第二重佈線層21；將其餘裸晶30b的主動面部分黏著於該第二重佈線層21上的該些裸晶30a的背面，其主動面的金屬接點31b覆晶接合於該第二重佈線層21；於該些第二重佈線層21上形成一第一封膠層22，以包覆該些裸晶30a、30b；於 各該模組區61內形成貫穿該第一封膠層22的至少一貫穿孔；於各該貫穿孔內填充金屬材質構成導電貫孔23，各該導電貫孔23外露於該第一封膠層22表面的一端231係構成各該晶片模組20的第一接墊層212，另一端則電連接該第二重佈線層21；如圖2A及圖2B所示，最後沿著相鄰模組區61邊界切割該第一封膠層22，形成多個相同晶片模組20，即各該晶片模組20係主要由一第一封膠體22’包覆一堆疊裸晶組30，該第二重佈線層21外露的表面即為各該晶片模組20的第二接墊層211；於本實施例，該第二接墊層211具有一外露接墊對應該第一接墊層212的外露接墊(即該導電貫孔23的外露端231)。
當多個晶片模組20依據上述說明製作完畢後，即進行如圖2C至圖2F所示的步驟(b)至步驟(f)。
於步驟(b)中，如圖2C所示，於該第一載板50的各元件區51上形成有一第一重佈線層10；於本實施例，該些第一重佈線層10係同時製成。
於步驟(c)中，如圖2C所示，先將第一層的晶片模組20a電連接至對應的該第一重佈層10上，其第二接墊層211朝上，再依序將第二至四層的晶片模組20b~20d堆疊並電連接至前一層的第二接墊層211。
於步驟(d)中，如圖2D所示，於該第一載板50上的該些第一重佈線層10上形成一第二封膠層40，以包覆該些晶片模組20a~20d。
於步驟(e)中，如圖2D及圖2E所示，移除該第一載板50，使各該第一重佈線層10的一表面11外露，並於外露表面11形成多個錫球12。
於步驟(f)中，如圖2E及圖2F所示，沿著相鄰的元件區51邊界切割該第二封膠層40，以形成多個N層的模組化堆疊式半導體元件1a；於本實施例，各該模組化堆疊式半導體元件1a係堆疊四層晶片模組20a~20d，並以第二 封膠體40’包覆；其中如圖2B及圖2C所示，各該晶片模組20a~20d的堆疊裸晶組係包含二個相同裸晶30a、30b，係以同向錯開堆疊，使二個相同裸晶30a、30b的金屬接點31a、31b外露，並對應該第二接墊層211，該至少一導電貫孔23係連接該第一接墊層212及該第二接墊層211。
請參閱圖3B至圖3F，為本發明模組化堆疊式半導體封裝方法的第三實施例，其與圖1F至圖1K所示的步驟(a)至步驟(f)大致相同，惟步驟(a)製作各該晶片模組20不同，如圖3A所示，提供一第二載板60及多個第一及第二裸晶30a~30d；其中該第二載板60係包含有多個模組區61；於該第二載板60的各該模組區61形成該第二重佈線層21；將位在第一層的第二裸晶30a的主動面上的金屬接點31a覆晶接合於該第二重佈線層21；將位在第二層的第一裸晶30b的主動面部分黏著於位在第一層的第二裸晶30a的背面，其主動面的金屬接點31b覆晶接合於該第二重佈線層21；將位在第三層的第一裸晶30c的背面全面貼合於位在第二層的第一裸晶30b的背面，其主動面上的金屬接點31c則對應該第一接墊層212；將位在第四層的第二裸晶30d的背面部分黏著於位在第三層的第一裸晶30c的主動面，其主動面的金屬接點31d對應該第一接墊層212。於該些第二重佈線層21上形成一第一封膠層22，以包覆該些第一及第二裸晶30a~30d；於各該模組區61內形成貫穿該第一封膠層22的至少一貫穿孔；於各該貫穿孔內填充金屬材質構成導電貫孔23，各該導電貫孔23外露於該第一封膠層22表面的一端231與第三層及第四層第一及第二裸晶30c、30d的金屬接點31c、31d係構成各該晶片模組20的第一接墊層212，各該導電貫孔23的另一端則電連接該第二重佈線層21；請配合圖3A及圖3B所示，最後沿著相鄰模組區61邊界切割該第一封膠層22，形成多個相同晶片模組20，即各該晶片模組20係主要由一第一封膠體22’包覆一堆疊裸晶組30，該第二重佈線層21外露的表面即為各該晶片模組 20的第二接墊層211；於本實施例，該第二接墊層211具有一外露接墊對應該第一接墊層212的外露接墊(即該導電貫孔23的外露端231)。
當多個晶片模組20依據上述說明製作完畢後，即進行如圖3C至圖3F所示的步驟(b)至步驟(f)。
於步驟(b)中，如圖3C所示，於該第一載板50的各該元件區51上形成有一第一重佈線層10；於本實施例，該些第一重佈線層10係同時製成。
於步驟(c)中，如圖3C所示，先將第一層的晶片模組20a電連接至對應的該第一重佈層10上，其第二接墊層211朝上，再依序將第二至四層的晶片模組20b~20d堆疊並電連接至前一層的第二接墊層211。
於步驟(d)中，如圖3D所示，於該第一載板50上的該些第一重佈線層10上形成一第二封膠層40，以包覆該些晶片模組20a~20d。
於步驟(e)中，如圖3D及圖3E所示，移除該第一載板50，使各該第一重佈線層10的一表面11外露，並於外露表面11形成多個錫球12。
於步驟(f)中，如圖3E及圖3F所示，沿著相鄰的元件區51邊界切割該第二封膠層40，以形成多個N層的模組化堆疊式半導體元件1b；於本實施例，各該模組化堆疊式半導體元件1b係堆疊四層晶片模組20a~20d，並以第二封膠體40’包覆；其中如圖3B所示，各該晶片模組20a~20d的堆疊裸晶組30係包含四個相同裸晶30a~30d，其中下二個裸晶30a、30b係以同向錯開堆疊，並對應第二接墊層211，上二個裸晶30c、30d係以同向錯開堆疊，並對應第一接墊層212，中間二個裸晶30b、30c係以背對背全面黏合。
綜上所述，本發明主要預先準備相同的晶片模組，各晶片模組已包含有多個相互堆疊的裸晶，以該些晶片模組進行堆疊封裝製程時，大幅減 少因對位誤差而造成晶片模組內裸晶彼此之電連接瑕疵，提升堆疊多層之堆疊式半導體封裝方法的良率。
以上所述僅是本發明的實施例而已，並非對本發明做任何形式上的限制，雖然本發明已以實施例揭露如上，然而並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明技術方案的範圍內，當可利用上述揭示的技術內容作出些許更動或修飾為等同變化的等效實施例，但凡是未脫離本發明技術方案的內容，依據本發明的技術實質對以上實施例所作的任何簡單修改、等同變化與修飾，均仍屬於本發明技術方案的範圍內。
10:第一重佈線層
11:表面
20a~20d:晶片模組
21:第二重佈線組
211:第二接墊層
212:第一接墊層
50:第一載板
51:元件區

Claims (10)

  1. 一種模組化堆疊式半導體封裝方法，包括：(a)提供一第一載板及N*M個相同晶片模組；其中該第一載板具有M個元件區，各該晶片模組包含一堆疊裸晶組及一包覆該堆疊裸晶組的第一封膠體；(b)於該第一載板上的各元件區內形成一第一重佈線層；(c)將N個晶片模組堆疊在該第一載板之各元件區的第一重佈線層上，並彼此電連接；(d)於該第一載板上的該些第一重佈線層上形成一第二封膠層，以包覆該些晶片模組；(e)移除該第一載板，使各該第一重佈線層的一表面外露，並於外露表面形成多個錫球；以及(f)沿著相鄰的元件區邊界切割該第二封膠層，以形成多個N層的模組化堆疊式半導體元件。
  2. 如請求項1所述之模組化堆疊式半導體封裝方法，其中於步驟(a)中，各該晶片模組的堆疊裸晶組係進一步形成於一第二重佈線層，該第一封膠體形成在該第二重佈線層上以包覆該堆疊裸晶組，且該第一封膠體進一步形成有至少一導電貫孔；其中該第一封膠體的一第一外露表面形成一第一接墊層，而該第二重佈線層的一第二外露表面係形成一第二接墊層；其中該第一接墊層的至少一接墊係對應該第二接墊層的至少一接墊，該至少一導電貫孔係連接該第一接墊層及該第二接墊層。
  3. 如請求項2所述之模組化堆疊式半導體封裝方法，其中上述步驟(c)係包含： (c1)將位在第一層的該些晶片模組的第一接墊層係朝向該第一載板，並分別與對應元件區內的該第一重佈線層電連接，此時位在該第一層的該些晶片模組的第二接墊層係朝向遠離第一重佈線層的方向；(c2)將位在同一層的該些晶片模組的第一接墊層分別朝向並電連接位在前一層的該些晶片模組的第二接墊層；此時，位在相同一層的該些晶片模組的第二接墊層係朝向遠離第一重佈線層的方向；以及(c3)重覆步驟(c2)直到完成N層堆疊。
  4. 如請求項3所述之模組化堆疊式半導體封裝方法，其中各該晶片模組的堆疊裸晶組係包含二個相同第一裸晶，係以背對背方式堆疊，其四側側邊齊平，其中一第一裸晶的主動面上第一金屬接點係電連接該第一接墊層，另一第一裸晶的主動面上第一金屬接點係電連接該第二接墊層。
  5. 如請求項4所述之模組化堆疊式半導體封裝方法，其中各該晶片模組的堆疊裸晶組係進一步包含二個第二裸晶，該二第二裸晶的背面分別部分設置在對應的第一裸晶的主動面上，其中一第二裸晶的主動面上的第二金屬接點則與對應第一裸晶的主動面上的第一金屬接點電連接第一接墊層，另一第二裸晶的主動面上的第二金屬接點則與對應第一裸晶的主動面上的第一金屬接點電連接第二接墊層。
  6. 如請求項3所述之模組化堆疊式半導體封裝方法，其中各該晶片模組的堆疊裸晶組係包含二顆以上的相同裸晶，係以同向錯開堆疊，使各該裸晶的主動面上金屬接點外露，並對應該第二接墊層。
  7. 如請求項4所述之模組化堆疊式半導體封裝方法，上述該N*M個相同晶片模組的製法係包含： (s1)提供一第二載板及多個第一裸晶；其中該第二載板係包含有多個模組區；(s2)於該第二載板的各該模組區形成該第二重佈線層；(s3)將部分第一裸晶的主動面上的第一金屬接點覆晶接合於該第二重佈線層；(s4)將其餘第一裸晶的背面全面黏著於該第二重佈線層上的該些第一裸晶的背面，其主動面的第一金屬接點則朝向遠離該第二重佈線層；(s5)於該些第二重佈線層上形成一第一封膠層，以包覆該些第一裸晶；(s6)於各該模組區內形成貫穿該第一封膠層的至少一貫穿孔；(s7)於各該貫穿孔內填充金屬材質構成導電貫孔；(s8)研磨該第一封膠層，使步驟(s4)的第一裸晶的主動面的第一金屬接點外露，與各該導電貫孔的外露一端構成各該晶片模組的第一接墊層；以及(s9)沿著相鄰模組區邊界切割該第一封膠層，形成多個相同晶片模組。
  8. 如請求項5所述之模組化堆疊式半導體封裝方法，上述該N*M個相同晶片模組的製法係包含：(s1)提供一第二載板、多個該第一裸晶及多個該第二裸晶；其中該第二載板係包含有多個模組區；(s2)於該第二載板的各該模組區形成該第二重佈線層；(s3)將位在第一層的第二裸晶的主動面上的第二金屬接點覆晶接合於該第二重佈線層；(s4)將位在第二層的第一裸晶的主動面部分黏著於位在第一層的該些第二裸晶的背面上，其主動面的第一金屬接點覆晶接合於該第二重佈線層； (s5)將位在第三層的第一裸晶的背面全面黏著於位在第二層的該些第一裸晶的背面上，其主動面的第一金屬接點則朝向遠離該第二重佈線層；(s6)將位在第四層的第二裸晶的背面部分黏著於位在第三層的該些第一裸晶的主動面上，其主動面的第二金屬接點則朝向遠離該第二重佈線層；(s7)於該些第二重佈線層上形成一第一封膠層，以包覆該些第一裸晶及該些第二裸晶；(s8)於各該模組區內形成貫穿該第一封膠層的至少一貫穿孔；(s9)於各該貫穿孔內填充金屬材質構成導電貫孔；(s10)研磨該第一封膠層，使位在第三層的第一裸晶的主動面的第一金屬接點，與位在的第四層的第二裸晶的主動面的第二金屬接點外露，與各該導電貫孔的外露一端構成各該晶片模組的第一接墊層；以及(s11)沿著相鄰模組區邊界切割該第一封膠層，形成多個相同晶片模組。
  9. 如請求項6所述之模組化堆疊式半導體封裝方法，上述該N*M個相同晶片模組的製法係包含：(s1)提供一第二載板及多個該裸晶；其中該第二載板係包含有多個模組區；(s2)於該第二載板的各該模組區形成該第二重佈線層；(s3)將部分裸晶的主動面上的金屬接點覆晶接合於該第二重佈線層；(s4)將其餘裸晶的主動面部分黏著於該第二重佈線層上的該些裸晶的背面，其主動面的金屬接點覆晶接合於該第二重佈線層；(s5)於該些第二重佈線層上形成一第一封膠層，以包覆該些裸晶；(s6)於各該模組區內形成貫穿該第一封膠層的至少一貫穿孔； (s7)於各該貫穿孔內填充金屬材質構成導電貫孔，各該導電貫孔外露於該第一封膠層表面的一端係構成各該晶片模組的第一接墊層，另一端則電連接該第二重佈線層；以及(s9)沿著相鄰模組區邊界切割該第一封膠層，形成多個相同晶片模組。
  10. 如請求項7至9中任一項所述之模組化堆疊式半導體封裝方法，其中於各該導電貫孔係以電鍍於各該貫穿孔形成該金屬材質。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114242669A (zh) * 2022-02-28 2022-03-25 甬矽电子(宁波)股份有限公司 堆叠封装结构和堆叠结构封装方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150318261A1 (en) * 2014-04-30 2015-11-05 Samsung Electronics Co., Ltd. Method of fabricating semiconductor package, semiconductor package formed thereby, and semiconductor device including the same
US20190273075A1 (en) * 2016-06-15 2019-09-05 Samsung Electronics Co., Ltd. Semiconductor device having stacked semiconductor chips and method for fabricating the same
US20200227386A1 (en) * 2019-01-14 2020-07-16 Intel Corporation Dual rdl stacked die package using vertical wire

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10510629B2 (en) * 2018-05-18 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method of forming same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150318261A1 (en) * 2014-04-30 2015-11-05 Samsung Electronics Co., Ltd. Method of fabricating semiconductor package, semiconductor package formed thereby, and semiconductor device including the same
US20190273075A1 (en) * 2016-06-15 2019-09-05 Samsung Electronics Co., Ltd. Semiconductor device having stacked semiconductor chips and method for fabricating the same
US20200227386A1 (en) * 2019-01-14 2020-07-16 Intel Corporation Dual rdl stacked die package using vertical wire

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114242669A (zh) * 2022-02-28 2022-03-25 甬矽电子(宁波)股份有限公司 堆叠封装结构和堆叠结构封装方法
CN114242669B (zh) * 2022-02-28 2022-07-08 甬矽电子(宁波)股份有限公司 堆叠封装结构和堆叠结构封装方法

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