TWI582919B - 無基板扇出型多晶片封裝構造及其製造方法 - Google Patents

無基板扇出型多晶片封裝構造及其製造方法 Download PDF

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Publication number
TWI582919B
TWI582919B TW104144776A TW104144776A TWI582919B TW I582919 B TWI582919 B TW I582919B TW 104144776 A TW104144776 A TW 104144776A TW 104144776 A TW104144776 A TW 104144776A TW I582919 B TWI582919 B TW I582919B
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Taiwan
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contacts
fan
wafers
layer
chip package
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TW104144776A
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TW201724383A (zh
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張家維
林國鼎
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力成科技股份有限公司
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Priority to TW104144776A priority Critical patent/TWI582919B/zh
Priority to US15/245,653 priority patent/US9837384B2/en
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Publication of TWI582919B publication Critical patent/TWI582919B/zh
Publication of TW201724383A publication Critical patent/TW201724383A/zh

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Description

無基板扇出型多晶片封裝構造及其製造方法
本發明係有關於多晶片封裝構造，特別係有關於一種無基板扇出型多晶片封裝構造及其製造方法。
隨著智慧型手機、平坦電腦、電子手環等攜帶式電子產品的興行，電子元件希望能越來越薄、更高容量與更多功能的趨勢發展。早期覆晶封裝的積體電路晶片的封裝構造尚有使用印刷電路板作為晶片基板，但在晶圓等級與面板等級的扇出型封裝構造係以積體電路製程的線路重置層取代印刷電路板的線路結構，在晶圓模封製程或面板模封製程中以晶圓等級與面板等級的暫時載板承載晶片，故不需要基板的封裝構件，以節省封裝厚度。
扇出型晶片封裝構造依其模封製程中晶片主動面朝向暫板或遠離暫板的方式區分為面朝下與面朝上型態兩種。在面朝下扇出型晶片封裝構造的製程中，晶片主動面貼附於暫時載板，故面朝下扇出型晶片封裝構造難以進行多晶片之封裝，在模封之後，剝離暫時載板，以將晶片主動面露出，線路重置層形成於封膠體與晶片主動面上，並直接連接晶片的銲墊。為了清除晶片銲墊的污染物，銲墊容易受到損害。此外，在面朝上扇出型晶 片封裝構造的製程中，預先生長凸塊在晶圓上，由晶圓單離出之晶片，晶片之背面貼附於暫時載板，再模封以形成封膠體，之後以研磨方式露出凸塊之接合表面，線路重置層形成於封膠體上，以連接至晶片上凸塊的接合表面。在研磨過程可能對晶片主動面造成損害。
為了解決上述之問題，本發明之主要目的係在於提供一種無基板扇出型多晶片封裝構造及其製造方法，達到多晶片堆疊之超級薄封裝型態，並降低製程中對晶片主動面與銲墊之損害。
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種無基板扇出型多晶片封裝構造，包含一第一線路重置層、複數個晶片、一封膠體、一介電層以及一第二線路重置層。該第一線路重置層係包含複數個第一接點，該第一線路重置層係形成於一載體平面上。該些晶片係堆疊於該載體平面上，並使該些晶片電性連接至該些第一接點。該封膠體係形成於該載體平面上，以密封該些晶片與該些第一接點，該封膠體係具有一由該載體平面界定形成之底面，該第一線路重置層係具有複數個顯露於該底面之接點表面。該介電層係形成於該封膠體之該底面上，但不覆蓋該些接點表面。該第二線路重置層係形成於該封膠體之該底面上，該第二線路重置層係包含複數個第二接點與一扇出線路，該些第二接點係連接至該些接點表面，該扇 出線路係包覆於該介電層中。其中，該些接點表面、該封膠體之該底面與該些晶片之一背面係位於同一平面中。本發明另揭示上述無基板扇出型多晶片封裝構造之製造方法。
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。
在前述無基板扇出型多晶片封裝構造中，係可另包含複數個金屬線，係電性連接該些晶片至該些第一接點並密封於該封膠體中，並且該些接點表面係可對準於該些第一接點。故該些第一接點係位於該些晶片之外。
在前述無基板扇出型多晶片封裝構造中，該些晶片係可呈錯位排列，以利打線位置之編排。
在前述無基板扇出型多晶片封裝構造中，係可另包含複數個銲球，係可突出於該介電層並電性連接至該第二線路重置層之該扇出線路，以構成為無基板之多晶片球格陣列封裝構造。
在前述無基板扇出型多晶片封裝構造中，係可另包含一保護片，係可疊設於該些晶片上，以保護該些晶片之主動面為不外露於該封膠體之外。
在前述無基板扇出型多晶片封裝構造中，係可另包含複數個黏晶膠層，係可形成於該些晶片之間，而不形成於該些晶片與該介電層之間，以節省封裝厚度。
在前述無基板扇出型多晶片封裝構造中，較佳地該 些晶片之該背面係被該介電層完全覆蓋，以得到良好的晶片背面絕緣效果。
藉由上述的技術手段，打線形成之金屬線連接內置線路重置層再連接至外置線路重置層，本發明可以整合現有封裝設備與扇出封裝製程以建立一種超級薄封裝構造。
10‧‧‧載體平面
20‧‧‧暫時載體
21‧‧‧黏著層
100‧‧‧無基板扇出型多晶片封裝構造
110‧‧‧第一線路重置層
111‧‧‧第一接點
112‧‧‧接點表面
120‧‧‧晶片
121‧‧‧背面
122‧‧‧銲墊
130‧‧‧封膠體
131‧‧‧底面
140‧‧‧介電層
150‧‧‧第二線路重置層
151‧‧‧第二接點
152‧‧‧扇出線路
160‧‧‧金屬線
170‧‧‧銲球
180‧‧‧保護片
190‧‧‧黏晶膠層
第1圖：依據本發明之一具體實施例，一種無基板扇出型多晶片封裝構造之截面示意圖。
第2A至2H圖：依據本發明之一具體實施例，繪示該無基板扇出型多晶片封裝構造之製作過程中各主要步驟之元件截面示意圖。
以下將配合所附圖示詳細說明本發明之實施例，然應注意的是，該些圖示均為簡化之示意圖，僅以示意方法來說明本發明之基本架構或實施方法，故僅顯示與本案有關之元件與組合關係，圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理，以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計，詳細之元件佈局可能更為複雜。
依據本發明之一具體實施例，一種無基板扇出型多晶片封裝構造100舉例說明於第1圖之截面示意圖。第2A至2H圖係 繪示在該無基板扇出型多晶片封裝構造100之製作過程中各主要步驟之元件截面示意圖。一種無基板扇出型多晶片封裝構造100係包含一第一線路重置層110、複數個晶片120、一封膠體130、一介電層140以及一第二線路重置層150。
該第一線路重置層110係為內置線路重置層而嵌埋於該封膠體130中，該第二線路重置層150係為外置線路重置層而位於該封膠體130之外，該第一線路重置層110與該第二線路重置層150之分隔界線係為一載體平面10。該第一線路重置層110與該第二線路重置層150係為利用積體電路製程製作的複合金屬層，包含例如銅之導電主層，銅導電主層之厚度係可為3微米，在銅導電主層之底部通常有一例如鈦(Ti)之接著層與銅(Cu)晶種層，鈦接著層之厚度係可為0.1微米，銅晶種層之厚度係可為0.2微米，而非必要地，在銅導電主層之上方另可形成鎳金層，鎳層之厚度係可為2微米，金層之厚度係可為0.3微米，以增加該重配置線路層140的防銹能力與焊接能力。因此，該第一線路重置層110與該第二線路重置層150相較於習知基板之線路結構，不需要電鍍線的連接。在本實施例中，該第一線路重置層110與該第二線路重置層150之形成係為相反方向的沉積與電鍍，故該第一線路重置層110之接著/晶種層與該第二線路重置層150之接著/晶種層係可相互的貼近。
請參閱第1圖，該第一線路重置層110係包含複數個第一接點111，該第一線路重置層110係形成於該載體平面10上。該些第一接點111係可為打線接指。該些晶片120係堆疊於該載體 平面10上，並使該些晶片120電性連接至該些第一接點111。該些晶片120係為設有積體電路之半導體元件，積體電路形成於晶片之主動面，並以複數個銲墊122為其接合端點。較佳地，該些晶片120係可呈錯位排列，以利打線位置之編排，在此所稱的「錯位排列」表示，某一晶片120與其鄰近的晶片不縱向對準而使兩相鄰晶片之間產生一適當橫向位移，以不遮蓋下方晶片之銲墊122，具體為如第1圖所示的兩側交叉錯位的晶片堆疊，也可以是四側偏移錯位的晶片堆疊，也可以是單側偏移錯位的階梯狀晶片堆疊。在相鄰晶片之間除了晶背貼附膜之黏晶膠層190之外，可以不需要介設間隔物。在一打線電性連接的結構，該無基板扇出型多晶片封裝構造100係可另包含複數個金屬線160，例如打線形成之金線，係電性連接該些晶片120之複數個銲墊122至該些第一接點111並密封於該封膠體130中，並且該些接點表面112係可對準於該些第一接點111。故該些第一接點111係位於該些晶片120之外。該第一線路重置層110係不位於該些晶片120之一最低層背面121的下方。在不同實施例中，亦可利用內接合引線、金屬柱或模封導通孔連接該些晶片120至該些第一接點111。
較佳地，該無基板扇出型多晶片封裝構造100係可另包含一保護片180，例如虛晶片、金屬片或是膠帶，係可疊設於該些晶片120上，該保護片180之厚度係可相同於該些晶片120之晶片單位厚度，以保護該些晶片120之主動面為不外露於該封膠體130之外。而複數個黏晶膠層190係可形成於該些晶片120之 間，而不形成於該些晶片120與該介電層140之間，以節省封裝厚度。
該封膠體130係形成於該載體平面10上，以密封該些晶片120與該些第一接點111，該封膠體130係為模封環氧化合物，其係具有熱固性與電絕緣性。該封膠體130係具有一由該載體平面10界定形成之底面131，而該第一線路重置層110係具有複數個顯露於該底面131之接點表面112。
該介電層140係形成於該封膠體130之該底面131上，但不覆蓋該些接點表面112。該介電層140係可包含複數個有機保護層，以氣相沉積、旋塗或印刷等方法形成，有機保護層之材質係具體可為聚亞醯胺(polyimide,PI)，有機保護層之每一層厚度係介於3~20微米，具體可為5微米。
該第二線路重置層150係形成於該封膠體130之該底面131上，該第二線路重置層150係包含複數個第二接點151與一扇出線路152，該些第二接點151係連接至該些接點表面112，該扇出線路152係包覆於該介電層140中。在本實施例中，該些第二接點151係可為凸塊接墊。
其中，該些接點表面112、該封膠體130之該底面131與該些晶片120之一背面121係位於同一平面中，以利該介電層140之平坦形成。更具體地，該些晶片120係可具有一不被該封膠體130覆蓋之背面121，該背面121係可共平面於該封膠體130之該底面131且被該介電層140覆蓋，以得到良好的晶片背面絕緣效 果。
因此，本發明係提供一種無基板扇出型多晶片封裝構造100，可以達到多晶片堆疊之超級薄封裝型態，並降低製程中對該些晶片120之主動面與該些銲墊122之損害。
更具體地，該無基板扇出型多晶片封裝構造100係可另包含複數個銲球170，係可突出於該介電層140並電性連接至該第二線路重置層150之該扇出線路152，以構成為無基板之多晶片球格陣列封裝構造。
上述無基板扇出型多晶片封裝構造100之製造方法係配合第2A至2H圖並進一步說明如後。
首先，請參閱第2A圖，提供一暫時載體20。該暫時載體20係為一晶圓模擬載體或一面板模擬載體，具體可為模擬成12吋晶圓之玻璃片，該暫時載體20之表面係形成有一黏著層21，在照射UV光之後可失去黏性，以提供一具有可剝離黏性之載體平面10。之後，請參閱第2B圖，利用積體電路製程形成一第一線路重置層110於該暫時載體20上之該載體平面10上，該第一線路重置層110係包含複數個第一接點111。
之後，請參閱第2C圖，以晶片取放方式堆疊複數個晶片120於該載體平面10上，並利用打線形成之複數個金屬線160使該些晶片120電性連接至該些第一接點111。一保護片180係可疊設於該些晶片120上。該些晶片120係呈錯位排列為較佳。上述晶片取放製程與打線連接製程係可為交錯重覆。
之後，請參閱第2D圖，以晶圓等級模封或面板等級模封方式形成一封膠體130於該載體平面10上，以密封該些晶片120與該些第一接點111。較佳地但非必要地，可以實施一晶圓等級研磨或面板等級研磨之步驟，以降低該封膠體130之厚度。
之後，請參閱第2E圖，以UV照射方式使得該黏著層21失去黏性，移除該暫時載體20而分離出該封膠體130，使得該封膠體130係具有一由該載體平面10界定形成之底面131為顯露，該第一線路重置層110係具有複數個顯露於該底面131之接點表面112。該些晶片120之最底層背面121亦為顯露。其中，該些接點表面112、該封膠體130之該底面131與該些晶片120之該背面121係位於同一平面中。該些接點表面112係可對準於該些第一接點111。
之後，請參閱第2F圖，形成一介電層140與一第二線路重置層150於該封膠體130之該底面131上，該介電層140係不覆蓋該些接點表面112，該第二線路重置層150係包含複數個第二接點151與一扇出線路152，該些第二接點151係連接至該些接點表面112，該扇出線路152係包覆於該介電層140中。較佳地，在該介電層140形成之後，該些晶片120之該背面121係被該介電層140完全覆蓋。
請參閱第2G圖，利用球放置與迴焊方式設置複數個銲球170於該第二線路重置層150上，該些銲球170係突出於該介電層140並電性連接至該第二線路重置層150之該扇出線路152。
請參閱第2H圖，進行一單體化切割步驟，或可包含其它後端製程，以形成複數個分離之無基板扇出型多晶片封裝構造100。
以上所揭露的僅為本發明較佳實施例而已，當然不能以此來限定本發明之權利範圍，因此依本發明權利要求所作的等同變化，仍屬本發明所涵蓋的範圍。
10‧‧‧載體平面
100‧‧‧無基板扇出型多晶片封裝構造
110‧‧‧第一線路重置層
111‧‧‧第一接點
112‧‧‧接點表面
120‧‧‧晶片
121‧‧‧背面
122‧‧‧銲墊
130‧‧‧封膠體
131‧‧‧底面
140‧‧‧介電層
150‧‧‧第二線路重置層
151‧‧‧第二接點
152‧‧‧扇出線路
160‧‧‧金屬線
170‧‧‧銲球
180‧‧‧保護片
190‧‧‧黏晶膠層

Claims (11)

  1. 一種無基板扇出型多晶片封裝構造，包括：一第一線路重置層，係包含複數個第一接點，該第一線路重置層係形成於一載體平面上；複數個晶片，係堆疊於該載體平面上，並使該些晶片電性連接至該些第一接點；一封膠體，係形成於該載體平面上，以密封該些晶片與該些第一接點，該封膠體係具有一由該載體平面界定形成之底面，該第一線路重置層係具有複數個顯露於該底面之接點表面；一介電層，係形成於該封膠體之該底面上，但不覆蓋該些接點表面；以及一第二線路重置層，係形成於該封膠體之該底面上，該第二線路重置層係包含複數個第二接點與一扇出線路，該些第二接點係連接至該些接點表面，該扇出線路係包覆於該介電層中；其中，該些接點表面、該封膠體之該底面與該些晶片之一背面係位於同一平面中。
  2. 如申請專利範圍第1項所述之無基板扇出型多晶片封裝構造，另包含複數個金屬線，係電性連接該些晶片至該些第一接點並密封於該封膠體中，並且該些接點表面係對準於該些第一接點。
  3. 如申請專利範圍第2項所述之無基板扇出型多晶片封裝構造，其中該些晶片係呈錯位排列。
  4. 如申請專利範圍第1項所述之無基板扇出型多晶片封裝構造，另包含複數個銲球，係突出於該介電層並電性連接至該第二線路重置層之該扇出線路。
  5. 如申請專利範圍第1項所述之無基板扇出型多晶片封裝構造，另包含一保護片，係疊設於該些晶片上。
  6. 如申請專利範圍第1項所述之無基板扇出型多晶片封裝構造，另包含複數個黏晶膠層，係形成於該些晶片之間，而不形成於該些晶片與該介電層之間。
  7. 如申請專利範圍第1至6項任一項所述之無基板扇出型多晶片封裝構造，其中該些晶片之該背面係被該介電層完全覆蓋。
  8. 一種無基板扇出型多晶片封裝之製造方法，包含：形成一第一線路重置層於一暫時載體之一載體平面上，該第一線路重置層係包含複數個第一接點；堆疊複數個晶片於該載體平面上，並使該些晶片電性連接至該些第一接點；形成一封膠體於該載體平面上，以密封該些晶片與該些第一接點；移除該暫時載體，使得該封膠體係具有一由該載體平面界定形成之底面，該第一線路重置層係具有複數個顯露於該底面之接點表面；以及形成一介電層與一第二線路重置層於該封膠體之該底面上，該介電層係不覆蓋該些接點表面，該第二線路重置層係包含複數個第二接點與一扇出線路，該些第二接點係連接至該些接點表面，該扇出線路係包覆於該介電層中； 其中，該些接點表面、該封膠體之該底面與該些晶片之一背面係位於同一平面中。
  9. 如申請專利範圍第7項所述之無基板扇出型多晶片封裝構造之製造方法，另包含之步驟為：形成複數個金屬線，其係電性連接該些晶片至該些第一接點，並且該些接點表面係對準於該些第一接點。
  10. 如申請專利範圍第9項所述之無基板扇出型多晶片封裝構造之製造方法，其中該些晶片係呈錯位排列。
  11. 如申請專利範圍第8至11項任一項所述之無基板扇出型多晶片封裝構造之製造方法，其中在該介電層形成之後，該些晶片之該背面係被該介電層完全覆蓋。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10847488B2 (en) * 2015-11-02 2020-11-24 Mediatek Inc. Semiconductor package having multi-tier bonding wires and components directly mounted on the multi-tier bonding wires
US20180175004A1 (en) * 2016-12-18 2018-06-21 Nanya Technology Corporation Three dimensional integrated circuit package and method for manufacturing thereof
US20190013214A1 (en) * 2017-07-10 2019-01-10 Powertech Technology Inc. Package structure and manufacturing method thereof
CN109729240B (zh) * 2017-10-27 2020-12-18 宁波舜宇光电信息有限公司 摄像模组及其扩展布线封装感光组件和电子设备
KR102015909B1 (ko) * 2017-12-20 2019-09-06 삼성전자주식회사 팬-아웃 반도체 패키지
CN111866323A (zh) * 2019-04-30 2020-10-30 宁波舜宇光电信息有限公司 摄像模组及其感光组件、电子设备和制备方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201232758A (en) * 2011-01-18 2012-08-01 Delta Electronics Inc Power semiconductor package structure and manufacturing method thereof
TW201401479A (zh) * 2012-06-26 2014-01-01 矽品精密工業股份有限公司 具堆疊結構之封裝件及其製法
US20140227832A1 (en) * 2010-07-01 2014-08-14 United Test And Assembly Center Ltd. Semiconductor packages and methods of packaging semiconductor devices

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7592691B2 (en) * 2006-09-01 2009-09-22 Micron Technology, Inc. High density stacked die assemblies, structures incorporated therein and methods of fabricating the assemblies
US8169065B2 (en) * 2009-12-22 2012-05-01 Epic Technologies, Inc. Stackable circuit structures and methods of fabrication thereof
US9136197B2 (en) * 2010-09-16 2015-09-15 Tessera, Inc. Impedence controlled packages with metal sheet or 2-layer RDL
US8786083B2 (en) * 2010-09-16 2014-07-22 Tessera, Inc. Impedance controlled packages with metal sheet or 2-layer RDL
DE102014101092A1 (de) * 2014-01-29 2015-07-30 Epcos Ag Chip mit Schutzfunktion und Verfahren zur Herstellung
US9640468B2 (en) * 2014-12-24 2017-05-02 Stmicroelectronics S.R.L. Process for manufacturing a package for a surface-mount semiconductor device and semiconductor device
US9412722B1 (en) * 2015-02-12 2016-08-09 Dawning Leading Technology Inc. Multichip stacking package structure and method for manufacturing the same
US9673183B2 (en) * 2015-07-07 2017-06-06 Micron Technology, Inc. Methods of making semiconductor device packages and related semiconductor device packages
TWI566356B (zh) * 2015-10-15 2017-01-11 力成科技股份有限公司 封裝結構及其製造方法
US9735131B2 (en) * 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140227832A1 (en) * 2010-07-01 2014-08-14 United Test And Assembly Center Ltd. Semiconductor packages and methods of packaging semiconductor devices
TW201232758A (en) * 2011-01-18 2012-08-01 Delta Electronics Inc Power semiconductor package structure and manufacturing method thereof
TW201401479A (zh) * 2012-06-26 2014-01-01 矽品精密工業股份有限公司 具堆疊結構之封裝件及其製法

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