TW201822330A - 晶片封裝結構 - Google Patents

晶片封裝結構 Download PDF

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Publication number
TW201822330A
TW201822330A TW106109694A TW106109694A TW201822330A TW 201822330 A TW201822330 A TW 201822330A TW 106109694 A TW106109694 A TW 106109694A TW 106109694 A TW106109694 A TW 106109694A TW 201822330 A TW201822330 A TW 201822330A
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Taiwan
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layer
chip
wafer
conductive
molding layer
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TW106109694A
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English (en)
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TWI701790B (zh
Inventor
陳威宇
黃立賢
蘇安治
陳憲偉
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台灣積體電路製造股份有限公司
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

提供晶片封裝結構。晶片封裝結構包含再佈線基板。晶片封裝結構包含第一晶片結構，其位於再佈線基板上。晶片封裝結構包含第一焊料凸塊，其配置於再佈線基板與第一晶片結構之間，並電性連接再佈線基板與第一晶片結構。晶片封裝結構包含第一成型層，其圍繞第一晶片結構。第一成型層與第一晶片結構以及再佈線基板之間隔有第一焊料凸塊，以定義間隙於第一成型層與第一晶片結構以及再佈線基板之間。晶片封裝結構包含第二晶片結構，其位於第一晶片結構上。晶片封裝結構包含第二成型層，其圍繞第二晶片結構。晶片封裝結構包含第三成型層，其圍繞第一成型層、第二成型層、與第一焊料凸塊，並填入間隙中。

Description

晶片封裝結構
本發明實施例關於半導體結構，更特別關於晶片封裝結構與其形成方法。
半導體積體電路產業經歷快速成長。積體電路材料與設計的技術進步，使每一代的電路比前一代的電路更小更複雜。然而這些進展會增加積體電路製程的複雜度。
在積體電路的進展中，隨著幾何尺寸(製程所能產生的最小構件或線路)縮小，功能密度(單位晶片面積中的內連線裝置數目)增加。上述尺寸縮小的製程的優點為增加產能及降低相關成本。
然而隨著結構尺寸一直縮小，將更難以進行製程，且製程(如熱製程)也更易影響積體電路的效能。綜上所述，目前挑戰為形成越來越小的半導體裝置時兼顧其可信度。
本發明一實施例提供之晶片封裝結構，包括：再佈線基板；第一晶片結構，位於再佈線基板上；第一焊料凸塊，配置於再佈線基板與第一晶片結構之間，並電性連接再佈線基板與第一晶片結構；第一成型層，圍繞第一晶片結構，其中第一成型層與第一晶片結構以及再佈線基板之間隔有第一焊料凸塊，以定義間隙於第一成型層與第一晶片結構以及再佈線基 板之間；第二晶片結構，位於第一晶片結構上；第二成型層，圍繞第二晶片結構；以及第三成型層，圍繞第一成型層、第二成型層、與第一焊料凸塊，並填入間隙中。
D‧‧‧距離
G‧‧‧間隙
I‧‧‧內連線結構
T、T1、T2‧‧‧厚度
W、W3、W4、W5、W6、W7、W8、W9、W10‧‧‧寬度
W1、W2‧‧‧最大寬度
110、220‧‧‧承載基板
120‧‧‧黏著層
130、130b、170‧‧‧晶片結構
130a、130c、131、134a、136a、138a、139a、142、146、162、170a、178a、179a、182、232a、244‧‧‧上表面
130d、144、154、184、194、239、242、418、518‧‧‧側壁
132、172‧‧‧晶片
134、174、232、412、512‧‧‧介電層
136、176‧‧‧接合墊
138、178‧‧‧內連線結構
139、179‧‧‧鈍化層
140、180、240‧‧‧成型層
150‧‧‧絕緣層
152‧‧‧孔洞
160‧‧‧導電通孔結構
190‧‧‧導電柱
192、412a、512a‧‧‧下表面
200、300、400、500、600、700、800‧‧‧晶片封裝結構
210‧‧‧焊料凸塊
230‧‧‧再佈線基板
234、414、514‧‧‧線路層
236a、236b‧‧‧導電墊
238、416、516‧‧‧導電通孔
250‧‧‧導電凸塊
410、510‧‧‧再佈線層
第1A至1J圖係一些實施例中，晶片封裝結構於其形成製程之多種階段中的剖視圖。
第1G-1圖係一些實施例中，第1G圖之焊料凸塊與導電柱的放大剖視圖。
第2圖係一些實施例中，晶片封裝結構的剖視圖。
第3圖係一些實施例中，晶片封裝結構的剖視圖。
第4A至4C圖係一些實施例中，晶片封裝結構於其形成製程之多種階段中的剖視圖。
第5圖係一些實施例中，晶片封裝結構的剖視圖。
第6圖係一些實施例中，晶片封裝結構的剖視圖。
下述內容提供的不同實施例或實例可實施本發明的不同結構。特定構件與排列的實施例係用以簡化本發明而非侷限本發明。舉例來說，形成第一構件於第二構件上的敘述包含兩者直接接觸，或兩者之間隔有其他額外構件而非直接接觸。此外，本發明之多種例子中可重複標號及/或符號，但這些重複僅用以簡化與清楚說明，不代表不同實施例及/或設置之間具有相同標號及/或符號的單元之間具有相同的對應關係。
此外，空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。應理解的是，在下述方法之前、之中、與之後可進行額外步驟，且其他實施例之方法的一些步驟可省略或取代為其他步驟。
第1A至1J圖係一些實施例中，晶片封裝結構於其形成製程之多種階段中的剖視圖。
如第1A圖所示的一些實施例，提供承載基板110。在一些實施例中，承載基板110設置以在後續製程步驟中，提供暫時的機械與結構支撐。在一些實施例中，承載基板110包含玻璃、氧化矽、氧化鋁、上述之組合、及/或類似物。在一些實施例中，承載基板110包含晶圓。
如第1A圖所示的一些實施例，黏著層120形成於承載基板110上。在一些實施例中，黏著層120包含任何合適的黏著材料如高分子材料。舉例來說，一些實施例之黏著層120包含紫外線膠，照射紫外線時將失去其黏著性。在一些實施例中，黏著層120包含雙面黏著帶。黏著層120的形成方法可為壓合製程、旋轉塗佈製程、或另一合適製程。
如第1A圖所示的一些實施例，提供晶片結構130至黏著層120上。在一些實施例中，每一晶片結構130包含晶片132、介電層134、接合墊136、內連線結構138、與鈍化層139。 在一些實施例中，介電層134形成於晶片132上。
在一些實施例中，介電層134包含氧化矽、氮氧化矽、硼矽酸鹽玻璃、磷矽酸鹽玻璃、硼磷矽酸鹽玻璃、氟化矽酸鹽玻璃、低介電常數材料、孔洞狀的介電材料、或上述之組合。在一些實施例中，介電層134的形成方法可為化學氣相沉積製程、高密度電漿化學氣相沉積製程、旋轉塗佈製程、濺鍍製程、或上述之組合。
在一些實施例中，接合墊136埋置於介電層134中。在一些實施例中，接合墊電性連接至晶片132之中/之上的裝置(未圖示)。在一些實施例中，內連線結構138形成於格別的接合墊136上。
在一些實施例中，內連線結構138包含導電柱或導電凸塊。在一些實施例中，鈍化層139形成於介電層134上，並圍繞內連線結構138。鈍化層139可包含高分子材料或另一合適的絕緣材料。
如第1B圖所示的一些實施例，成型層140形成於承載基板110與黏著層120上。在一些實施例中，成型層140圍繞晶片結構130在一些實施例中，部份的成型層140位於晶片結構130之間。成型層140可包含高分子材料或另一合適的絕緣材料。
在一些實施例中，成型層140的形成方法包含形成成型化合物材料於黏著層120上、進行硬化製程以交聯(或熱固化)成型化合物材料層的高分子、以及在成型化合物材料層上進行研磨製程，直到露出內連線結構138。如此一來，一些實 施例之內連線結構138的上表面138a、鈍化層139的上表面139a、晶片結構130的上表面130a、與成型層140的上表面142將共平面(或彼此齊平)。
如第1B圖所示的一些實施例中，絕緣層150形成於成型層140與晶片結構130上。在一些實施例中，絕緣層150為連續的層狀物。在一些實施例中，絕緣層150具有孔洞152於內連線結構138上。在一些實施例中，孔洞152分別露出下方的內連線結構138。
如第1C圖所示的一些實施例，導電通孔結構160形成於孔洞152之中與之上，以分別電性連接至內連線結構138。導電通孔結構160可包含銅或另一合適的導電材料。
如第1C圖所示的一些實施例，提供晶片結構170於絕緣層150上。在一些實施例中，晶片結構170位於晶片結構130及成型層140上。
在一些實施例中，晶片結構170露出每一晶片結構130的一部份。在一些實施例中，晶片結構170位於導電通孔結構160之間。在一些實施例中，導電通孔結構160圍繞晶片結構170。
在一些實施例中，每一晶片結構170包含晶片172、介電層174、接合墊176、內連線結構178、與鈍化層179。在一些實施例中，介電層174形成於晶片172上。
在一些實施例中，介電層174包含氧化矽、氮氧化矽、硼矽酸鹽玻璃、磷矽酸鹽玻璃、硼磷矽酸鹽玻璃、氟化矽酸鹽玻璃、低介電常數材料、孔洞狀的介電材料、或上述之組 合。在一些實施例中，介電層174的形成方法可為化學氣相沉積製程、高密度電漿化學氣相沉積製程、旋轉塗佈製程、濺鍍製程、或上述之組合。
在一些實施例中，接合墊176埋置於介電層174中。在一些實施例中，接合墊176電性連接至形成於晶片172之中/之上的裝置(未圖示)。在一些實施例中，內連線結構178分別形成於接合墊176上。
在一些實施例中，內連線結構178包含導電柱或導電凸塊。在一些實施例中，鈍化層179形成於介電層174上，並圍繞內連線結構178。鈍化層179包含高分子材料或另一合適的絕緣材料。
如第1C圖所示的一些實施例，成型層180形成於絕緣層150上。在一些實施例中，絕緣層150與成型層140及晶片結構130之間，隔有成型層180與晶片結構170。在一些實施例中，成型層180位於晶片結構130及成型層140上。
在一些實施例中，成型層180圍繞晶片結構170與導電通孔結構160。在一些實施例中，部份的成型層180位於晶片結構170與導電通孔結構160之間。成型層180可包含高分子材料或另一合適的絕緣材料。
在一些實施例中，成型層180的形成方法包含形成成型化合物材料於絕緣層150上、進行硬化製程以交聯(或熱固化)成型化合物材料層的高分子、以及在成型化合物材料層上進行研磨製程，直到露出內連線結構160與內連線結構178。
如此一來，一些實施例之內連線結構178的上表面 178a、鈍化層179的上表面179a、晶片結構170的上表面170a、導電通孔結構160的上表面162、與成型層180的上表面182將共平面(或彼此齊平)。在一些實施例中，導電通孔結構160穿過成型層180。
如第1D圖所示的一些實施例，導電柱190分別形成於導電通孔結構160與內連線結構178上。在一些實施例中，導電柱190直接接觸下方的導電通孔結構160與下方的內連線結構178。
導電柱190可包含銅或另一合適的導電材料。在一些實施例中，導電柱190不含錫。在一些實施例中，導電柱190的形成方法為電鍍製程。
如第1D圖所示的一些實施例，焊料凸塊210形成於導電柱190上。在一些實施例中，焊料凸塊210直接接觸導電柱190。在一些實施例中，一些導電柱190位於晶片結構170與焊料凸塊210之間。
在一些實施例中，一些導電柱190位於導電通孔結構160與焊料凸塊210之間。焊料凸塊210可包含錫、銀、金、鉛、或另一合適的焊料材料。在一些實施例中，焊料凸塊210與導電柱190由不同材料組成。在一些實施例中，焊料凸塊210的形成方法可為電鍍製程。
如第1E圖所示的一些實施例，自承載基板110剝離晶片結構130與成型層140。在一些實施例中，剝離製程包含在黏著層120上進行熱製程。舉例來說，以紫外線照射黏著層120，以弱化黏著層120的黏著性。
如第1E圖所示的一些實施例，在成型層180、絕緣層150、與成型層140上進行切割製程，以形成個別的晶片封裝結構200。在一些實施例中，每一晶片封裝結構200包含晶片結構130、成型層140、絕緣層150、導電通孔結構160、晶片結構170、成型層180、導電柱190、與焊料凸塊210。
在一些實施例中，晶片封裝結構200為多晶片堆疊的封裝結構。一些實施例之每一晶片封裝結構200中，成型層180的側壁184、絕緣層150的側壁154、與成型層140的側壁144共平面。
如第1F圖所示的一些實施例，提供承載基板220。承載基板220設置以在後續製程步驟中，提供暫時的機械與結構支撐。在一些實施例中，承載基板220包含玻璃、氧化矽、氧化鋁、上述之組合、及/或類似物。
如第1F圖所示的一些實施例，再佈線基板230分開地形成於載體基板220上(而非整體地形成於晶片封裝結構200上)。在一些實施例中，再佈線基板230包含介電層232、線路層234、導電墊236a與236b、以及導電通孔238。在一些實施例中，介電層232具有上表面232a。
在一些實施例中，線路層234與導電通孔238位於介電層232中。在一些實施例中，導電墊236a位於介電層232上。在一些實施例中，導電墊236b位於介電層232下。
在一些實施例中，導電通孔238位於導電墊236a與236b以及線路層234之間。如此一來，一些實施例的導電墊236a與236b與線路層234可依設計需求，經由導電通孔238彼此電性 連接。在一些實施例中，每一導電通孔238的寬度W朝介電層232之上表面232a的方向持續增加。
如第1G圖所示的一些實施例，晶片封裝結構200翻轉朝上後，置於再佈線基板230上。在一些實施例中，焊料凸塊210位於個別的導電墊236a上。在一些實施例中，之後可在焊料凸塊210上進行再流動製程。
在一些實施例中，導電柱190之組成為第一導電材料，而焊料凸塊210之組成為第二導電材料。在一些實施例中，第一導電材料的第一熔點高於第二導電材料的第二熔點。
在一些實施例中，再流動製程的溫度介於第一熔點與第二熔點之間。如此一來，一些實施例之再流動製程中的焊料凸塊210將熔融，並接合至導電墊236a與導電柱190。
第1G-1圖係一些實施例中，第1G圖之焊料凸塊210與導電柱190的放大剖視圖。如第1G與1G-1圖所示，在再流動製程之後，焊料凸塊210覆蓋焊料凸塊210上的導電柱190之下表面192。在一些實施例中(未圖示)，焊料凸塊210亦覆蓋焊料凸塊210上之導電柱190之部份側壁194。
在一些實施例中，導電柱190的厚度T2大於焊料凸塊210的厚度T1。在一些實施例中，焊料凸塊210的最大寬度W1大於其上之導電柱190之最大寬度W2。
在一些實施例中，導電柱190與其下之焊料凸塊210一起形成內連線結構I。在一些實施例中，內連線結構I的厚度T，實質上等於晶片結構170(或成型層180)與再佈線基板230之間的距離D。在一些實施例中，厚度T或距離D介於約20微米 至約30微米之間。
在一些實施例中，成型層180與晶片結構170與再佈線基板230之間隔有間隙G。在一些實施例中，導電柱190與焊料凸塊210位於間隙G中。
由於導電柱190不會在再流動製程中熔融，因此導電柱190可維持內連線結構I的厚度T，且導電柱190可維持距離D至適當數值。如此一來，後續製程中的成型化合物材料可輕易填入間隙G。
此外，導電柱190可在維持相同距離D時，減少其下方之焊料凸塊210的體積，可避免相鄰之焊料凸塊210因再流動製程而短路。
如第1H圖所示的一些實施例，成型層240形成於再佈線基板230上。在一些實施例中，成型層240圍繞晶片封裝結構200。
在一些實施例中，成型層240圍繞晶片結構130、成型層140、絕緣層150、導電通孔結構160、晶片結構170、成型層180、導電柱190、與焊料凸塊210。
在一些實施例中，成型層240填入間隙G。在一些實施例中，成型層240直接接觸焊料凸塊210、導電柱190、再佈線基板230、成型層140與180、以及絕緣層150。成型層240可包含高分子材料或另一合適的絕緣材料。
在一些實施例中，成型層240的形成方法包含形成成型化合物材料於再佈線基板230與晶片封裝結構200上、進行硬化製程以交聯(或熱固化)成型化合物材料層的高分子、以及 在成型化合物材料層上進行研磨製程，直到露出晶片結構130的上表面131。
如第1I圖所示的一些實施例，移除承載基板220。如第11圖所示的一些實施例中，導電凸塊250分別形成於導電墊236b上。導電凸塊250可包含錫或另一合適的導電材料。在一些實施例中，導電凸塊250的形成方法可包含形成焊料膏於導電墊236b上，並再流動焊料膏。
如第1J圖所示的一些實施例中，在成型層240與再佈線基板230上進行切割製程，以形成個別的晶片封裝結構300。在一些實施例中，每一晶片封裝結構300包含晶片封裝結構200、成型層240、再佈線基板230、與導電凸塊250。在一些實施例的晶片封裝結構300中，成型層240的側壁242與再佈線基板230的側壁239共平面。
在一些實施例中，在晶片封裝結構300中，成型層240的上表面244、晶片結構130的上表面131、與成型層140的上表面146共平面。在一些實施例中，導電柱160穿過成型層180。在一些實施例中，成型層240連續地圍繞整個晶片封裝結構200。
在一些實施例中，成型層240為單層結構。在一些實施例中，成型層240未覆蓋晶片結構130的上表面131。在一些實施例中，晶片封裝結構300為扇出式晶片封裝結構。
在一些實施例中，再佈線基板230的寬度W3大於晶片封裝結構200的寬度W4。在一些實施例中，寬度W4大於晶片結構130的寬度W5或晶片結構170的寬度W6。
在一些實施例中，第1A至1J圖的製程包含形成晶片封裝結構200、將晶片封裝結構200接合至再佈線基板230、形成成型層240於再佈線基板230上以及晶片封裝結構200之間、以及進行切割製程以形成個別的晶片封裝結構300。
在一些實施例中，由於晶片封裝結構200與再佈線基板230分開形成，可避免形成再佈線基板230之介電層232的熱製程影響晶片封裝結構200的晶片132與172。如此一來，一些實施例可維持晶片132與172的效能。
此外，由於分開形成晶片封裝結構200與再佈線基板230，因此可同時形成晶片封裝結構200與再佈線基板230。如此一來，一些實施例可縮短晶片封裝結構300的週期(製程時間)。
在一些實施例中，可對第1D圖之導電柱190與焊料凸塊210進行電性檢測(如最終檢測)，以確認良品晶粒。在一些實施例中，可對第1F圖之再佈線基板230進行電性檢測(如最終檢測)，以確認良品再佈線層。
在一些實施例中，之後在第1G圖所示的步驟中，撿選具有良品晶粒的晶片封裝結構200並將其置於具有良品再佈線層的再佈線基板230上，以形成具有良品晶粒與良品再佈性層的晶片封裝結構300。如此一來，一些實施例可改善晶片封裝結構300的良率。
第2圖係一些實施例中，晶片封裝結構400的剖視圖。如第2圖所示的一些實施例，晶片封裝結構400與第1J圖之晶片封裝結構300類似，差別在於晶片封裝結構400進一步包含 再佈線層410。
在一些實施例中，再佈線層410位於成型層140與180之間、位於晶片結構130與成型層180之間、位於晶片結構130與170之間、位於成型層140與晶片結構170之間、以及位於晶片結構130與導電通孔結構160之間。
在一些實施例中，再佈線層410包含介電層412、線路層414、與導電通孔416。在一些實施例中，線路層414與導電通孔416位於介電層412中。在一些實施例中，導電通孔416位於線路層414與內連線結構138之間。
如此一來，一些實施例的內連線結構138與線路層414可依設計需求，經由導電通孔416彼此電性連接。在一些實施例中，每一導電通孔416的寬度W8朝介電層412之下表面412a的方向持續增加。
在一些實施例中，再佈線層410直接接觸晶片結構130、成型層140與240、導電通孔結構160、與絕緣層150。在一些實施例中，成型層180的側壁184、成型層140的側壁144、與再佈線層410的側壁418共平面。在一些實施例中，再佈線層410的寬度W7與晶片封裝結構200的寬度W4實質上相同。
第3圖係一些實施例中，晶片封裝結構500的剖視圖。如第3圖所示的一些實施例，晶片封裝結構500與第2圖之晶片封裝結構400類似，差別在於晶片封裝結構500進一步包含再佈線層510。
在一些實施例中，再佈線層510位於成型層240與180之間、位於晶片結構170與成型層240之間、位於晶片結構 170與導電柱190之間、以及位於導電通孔結構160與導電柱190之間。
在一些實施例中，再佈線層510包含介電層512、線路層514、與導電通孔516。在一些實施例中，線路層514與導電柱516位於介電層512中。在一些實施例中，導電通孔516位於線路層514與內連線結構178之間。
如此一來，一些實施例的內連線結構178與線路層514可依設計需求，經由導電通孔516彼此電性連接。在一些實施例中，每一導電通孔516的寬度W10朝介電層512之下表面512a的方向持續增加。
在一些實施例中，再佈線層510直接接觸晶片結構170、成型層180與240、導電通孔結構160、與導電柱190。在一些實施例中，成型層180之側壁184、成型層之側壁144、再佈線層410之側壁418、與再佈線層510之側壁518共平面。在一些實施例中，再佈線層410的寬度W7、晶片封裝結構200的寬度W4、與再佈線層510的寬度W9實質上彼此相同。
第4A至4C圖係一些實施例中，形成晶片封裝結構之製程的多種階段其剖視圖。如第4A圖所示的一些實施例，提供承載基板110與黏著層120。在一些實施例中，第4A圖的承載基板110與黏著層120之材料、結構、與位置與第1A圖的承載基板110與黏著層120之材料、結構、與位置類似。
如第4A圖所示的一些實施例，提供晶片結構130b於黏著層120上。在一些實施例中，第4A圖之晶片結構130b與第1A圖之晶片結構130類似，差別在於晶片結構130b不包含內 連線結構138與鈍化層139。
如第4B圖所示的一些實施例，成型層140形成於承載基板110與黏著層120上。在一些實施例中，成型層140圍繞晶片結構130b。在一些實施例中，部份的成型層140位於晶片結構130b之間。成型層140可包含高分子材料或另一合適的絕緣材料。
在一些實施例中，成型層140的形成方法包含轉移成型製程。轉移成型製程可包含：提供模具於黏著層120上，其中模具的頂板部份直接接觸接合墊136的上表面136a與介電層134的上表面134a，且模具的側壁部份與晶片結構130b的側壁部份130d之間具有空間；將成型化合物材料注入空間中；進行硬化製程以交聯(熱固化)成型化合物材料的高分子；以及移除模具。
在一些實施例中，由於模具的頂板部份直接接觸上表面136a與134a，成型層140將露出接合墊136與介電層134。如此一來，不需在成型化合物材料層上進行研磨製程以露出接合墊136。
如此一來，一些實施例不需避免研磨製程損傷接合墊136，而形成內連線結構與鈍化層於接合墊136上。因此在一些實施例中，可減少晶片結構130b的成本。在一些實施例中，接合墊136的上表面136a、介電層134的上表面134a、晶片結構130b的上表面130c、與成型層140的上表面142共平面(或彼此對準)。
如第4B圖所示的一些實施例，絕緣層150形成於成 型層140與晶片結構130b上。在一些實施例中，絕緣層150為連續的層狀物。在一些實施例中，絕緣層150具有孔洞152分別位於接合墊136上。在一些實施例中，孔洞152各自露出下方的接合墊136。
在一些實施例中，進行第1C至1J圖中的步驟後，實質上形成第4C圖所示的晶片封裝結構600。在一些實施例中，晶片封裝結構600與第1J圖的晶片封裝結構300類似，差別在晶片封裝結構600的晶片結構130b，不包含第1J圖之晶片封裝結構300的內連線結構138與鈍化層139。如此一來，一些實施例可降低晶片封裝結構600的成本。
第5圖係一些實施例中，晶片封裝結構700的剖視圖。如第5圖所示的一些實施例，晶片封裝結構700與第4C圖的晶片封裝結構600類似，差別在於晶片封裝結構700更包含再佈線層410。
在一些實施例中，第5圖的再佈線層410與第2圖的再佈線層410類似。在一些實施例中，再佈線層410位於成型層140與180之間、位於晶片結構130b與成型層180之間、位於晶片結構130b與170之間、位於成型層140與晶片結構170之間、以及位於晶片結構130b與導電通孔結構160之間。
在一些實施例中，再佈線層410包含介電層412、線路層414、與導電通孔416。在一些實施例中，線路層414與導電通孔416位於介電層412中。在一些實施例中，導電通孔416位於線路層414與接合墊136之間。
如此一來，一些實施例的導電墊136與線路層414 可依設計需求，經由導電通孔416彼此電性連接。在一些實施例中，再佈線層410直接接觸晶片結構130b、成型層140與240、導電通孔結構160、與絕緣層150。
第6圖係一些實施例中，晶片封裝結構800的剖視圖。如第6圖所示的一些實施例，晶片封裝結構800與第5圖之晶片封裝結構700類似，差別在於晶片封裝結構800更包含再佈線層510。
在一些實施例中，第6圖之再佈線層510與第3圖之再佈線層510類似。在一些實施例中，再佈線層510位於成型層240與180之間、位於晶片結構170與成型層240之間、位於晶片結構170與導電柱190之間、以及位於導電通孔結構160與導電柱190之間。
在一些實施例中，再佈線層510包含介電層512、線路層514、與導電通孔516。在一些實施例中，線路層514與導電通孔516位於介電層512中。在一些實施例中，導電通孔516位於線路層514與內連線結構178之間。
如此一來，一些實施例的內連線結構178與線路層514可依設計需求，經由導電通孔516彼此電性連接。在一些實施例中，再佈線層510直接接觸晶片結構170、成型層180與240、導電通孔結構160、與導電柱190。
本發明一些實施例提供晶片封裝結構與其形成方法。用以形成晶片封裝結構的方法包括分別形成多晶片堆疊的封裝結構與再佈線基板；將多晶片堆疊的封裝結構接合至再佈線基板上；以及形成成型層於再佈線基板上並圍繞多晶片封裝 結構。如此一來，可避免形成再佈線基板之介電層的方法之熱製程，影響多晶片堆疊的封裝結構。如此一來，可維持晶片效能，並改善具有這些晶片的晶片封裝結構良率。
在一些實施例中，提供晶片封裝結構，其包含再佈線基板。晶片封裝結構包含第一晶片結構，其位於再佈線基板上。晶片封裝結構包含第一焊料凸塊，其配置於再佈線基板與第一晶片結構之間，並電性連接再佈線基板與第一晶片結構。晶片封裝結構包含第一成型層，其圍繞第一晶片結構，其中第一成型層與第一晶片結構以及再佈線基板之間隔有第一焊料凸塊，以定義間隙於第一成型層與第一晶片結構以及再佈線基板之間。晶片封裝結構包含第二晶片結構，其位於第一晶片結構上。晶片封裝結構包含第二成型層，其圍繞第二晶片結構。晶片封裝結構包含第三成型層，其圍繞第一成型層、第二成型層、與第一焊料凸塊，並填入間隙中。
在一些實施例中，上述晶片封裝結構更包含：導電凸塊，位於間隙中以及第一晶片結構與第一焊料凸塊之間。
在一些實施例中，上述晶片封裝結構之導電柱直接接觸第一晶片結構與第一焊料凸塊。
在一些實施例中，上述晶片封裝結構之第一焊料凸塊的組成為第一導電材料，導電柱的組成為第二導電材料，且第二導電材料的熔點高於第一導電材料的熔點。
在一些實施例中，上述晶片封裝結構之第一焊料凸塊的最大寬度大於導電柱的最大寬度。
在一些實施例中，上述晶片封裝結構之第三成型 層直接接觸第一焊料凸塊、導電柱、再佈線基板、第一成型層、與第二成型層。
在一些實施例中，上述晶片封裝結構更包括：導電通孔結構，其穿過第一成型層並電性連接至第二晶片結構；第二焊料凸塊，其位於間隙中並連接至再佈線基板；以及導電柱，其位於導電通孔結構與第二焊料凸塊之間。
在一些實施例中，上述晶片封裝結構更包括：再佈線層，其位於第一成型層與間隙中的第三成型層之間，並位於第一晶片結構與第一焊料凸塊之間，其中導電通孔結構連接至再佈線層。
在一些實施例中，上述晶片封裝結構之第三成型層的側壁與再佈線基板的側壁共平面，第三成型層的上表面、第二晶片結構的上表面、與第二成型層的上表面共平面，且第一晶片結構的下表面與第一成型層的下表面共平面。
一些實施例提供晶片封裝結構，其包含再佈線基板。晶片封裝結構包含第一晶片結構，其位於再佈線基板上。晶片封裝結構包含第一焊料凸塊，其配置於再佈線基板與第一晶片結構之間，且電性連接再佈線基板與第一晶片結構。晶片封裝結構包含第一成型層，其圍繞第一晶片結構。第一成型層及第一晶片結構均與再佈線基板隔有第一焊料凸塊，以定義間隙於第一成型層及第一晶片結構與再佈線基板之間。晶片封裝結構包含第一導電柱，其位於間隙中並位於第一晶片結構下。第一焊料凸塊配置於第一導電柱與再佈線基板之間。第一焊料凸塊與第一導電柱一起形成內連線結構，且內連線結構的厚度 實質上等於第一晶片結構與再佈線基板之間的距離。晶片封裝結構包含第二晶片結構，其位於第一晶片結構與第一成型層中至少一者上。晶片封裝結構包含第二成型層，其圍繞第二晶片結構。晶片封裝結構包含第三成型層，其圍繞第一成型層、第二成型層、第一焊料凸塊、與第一導電柱，並填入間隙中。
在一些實施例中，上述晶片封裝結構之第一導電柱的厚度大於第一焊料凸塊的厚度。
在一些實施例中，上述晶片封裝結構更包括：導電通孔結構穿過第一成型層並電性連接至第二晶片結構；第二焊料凸塊位於間隙中；以及第二導電柱位於導電通孔結構與第二焊料凸塊之間。
在一些實施例中，上述晶片封裝結構更包括：再佈線層位於第二成型層第一成型層之間、位於第二晶片結構第一成型層之間、與位於第二晶片結構與第一晶片結構之間，其中導電通孔結構連接至再佈線層。
在一些實施例中，上述晶片封裝結構之再佈線層的側壁、第一成型層的側壁、與第二成型層的側壁共平面。
在一些實施例中，上述晶片封裝結構之第二晶片結構包含晶片、介電層、與導電墊，介電層位於晶片上，導電墊埋置於介電層中，且第二成型層之下表面、介電層之下表面、與導電墊之下表面共平面。
在一些實施例中，提供晶片封裝結構的形成方法，其包括：提供第一晶片結構於第一承載基板上。上述方法包括形成第一成型層以圍繞第一晶片結構。上述方法包括將第 二晶片結構置於第一晶片結構上。上述方法包括形成第二成型層以圍繞第二晶片結構。上述方法包括形成第一焊料凸塊於第二晶片結構上。上述方法包括移除第一承載基板。上述方法包括提供再佈線基板於第二承載基板上。上述方法包括經由第一焊料凸塊將第二晶片結構接合至再佈線基板。第二成型層與第二晶片結構均與再佈線基板之間隔有第一焊料凸塊，以定義間隙於第二成型層與第二晶片結構及再佈線基板之間。上述方法包括形成第三成型層於再佈線基板上，以圍繞第一成型層、第二成型層、與第一焊料凸塊，並填入間隙。上述方法包括移除第二承載基板。
在一些實施例中，上述形成晶片封裝結構的方法更包括：在形成第二成型層之後與形成第一焊料凸塊之前，形成導電柱於第二晶片結構上，其中第一焊料凸塊形成於導電柱上。
在一些實施例中，上述形成晶片封裝結構的方法，其中導電柱的組成為第一導電材料，第一焊料凸塊之組成為第二導電材料，且第一導電材料的熔點高於第二導電材料的熔點，且經由第一焊料凸塊將第二晶片接合至再佈線基板的步驟包括：將第一焊料凸塊置於再佈線基板上；以及在第一焊料凸塊上進行再流動製程，且再流動製程的溫度介於第一導電材料的熔點與第二導電材料的熔點之間。
在一些實施例中，上述形成晶片封裝結構的方法更包括：在形成第一成型層之後與放置第二晶片結構之前，形成導電通孔結構於第一晶片結構上，其中第二成型層亦圍繞導 電通孔結構。
在一些實施例中，上述形成晶片封裝結構的方法更包括：在形成第一焊料凸塊之步驟中，形成第二焊料凸塊於導電通孔結構上。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明。本技術領域中具有通常知識者應理解可採用本發明作基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本發明精神與範疇，並可在未脫離本發明之精神與範疇的前提下進行改變、替換、或更動。

Claims (1)

  1. 一種晶片封裝結構，包括：一再佈線基板；一第一晶片結構，位於該再佈線基板上；一第一焊料凸塊，配置於該再佈線基板與該第一晶片結構之間，並電性連接該再佈線基板與該第一晶片結構；一第一成型層，圍繞該第一晶片結構，其中該第一成型層與該第一晶片結構以及該再佈線基板之間隔有該第一焊料凸塊，以定義一間隙於該第一成型層與該第一晶片結構以及該再佈線基板之間；一第二晶片結構，位於該第一晶片結構上；一第二成型層，圍繞該第二晶片結構；以及一第三成型層，圍繞該第一成型層、該第二成型層、與該第一焊料凸塊，並填入該間隙中。
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