TWI720176B - 半導體結構及其製造方法 - Google Patents

半導體結構及其製造方法 Download PDF

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TWI720176B
TWI720176B TW106111903A TW106111903A TWI720176B TW I720176 B TWI720176 B TW I720176B TW 106111903 A TW106111903 A TW 106111903A TW 106111903 A TW106111903 A TW 106111903A TW I720176 B TWI720176 B TW I720176B
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Taiwan
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semiconductor die
conductive
layer
interconnection layer
substrate
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TW106111903A
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TW201743422A (zh
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鄭心圃
洪瑞斌
許峰誠
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台灣積體電路製造股份有限公司
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Abstract

本揭露提供一種製造一結構之方法。該方法包括：提供一基板；在該基板上方形成一互連層；在該互連層上方形成複數個導電墊；在該互連層上方形成導電柱；將一第一半導體晶粒放置於該等導電墊上方，該半導體晶粒與該等導電柱間隔開；及將一第二半導體晶粒與該等導電柱接合。

Description

半導體結構及其製造方法
本發明實施例係關於一種半導體結構及其製造方法。
涉及半導體裝置之電子設施對於諸多現代應用係必要的。材料及設計之技術進步已產生數代半導體裝置，其中各代具有比前一代更小且更複雜之電路。在進展及創新之過程中，功能密度(即，每晶片面積之互連裝置之數目)已大體上增加，而幾何大小(即，可使用一製程產生之最小組件)已減小。此等進步已增加處理及製造半導體裝置之複雜性。 隨著技術之演進，考慮到更小尺寸以及功能性及電路量之一增加，裝置之設計變得更為複雜。許多製造操作實施於此一小的且高效能的半導體裝置內。以一小型化規模製造一半導體裝置變得更為複雜，且製造複雜性之增加可引起不足，諸如高良率損失、電互連之不良可靠性、低測試涵蓋範圍等。因此，需持續修改電子設施中之裝置之結構及製造方法以改良裝置穩健性以及降低製造成本且減少處理時間。
在本發明之實施例中，一種製造一半導體封裝之方法包括：提供一基板；在該基板上方形成一互連層；在該互連層上方形成複數個導電墊；在該互連層上方形成導電柱；將一第一半導體晶粒放置於該等導電墊上方，該半導體晶粒與該等導電柱間隔開；及將一第二半導體晶粒與該等導電柱接合。 在本發明之實施例中，一種製造一半導體封裝之方法包括：提供一第一基板；在該第一基板上方形成一互連層；在該互連層上方形成複數個導電墊；將一第一半導體晶粒與該複數個導電墊接合；將一第二基板放置於與該第一基板相對之一側上在該第一半導體晶粒上方；自該互連層之一第一表面移除該第一基板；及在該第一表面上形成一連接件。 在本發明之實施例中，一種半導體封裝包括：一互連層：在該互連層上方之複數個導電柱：與該互連層接合之一第一半導體晶粒：與該互連層接合之一整合被動裝置，其中該整合被動裝置放置於該第一半導體晶粒之一相同側上：與該等導電柱接合之一第二半導體晶粒：及包圍該第一半導體晶粒及該整合被動裝置之一囊封材料。
優先權主張及交叉參考 本申請案主張2016年5月31日申請之美國專利申請案序號62/343,402之優先權，該案揭露之全文特此以引用的方式併入。 以下揭露提供用於實施所提供標的之不同特徵之許多不同實施例或實例。下文描述組件及配置之特定實例以簡化本揭露。當然，此等實例僅為實例且並不意欲為限制性的。例如，在下文描述中，一第一構件形成於一第二構件上方或上可包含其中第一構件及第二構件經形成而直接接觸之實施例，且亦可包含其中額外構件可形成於第一構件與第二構件之間使得第一構件及第二構件可未直接接觸之實施例。另外，本揭露可在各項實例中重複元件符號及/或字母。此重複係用於簡單及清楚之目的，且本身並不指示所論述之各種實施例及/或組態之間之一關係。 此外，為便於描述，本文中可使用空間相對術語(諸如「下面」、「下方」、「下」、「上方」、「上」及類似者)來描述一個元件或構件與另一(些)元件或構件之關係，如圖中所繪示。除圖中描繪之定向之外，空間相對術語亦意欲涵蓋裝置在使用或操作中之不同定向。設備可以其他方式定向(旋轉90度或成其他定向)，且因此可同樣解釋本文中使用之空間相對描述符。 本揭露提出一種半導體結構及其製造方法，其中一互連層(有時稱為佈線金屬層、重佈層)最初在晶粒與互連層之間之接合之前形成於一載體上方。繪示形成半導體封裝結構之中間階段。亦論述一些實施例之一些變動。貫穿各個視圖及實施例使用相似元件符號指定相似元件。 圖1A係根據本揭露之各種實施例之一半導體封裝結構100之一示意性透視圖。在一些實施例中，半導體封裝結構100係一層疊封裝(PoP)結構，其包含至少一或多個組件封裝或晶粒。在一些實施例中，半導體封裝結構100可包含與半導體晶粒電連接之離散主動組件或被動組件。根據一些實施例，半導體封裝結構100包含其中半導體晶粒或組件經堆疊且透過導電構件電連接之一整合扇出(InFO)結構。 參考圖1A，半導體封裝結構100包括一互連層120、一第一半導體晶粒132、一第二半導體晶粒140、整合被動裝置(IPD) 134及152、複數個導電柱130及複數個連接件144及150。 根據一些實施例，第一半導體晶粒132及第二半導體晶粒140可各自為一基板、一離散晶粒或一封裝裝置。根據一些實施例，第一半導體晶粒132及第二半導體晶粒140可各自包括一基板及互連層(或替代地稱為金屬層、重佈層等)或形成於各自基板上之選用主動裝置及被動裝置。根據一些實施例，第一半導體晶粒132及第二半導體晶粒140可各自包括具有囊封材料之一或多個組件晶粒或晶片。根據一些實施例，第一半導體晶粒132及第二半導體晶粒140可各自為包括導電凸塊、墊或接合導線之一封裝結構。 在一些實施例中，IPD 134可為一被動組件，諸如電容器、電感器、電阻器或類似者。在一些實施例中，IPD 134可包括一熔絲或反熔絲組件。儘管在本揭露各處使用術語「IPD」，然替代地可放置諸如一電源管理電路之一主動裝置來代替IPD 134或IPD 152。 互連層120經組態以電連接其之上覆組件，諸如第一半導體晶粒132、IPD 134或第二半導體晶粒140。另外，互連層120經組態以將上覆組件與連接件150或IPD 152電耦合。互連層120可包含多個金屬層。金屬層之各者可包含導線或導電線，且透過金屬通路電耦合至一鄰近上覆或下伏金屬層。在本實施例中，數個隔開的金屬線115放置於互連層120中且透過對應金屬通路114及124互連。在一些實施例中，金屬線115以及金屬通路114及124係由導電材料(諸如銅、銀、金或鎢)形成。互連層120之金屬層及通路之數目及圖案僅經提供用於繪示。金屬層、金屬通路或導線之其他數目及替代配線圖案亦在本揭露之預期範疇內。 此外，前述金屬層及金屬通路與其他組件電絕緣。絕緣可藉由絕緣材料達成。在一些實施例中，可用金屬間介電(IMD)層106及116填充互連層120之剩餘部分。IMD層106及116之介電材料可由氧化物(諸如無摻雜矽酸鹽玻璃(USG)、氟化矽酸鹽玻璃(FSG)、低介電係數材料或類似者)形成。低介電係數材料可具有低於3.8之k值，然而IMD 106/116之介電材料亦可接近於3.8。在一些實施例中，低介電係數材料之k值低於約3.0，且可低於約2.5。根據一些實施例，介電層106或116包括聚合物材料。 數個導電墊126放置於互連層120之各自金屬通路124上方。導電墊126可連接至一頂表面120B上之互連層120之暴露的金屬通路124。在一些實施例中，導電墊126之一子集接合至其他組件，諸如第一半導體晶粒132。在一些實施例中，導電墊126之一子集用作經組態以接收測試型樣之測試端子(即，測試墊)。 第一半導體晶粒132放置於互連層120上方。根據一些實施例，至少一個IPD 134在具第一半導體晶粒132之頂表面120B上接合至互連層120。根據一些實施例，至少一個IPD 134在與連接件150相對之表面120B上接合至之互連層120。根據一些實施例，至少一個IPD 152及第一半導體晶粒132在底表面120A處接合至互連層120。 根據一些實施例，IPD 134及第一半導體晶粒132具有不同高度。IPD 134具有自一頂表面134A至互連層120之頂表面120B量測之一第一高度，其不同於第一半導體晶粒132之一第二高度，其中該第二高度係自一頂表面132A至互連層120之頂表面120B量測。在一些實施例中，第一半導體晶粒132之第二高度大於IPD 134之第一高度。IPD 152可垂直放置於第一半導體晶粒132下方，使得其等之間之連接長度與為約數毫米之IPD 134與第一半導體晶粒132之間之互連相比可縮短至小於100 µm之一數量級。 導電柱130放置於互連層120上方。根據一些實施例，導電柱130接合至互連層120之頂表面120B。導電柱130可與第一半導體晶粒132或導電墊126間隔開。在一些實施例中，導電柱130可包含導電材料，諸如金、銀、鋁、鈦、銅、鎢、鎳、鉻及其等之一合金。在一些實施例中，導電柱130具有大於第一半導體晶粒132之第一高度之一第三高度。在一些實施例中，導電柱130之第三高度大於IPD 134之第二高度。對於不同應用，第三高度可不同。根據一些實施例，第三高度介於約200 μm與約250 μm之間。 第二半導體晶粒140放置於互連層120上方。在一些實施例中，第一半導體晶粒132配置於互連層120與第二半導體晶粒140之間。第二半導體晶粒140透過導電柱130接合至互連層120。在本實施例中，第二半導體晶粒140包括面向互連層120之複數個導電墊142。導電墊142可與各自導電柱130對準且透過連接件144電連接至各自導電柱130。 連接件144放置於導電柱130與第二半導體晶粒140之間。另外，連接件150放置成鄰近於互連層120之一底表面120A。連接件144或150可為接點凸塊，諸如受控倒疊晶片連接(C4)凸塊、球柵陣列凸塊或微凸塊。連接件144及150可包括一導電材料，諸如錫、銅、金或銀。 在半導體封裝結構100中，一囊封材料136填充第一半導體晶粒132、互連層120、IPD 134及導電柱130之中的空間。根據一些實施例，囊封材料136可為一模塑料或成型底膠材料。根據一些實施例，囊封材料136經組態以包圍第一半導體晶粒132及IPD 134。在一些實施例中，第一半導體晶粒132之一頂表面132A自囊封材料136暴露。根據一些實施例，囊封材料136填充第一半導體晶粒132與互連層120之間之一空間。囊封材料136可為一模塑料樹脂，諸如聚醯亞胺、PPS、PEEK、PES、一耐熱晶體樹脂或其等之組合。 在一些實施例中，另一囊封材料148囊封第二半導體晶粒140。根據一些實施例，囊封材料148可橫向包圍第二半導體晶粒140。根據一些實施例，囊封材料148填充第一半導體晶粒132與第二半導體晶粒140之間之一間隙。在一些實施例中，囊封材料148之一側壁邊緣與囊封材料136之一側壁邊緣對準。在一些實施例中，囊封材料148或136之一側壁邊緣與互連層120之一側壁邊緣對準。囊封材料148可為一模塑料樹脂，諸如聚醯亞胺、PPS、PEEK、PES、一耐熱晶體樹脂或其等之組合。在一些實施例中，囊封材料148可包括與囊封材料136相同之一材料。 圖1B係根據本揭露之各種實施例之圖1A中之半導體封裝結構100中之一頂表面120B之一剖面俯視圖。參考圖1B，如從頂表面120B所觀察，互連層120之一最上子層包括導電墊126及IMD材料116。如先前論述，在一些實施例中，導電墊之一子集(例如墊126A)組態為測試墊以接收測試型樣。根據一些實施例，導電墊126B/126C分別組態為連接至一電源電壓位準或一接地電壓位準之一電源端子或一接地端子。在一些實施例中，導電墊之一些者(諸如126B)形成分佈於鄰近於表面120B之一頂層處之一網狀佈局。網狀佈局包括比形成於對應晶粒(諸如第一半導體晶粒132)之一表面上之一現有網狀佈局大之一層面積。因此，可獲得一更佳電屏蔽效應。 圖2A至圖2R係根據一些實施例之用於製造圖1A中之一半導體封裝結構之一方法之中間結構之剖面圖。圖2A至圖2R中展示之操作亦示意性地繪示於圖3中展示之製程流程300中。 在圖2A中，接收或提供一基板102。各自操作展示為圖3中之製程流程300之操作302。基板102可為一載體基板。基板102可包括例如矽基材料，諸如玻璃或氧化矽；氧化鋁、陶瓷材料或其等之組合。載體基板102包括一平坦頂表面，其上可附接半導體組件，諸如一半導體晶粒或IPD。 接著，一黏著層104形成於基板102上方。各自操作展示為圖3中之製程流程300之操作304。黏著層104經組態以幫助基板102與上覆層之間之黏著。在一些實施例中，黏著層104可包括紫外線膠，當暴露於紫外光時，紫外線膠之黏著強度將劣化。根據一些實施例，黏著層104包括其他類型之黏著劑，諸如壓敏黏著劑、可輻射固化黏著劑、環氧樹脂或其等之組合。黏著層104可以一半液體或凝膠形式施配且在一外部壓力下可變形。 在一些實施例中，一額外聚合物層(未單獨展示)可視情況放置於黏著層104上方。當在後續操作中移除黏著層104之一部分時，該聚合物層用於保護上覆裝置(諸如一半導體晶粒)免受損壞。或者，此額外聚合物層可視為一隨後形成之互連層之一初始聚合物子層。在一些實施例中，聚合物層可為一保護材料，諸如聚苯并㗁唑(PBO)、聚醯亞胺(PI)、苯環丁烯(BCB)、氧化矽、氮化矽、氮氧化矽或任何其他適合保護材料。聚合物層可使用一旋塗製程或一沈積製程(例如，化學氣相沈積)或其他適合製程形成。在一些實施例中，聚合物層可形成為介於約1 μm與約100 μm之間(諸如約20 μm)之一厚度。在一些實施例中，聚合物層替代地由一介電材料形成。 參考圖2B至圖2F，一互連層形成於黏著層104上方。各自操作展示為圖3中之製程流程300之操作306。互連層可包括介電材料及導電連接之交替層，其中包括金屬線或導線且橫向延伸之導電連接由垂直延伸之金屬通路互連。在圖2B中，最初一圖案化介電層106形成於黏著層104上方。圖案化介電層106可藉由多種技術形成，例如，化學氣相沈積(CVD)、低壓CVD (LPCVD)、電漿輔助CVD (plasma-enhanced CVD，PECVD)、濺鍍及物理氣相沈積(PVD)、熱生長及類似者。圖案化介電層106可由多種介電材料形成，且可為例如氧化物(例如，Ge氧化物)、氮氧化物(例如，GaP氮氧化物)、二氧化矽(SiO2 )、含氮氧化物(例如，含氮SiO2 )、氮摻雜氧化物(例如，N2 植入SiO2 )、氮氧化矽(Six Oy Nz )、聚合物材料及類似者。一光阻劑(未展示)圖案化於介電層106上方以形成通孔103。在通孔103形成之後剝離光阻劑。 參考圖2C，一晶種層108沈積於圖案化介電層106上方。晶種層108係有利於形成互連層120之導電構件之一導電材料之一薄層。在一些實施例中，晶種層108可包括鈦子層其其後接著著銅子層。晶種層108可使用一適合製程(諸如濺鍍、蒸鍍或沈積)形成。在一些實施例中，晶種層108毯覆於介電層106上方。 一旦晶種層108經構造，便將一遮罩層112放置於晶種層108上方以幫助形成互連層120中之其他導電構件。遮罩層112可為一光阻層或一硬遮罩層，諸如氮化矽。遮罩層112可藉由多種技術形成，例如，CVD、LPCVD、PECVD、濺鍍、PVD及類似者。 在圖2D中，導電通路114形成於通孔103中，其中遮罩層112係圖案化遮罩。此外，導電線115經形成以連接導電通路114且在晶種層108上方橫向延伸。導電通路114及導電線115包括一或多種導電材料(諸如銅、鎢或其他導電金屬)，且可藉由電鍍、無電式電鍍或任何適合製程形成。一旦導電通路114及導電線115已形成，此後便可移除遮罩層112。此外，藉由例如一蝕刻製程移除在介電層106上方的雖然暴露但未由導電通路114或導電線115覆蓋之晶種層108之一部分以暴露介電層106。因此，暴露介電層106之頂表面之一部分(諸如標記為106A之部分)。 參考圖2E，隨後一第二介電層116及一第二晶種層118形成於介電層106、導電通路114及導電線115上方。第二介電層116可在介電層106之頂表面之部分106A處與介電層106接觸。在一些實施例中，介電層116可部分覆蓋導電線115。用於第二介電層116及第二晶種層118之材料及形成製程分別與應用於介電層106及晶種層108之材料及形成製程類似，且為簡單起見將不再重複。 在一些實施例中，一圖案化光阻層(未單獨展示)放置於介電層116上方以形成通孔113及117。一旦通孔113及117經形成，便可剝離圖案化光阻層。在一些實施例中，晶種層108可形成為放置於介電層116及導電線115上方且襯於通孔113及117之一毯覆層。接著，另一圖案化光阻層122形成於晶種層118上方，其中通孔113自圖案化光阻劑122暴露而通孔117被覆蓋。 在圖2F中，藉由在暴露的通孔113中填充導電材料(諸如銅或鎢)而形成導電通路124。導電通路124可使用一適合製程(諸如電化學電鍍、無電式電鍍、濺鍍或沈積)形成。在本揭露各處，包括導電構件114、115、124、介電層106及116及選用晶種層108及118之複合結構稱為互連層120。 隨後，導電墊126形成於互連層120之各自導電通路124上方。在一些實施例中，導電墊126係由一導電材料(諸如鋁、銅、鎢或類似者)形成。各自操作展示為圖3中之製程流程300之操作308。導電墊126可使用諸如CVD或PVD之一製程形成，然而可替代地利用其他適合材料及方法。在導電材料已形成之後，形成導電墊126可進一步涉及一移除操作(諸如使用一蝕刻製程)以移除圖案化光阻劑122。 參考圖2G，另一圖案化光阻層128形成於導電墊126及晶種層118上方。一些通孔(諸如通孔117)向上延伸穿過光阻層128，因此通孔117自光阻層128暴露。另外，與通孔117間隔開之一些通孔(諸如通孔123)亦形成於圖案化光阻劑128中。通孔123自先前通孔117偏移且比通孔117淺。在一些實施例中，光阻層128可替代地由一乾膜形成。 在圖2H中，導電柱130形成於晶種層118上方及各自通孔117及123中。各自操作展示為圖3中之製程流程300之操作310。一旦導電柱130經形成，便移除圖案化光阻層128。 參考圖2H，一些導電柱130形成於介電層116上方，一晶種層118放置於其等之間。又，一些導電柱130形成於導電線115上方，一晶種層118放置於其等之間。此外，在移除圖案化光阻層128之後，亦移除在介電層116上方橫向延伸但未由導電柱130覆蓋晶種層118之一暴露部分。在一些實施例中，保留垂直延伸之晶種層118之一部分，該部分襯於介電層116中之通孔117之側壁。在一些實施例中，保留襯於通孔117之底部之晶種層118之一部分。在一些實施例中，藉由移除上覆晶種層118而暴露未由導電柱130覆蓋之介電層116之一部分。在一些實施例中，襯於通孔117之側壁之晶種層118之一部分與介電層116之一頂表面116A共面。 導電柱130可包括不同長度。例如，與導電線115電連接且延伸至介電層116導電柱130 (展示為較接近封裝結構之中心)可具有大於立於介電層116上之該等導電柱130 (展示為較接近封裝結構之邊緣)之一長度。在一些實施例中，導電柱130在頂層處實質上共面而與其等之長度無關。 參考圖2I，在此圖及後續圖中繪示半導體封裝結構100之中間階段，其中簡化互連層120之細節。在完成互連層120後，針對互連層120執行一第一完整性測試。在一些實施例中，在缺乏其他互連裝置(諸如圖1A中之第一半導體晶粒132及第二半導體晶粒140)之情況下，第一完整性測試被視為對於半導體封裝結構100之一部分測試。可藉由透過輸入端子(諸如圖1A中之測試墊126)輸入測試型樣而執行第一完整性測試，以識別互連層120之缺陷結構(例如，短路或開路)。因而，在附接第一半導體晶粒132、IPD 134及152或第二半導體晶粒140之前，集中於互連層120之一前瞻式測試可有助於降低互連層120中之製造故障之可能性。因此可節省良好半導體晶粒132及140附接至互連層120中之故障單元之成本。 若通過第一完整性測試，則如圖2J中繪示，至少一個第一半導體晶粒132放置於互連層120上方。各自操作展示為圖3中之製程流程300之操作312。在一些實施例中，第一半導體晶粒132包括接合至互連層120之一些導電墊126 (為簡單起見未單獨展示，但於圖1A中繪示)之導電凸塊。另外，至少一個IPD 134 (其等與接合至第一半導體晶粒132之導電墊126間隔開)透過一些其他導電墊126放置於互連層120上方且接合至互連層120。IPD 134放置於導電柱130與第一半導體晶粒132之間。在一些實施例中，IPD 134及半導體晶粒132之厚度實質上不同。根據本揭露之互連層第一方法實現具有不同厚度之組件於相同封裝中之靈活整合。 參考圖2K，一旦第一半導體晶粒132及IPD 134在適當位置中，便針對互連層120、第一半導體晶粒132及IPD 134之互連結構執行一第二完整性測試。在一些實施例中，在缺乏其他互連裝置(諸如第二半導體晶粒140)之情況下，第二完整性測試被視為對於半導體封裝結構100之一部分測試。然而，由於已完成更多連接及接合結構，故第二完整性測試可提供比第一完整性測試更全面之一測試涵蓋範圍。以第一完整性測試之一類似方法，集中於互連層120、第一半導體晶粒132及IPD 134之前瞻式第二測試將有助於預先偵測可能連接故障，且因此可節省良好晶粒140附接至封裝結構100中之故障單元之成本。 在圖2L中，回應於通過第二完整性測試，一囊封材料136囊封或包圍第一半導體晶粒132。在一些實施例中，囊封材料136包圍導電柱130及IPD 134。各自操作展示為圖3中之製程流程300之操作314。囊封製程可在一模製裝置(未個別展示)中執行。例如，圖2K中之中間半導體封裝結構100可放置於模製裝置之一腔內。接著囊封材料136可在腔被氣密密封之前施配於腔內，或替代地可透過一注射口注射至密封腔中。 一旦囊封材料136已形成，便可執行一薄化或平坦化製程以移除過量囊封材料136。可使用一機械研磨或化學機械拋光(CMP)製程來執行薄化以使囊封材料136之一頂表面平整。另外，第一半導體晶粒132之一頂表面132A自囊封材料136暴露。此外，導電柱130之各者之一頂部自囊封材料136暴露。 在圖2M中，接收或提供第二半導體晶粒140。接著將第二半導體晶粒140放置於囊封材料136上方。接著將第二半導體晶粒140接合至各自導電柱130。各自操作展示為圖3中之製程流程300之操作316。在一些實施例中，第二半導體晶粒140之各者包括透過連接件144接合至各自導電柱130之導電墊142。 參考圖2N，將一囊封材料148施覆至第二半導體晶粒140。囊封材料148囊封或包圍第二半導體晶粒140之各者。各別操作在圖3中展示為製程流程300之操作318。根據一些實施例，囊封材料148橫向包圍各第二半導體晶粒140。根據一些實施例，囊封材料148填充鄰近第二半導體晶粒140之間之一間隙。根據一些實施例，囊封材料148填充第一半導體晶粒132與其等對應第二半導體晶粒140之間之一間隙。在一些實施例中，囊封材料148填充第二半導體晶粒140與囊封材料136之間之一間隙。根據一些實施例，囊封材料148包圍連接件144且覆蓋囊封材料136之頂表面。在一些實施例中，囊封材料148覆蓋第一半導體晶粒132之頂表面132A且與其接觸。 在圖2O中，半導體封裝結構100經倒置。自黏著層104移除基板102。各自操作展示為圖3中之製程流程300之操作320。根據一些實施例，使黏著層104暴露於一能源，諸如紫外(UV)光，使得黏著性劣化且基板102自半導體封裝結構100釋離。一旦基板102與半導體封裝結構110分離，便亦將黏著層104移除。因此，與第一半導體晶粒132相對之互連層120之一表面120A暴露。 在圖2P中，自表面120A移除互連層120之一上部分使得互連層120變薄。一導電部分(諸如導電通路114，未單獨展示但於圖1A中繪示)自互連層120之表面120A暴露。根據一些實施例，可藉由使用一蝕刻操作(諸如一乾式蝕刻或濕式蝕刻操作)而薄化互連層120。 在圖2Q中，連接件150形成於互連層120之表面120A上。各自操作展示為圖3中之製程流程300之操作322。在一些實施例中，一錫層最初可藉由任何適合方法(諸如蒸鍍、電鍍、列印、焊料轉移或植球)形成於互連層120上。在已形成錫層之後，如所需般在焊接材料待塑形之處執行一回焊操作。在一些實施例中，連接件150形成於一側120A上，側120A與第一半導體晶粒132所附接之側120B相對。根據一些實施例，至少一個IPD 152放置於互連層120上方。IPD 152連同互連層120之一相同側上之連接件150一起接合至一些導電通路114 (未單獨展示)。在一些實施例中，一些IPD 152放置於一側120A上，側120A與第一半導體晶粒132所附接之側120B相對。在一些實施例中，IPD 152與各自第一半導體晶粒132對準。在一些實施例中，放置於相對側上之IPD 152之各者及IPD 134之各者配置於脫位位置中使得其等跨互連層120彼此未對準。 在考慮到不同需求及應用時，考量放置IPD 134及IPD 152之位置。例如，IPD 152以一減小的互連長度與第一半導體晶粒132垂直對準。因此，可改良電性質及製造成本。然而，當需要一IPD (諸如一IPD 134)與第一半導體晶粒132及第二半導體晶粒140協同運作時，較佳可將IPD 134安置於第一半導體晶粒132之相同側上以減小兩個半導體晶粒132與140之間之佈線長度。此外，第一半導體晶粒132之橫向側上之備用空間可容納額外組件。因此，歸因於較少IPD佔據用於連接件150之空間，連接件150之安置密度可增加，而使封裝結構100更緊湊。在一些實施例中，儘管第一半導體晶粒132及IPD 134可具有不同高度，然其等兩者可皆接合至互連層120之一相同側(即，表面120B上)。 在圖2R中，執行一切割或單粒化操作。各自操作展示為圖3中之製程流程300之操作324。根據一些實施例，使用一刀片160執行單粒化。根據一些實施例，使用一雷射160執行單粒化操作。在一些實施例中，對於離散封裝晶粒100-1及100-2之各者，作為單粒化操作之一結果，囊封材料136之一側壁邊緣136A與囊封材料148之一側壁邊緣148A共面。 圖2A至圖2M其後接著圖4A至圖4E係根據一些實施例之製造一半導體封裝結構之另一方法之中間結構之剖面圖。圖2A至圖2M其後接著圖4A至圖4E中展示之操作亦示意性地繪示於圖5中展示之製程流程500中。在後續論述中，為簡單起見，省略圖2A至圖2M中展示之操作(對應於操作302至操作316)，而參考圖5中之對應操作論述圖4A至圖4E。 參考圖4A，一囊封材料402填充第一半導體晶粒132與對應第二半導體晶粒140之間之間隙。各自操作展示為圖5中之製程流程500之操作502。囊封材料402可為一模塑料樹脂，諸如聚醯亞胺、PPS、PEEK、PES、一耐熱晶體樹脂或其等之組合。在一些實施例中，囊封材料402可與囊封材料136或148相同。操作308與操作502之間之差異可在於：在當前實施例之製程流程500中，囊封材料402將施覆至第一半導體晶粒132與第二半導體晶粒140之間之間隙。在一些實施例中，囊封材料402填充第二半導體晶粒140與囊封材料136之間之一間隙。在一些實施例中，囊封材料402包圍導電墊142及連接件144。第二半導體晶粒140之其他表面(諸如頂表面或橫向表面)將未由囊封材料402覆蓋。 在圖4B中，移除基板102及黏著層104。圖4B之各自操作展示為圖5中之製程流程500之操作504，操作504類似於圖3中之操作320。與操作320相比，操作504之差異可歸因於引入一帶以承載半導體封裝結構100之事實。根據一些實施例，亦可利用由剛性材料製成之一框架來固持該帶且支撐半導體封裝結構100。在本實施例中，尚未完成之封裝結構100之剛性可能不足以抵抗外部應力。在後續製程期間，框架連同帶可有助於增加半導體封裝結構100之剛性。 圖4C、圖4D及圖4E中之操作分別類似於圖2P、圖2Q及圖2R中之操作。各自操作展示為圖5中之製程流程500之操作506及508。圖4C至圖4E相較於圖2P至圖2Q之主要差異在於引入帶及(視情況)框架以支撐半導體封裝結構100。 圖2A至圖2L其後接著圖6A至圖6F係根據一些實施例之製造一半導體封裝結構之又一方法之中間結構之剖面圖。在後續論述中，為簡單起見，省略圖2A至圖2L中展示之操作(對應於操作302至操作314)，而參考圖7中之對應操作論述圖6A至圖6F。另外，在圖7之操作302、304或306中使用之術語「基板」及「黏著層」分別由術語「第一基板」及「第一黏著層」取代，以與如稍後將介紹之其他操作中之一第二基板及一第二黏著層區分。 參考圖6A，一第二黏著層602形成於第一半導體晶粒132及囊封材料136上方。接著，一第二基板604放置於第二黏著層602上方。第二基板604透過第二黏著層602接合至囊封材料136。圖6A之各自操作展示為圖7中之製程流程700之操作702。根據一些實施例，第二黏著層602可包括類似於圖2A中之(第一)黏著層104之一材料。根據一些實施例，第二基板604可包括類似於圖2A中之(第一)基板102之一材料。 一旦第二基板604接合至囊封材料136，第一基板102及第一黏著層104便自半導體封裝結構100釋離。圖6B之各自操作展示為圖7中之製程流程700之操作704。 在圖6C中，連接件150及IPD 152形成於互連層120上方。圖6C之各自操作展示為圖7中之製程流程700之操作706。用於形成連接件150及IPD 152之材料及製程類似於關於圖2P及圖2Q或替代地圖4C及圖4D描述且繪示之材料及製程。 隨後，在圖6D中，移除第二基板604及第二黏著層602。圖6D之各自操作展示為圖7中之製程流程700之操作708。此外，半導體封裝結構100安置於一帶404上。根據一些實施例，向下薄化囊封材料136使得導電柱130暴露。 參考圖6E，提供第二半導體晶粒140且將其接合至導電柱130。圖6E之各自操作展示為圖7中之製程流程700之操作710。在一些實施例中，第二半導體晶粒140僅透過連接件144與導電柱130接觸。在一些實施例中，未利用囊封材料包圍連接件144。 參考圖6F，執行一切割或單粒化操作。圖6F之各自操作展示為圖7中之製程流程700之操作712。用於形成連接件150及IPD 152之材料及製程類似於關於圖2R之描述且繪示之材料及製程。 其中最初形成互連層且其後接著組件晶粒之接合製程之所提出的結構及方法包含數種優點。製造商可在製造封裝結構之中間階段中執行更多輪之完整性測試。因此，可在附接組件晶粒之前偵測連接故障(例如，短路或開路)。可節省將良好晶粒與故障互連層接合所招致之成本。 另外，此提議可將具有不同厚度或高度之晶粒容納於互連層之一相同側上。此外，可同時執行組件晶粒及互連層之製程，且一旦完成便組合組件晶粒及互連層。可進一步縮減製造週期。 與現有方法相比，根據一些實施例之組件晶粒可經歷較少熱預算。可有效地減輕現有囊封操作中常見之晶粒位移問題。此外，在將IPD整合至封裝結構中時，在選擇接合位置方面達到一較大靈活性，因此增強電效能且減小佔據面積。又，組件晶粒可堆疊且接合於具有一較佳平坦度之一載體基板(諸如一基於玻璃之載體)上方。生產良率因此增加。 本揭露提供一種製造一結構之方法。該方法包括：提供一基板；在該基板上方形成一互連層；在該互連層上方形成複數個導電墊；在該互連層上方形成導電柱；將一第一半導體晶粒放置於該等導電墊上方，該半導體晶粒與該等導電柱間隔開；及將一第二半導體晶粒與該等導電柱接合。 本揭露提供一種製造一結構之方法。該方法包括：提供一第一基板；在該第一基板上方形成一互連層；在該互連層上方形成複數個導電墊；將一第一半導體晶粒與該複數個導電墊接合；將一第二基板放置於與該第一基板相對之一側上在該第一半導體晶粒上方；自該互連層之一第一表面移除該第一基板；及在該第一表面上形成一連接件。 本揭露提供一種結構。該結構包括一互連層及該互連層上方之複數個導電柱。該結構亦包括與該互連層接合之一第一半導體晶粒及與該互連層接合之一整合被動裝置，其中該整合被動裝置放置於該第一半導體晶粒之一相同側上。另外，該結構包括與該等導電柱接合之一第二半導體晶粒，及包圍該第一半導體晶粒及該整合被動裝置之一囊封材料。 前文概述數種實施例之特徵使得熟習此項技術者可更佳理解本揭露之態樣。熟習此項技術者應瞭解，其等可容易使用本揭露作為設計或修改其他製程及結構之一基礎以實行本文介紹之實施例之相同目的及/或達成相同優點。熟習此項技術者亦應認識到，此等等效構造不脫離本揭露之精神及範疇，且其等可在不脫離本揭露之精神及範疇之情況下進行各種改變、置換及更改。
100‧‧‧半導體封裝結構100-1‧‧‧封裝晶粒100-2‧‧‧封裝晶粒102‧‧‧基板/第一基板103‧‧‧通孔104‧‧‧黏著層/第一黏著層106‧‧‧金屬間介電(IMD)層/圖案化介電層106A‧‧‧介電層頂表面之部分108‧‧‧晶種層112‧‧‧遮罩層113‧‧‧通孔114‧‧‧金屬通路/導電通路/導電構件115‧‧‧金屬線/導電線/導電構件116‧‧‧金屬間介電(IMD)層/金屬間介電(IMD)材料/第二介電層116A‧‧‧介電層之頂表面117‧‧‧通孔118‧‧‧第二晶種層120‧‧‧互連層120A‧‧‧互連層之底表面/側120B‧‧‧互連層之頂表面/側122‧‧‧圖案化光阻層/圖案化光阻劑123‧‧‧通孔124‧‧‧金屬通路/導電通路/導電構件126‧‧‧導電墊/測試墊126A‧‧‧墊126B‧‧‧導電墊126C‧‧‧導電墊128‧‧‧圖案化光阻層/圖案化光阻劑130‧‧‧導電柱132‧‧‧第一半導體晶粒132A‧‧‧第一半導體晶粒之頂表面134‧‧‧整合被動裝置(IPD)134A‧‧‧整合被動裝置(IPD)之頂表面136‧‧‧囊封材料136A‧‧‧囊封材料之側壁邊緣140‧‧‧第二半導體晶粒142‧‧‧導電墊144‧‧‧連接件148‧‧‧囊封材料148A‧‧‧囊封材料之側壁邊緣150‧‧‧連接件152‧‧‧整合被動裝置(IPD)160‧‧‧刀片/雷射300‧‧‧製程流程302‧‧‧操作304‧‧‧操作306‧‧‧操作308‧‧‧操作310‧‧‧操作312‧‧‧操作314‧‧‧操作316‧‧‧操作318‧‧‧操作320‧‧‧操作324‧‧‧操作402‧‧‧囊封材料404‧‧‧帶500‧‧‧製程流程502‧‧‧操作504‧‧‧操作506‧‧‧操作508‧‧‧操作602‧‧‧第二黏著層604‧‧‧第二基板700‧‧‧製程流程702‧‧‧操作704‧‧‧操作706‧‧‧操作708‧‧‧操作710‧‧‧操作712‧‧‧操作
當結合附圖閱讀時，自以下[實施方式]最佳理解本揭露之態樣。應注意，根據產業中之標準實踐，各個構件未按比例繪製。事實上，為清楚論述，可任意增大或減少各個構件之尺寸。 圖1A係根據本揭露之各種實施例之一半導體封裝結構之一示意圖。 圖1B係根據本揭露之各種實施例之圖1A中之半導體封裝結構之一剖面俯視圖。 圖2A至圖2R係根據各種實施例之製造圖1A中之半導體封裝結構之一方法之中間結構之剖面圖。 圖3係根據一些實施例之製造圖2A至圖2R中之一半導體封裝結構之一流程圖。 圖4A至圖4E係根據各種實施例之製造一半導體封裝結構之一方法之一些中間結構之剖面圖。 圖5係根據一些實施例之製造圖2A至圖2M及圖4A至圖4E中之一半導體封裝結構之一流程圖。 圖6A至圖6F係根據各種實施例之製造一半導體封裝結構之一方法之一些中間結構之剖面圖。 圖7係根據一些實施例之製造圖2A至圖2L及圖6A至圖6F中之一半導體封裝結構之一流程圖。
100‧‧‧半導體封裝結構
106‧‧‧金屬間介電(IMD)層/圖案化介電層
114‧‧‧金屬通路/導電通路/導電構件
115‧‧‧金屬線/導電線/導電構件
116‧‧‧金屬間介電(IMD)層/金屬間介電(IMD)材料/第二介電層
120‧‧‧互連層
120A‧‧‧互連層之底表面/側
120B‧‧‧互連層之頂表面/側
124‧‧‧金屬通路/導電通路/導電構件
126‧‧‧導電墊/測試墊
130‧‧‧導電柱
132‧‧‧第一半導體晶粒
132A‧‧‧第一半導體晶粒之頂表面
134‧‧‧整合被動裝置(IPD)
134A‧‧‧整合被動裝置(IPD)之頂表面
136‧‧‧囊封材料
140‧‧‧第二半導體晶粒
142‧‧‧導電墊
144‧‧‧連接件
148‧‧‧囊封材料
150‧‧‧連接件
152‧‧‧整合被動裝置(IPD)

Claims (10)

  1. 一種製造一半導體封裝之方法，該方法包括：提供一基板；在該基板上方形成一互連層；在該互連層上方形成複數個導電墊，該等導電墊包括測試墊；透過該測試墊執行對該互連層之第一測試；回應於該互連層通過該第一測試而在該互連層上方形成導電柱；將一第一半導體晶粒放置於該等導電墊上方，該第一半導體晶粒與該等導電柱間隔開；將一第二半導體晶粒與該等導電柱接合；及薄化該互連層以暴露該互連層之導電部分。
  2. 如請求項1之方法，其進一步包括在形成該互連層之前在該基板上方提供黏著層。
  3. 一種製造半導體封裝之方法，該方法包括：提供第一基板；在該第一基板上方形成互連層；在該互連層上方形成多個導電墊，該多個導電墊包括至少一個測試墊；透過該測試墊執行對該互連層之第一測試；回應於該互連層通過該第一測試而將第一半導體晶粒與該多個導 電墊接合；在與該第一基板相對之一側上將第二基板放置於該第一半導體晶粒上方；自該互連層之第一表面移除該第一基板；及在該第一表面上形成連接件。
  4. 一種製造半導體封裝之方法，該方法包括：提供第一基板；在該第一基板上方形成互連層；在該互連層上方形成多個導電墊，該多個導電墊包括測試墊；透過該等測試墊執行對該互連層之第一測試；回應於該互連層通過該第一測試而將第一半導體晶粒與該多個導電墊接合；以囊封材料囊封該第一半導體晶粒及該多個導電墊；及將第二半導體晶粒與該經囊封第一半導體晶粒接合。
  5. 一種製造半導體封裝之方法，該方法包括：提供基板；在該基板上方形成黏著層；在該黏著層上方形成包括金屬線及金屬通孔之互連層；在該互連層上方形成多個導電墊，該多個導電墊包括測試墊；透過該測試墊執行對該互連層之第一測試；回應於該互連層通過該第一測試而在該互連層上方形成導電柱； 將第一半導體晶粒放置於該等導電墊上方，該第一半導體晶粒與該等導電柱間隔開；將第二半導體晶粒與該等導電柱接合；及移除該基板及該黏著層以暴露該互連層之導電部分。
  6. 一種製造半導體封裝之方法，該方法包括：提供第一基板；在該第一基板上方形成互連層；在該互連層上方形成多個導電墊，該多個導電墊包括至少一個測試墊；透過該測試墊執行對該互連層之第一測試；回應於該互連層通過該第一測試而將第一半導體晶粒與該多個導電墊接合；在與該第一基板相對之一側上將第二基板放置於該第一半導體晶粒上方；自該互連層之第一表面移除該第一基板；薄化該互連層以暴露該互連層之導電部分；及在該第一表面上形成連接件。
  7. 一種製造半導體封裝之方法，該方法包括：提供第一基板；在該第一基板上方形成包括金屬線及金屬通孔之互連層；在該互連層上方形成多個導電墊及多個導電柱，該多個導電墊包 括測試墊；透過該等測試墊執行對該互連層之第一測試；回應於該互連層通過該第一測試而將第一半導體晶粒與該多個導電墊接合；以囊封材料囊封該第一半導體晶粒、該多個導電墊及該多個導電柱；及將該第二半導體晶粒與該經囊封第一半導體晶粒接合。
  8. 一種半導體封裝，其包括：互連層，其包括配置為接合墊之第一導電墊及配置為測試墊之第二導電墊；多個導電柱，其等在該互連層上方；第一半導體晶粒，其透過該第一導電墊接合至該互連層；整合被動裝置，其透過該第一導電墊接合至該互連層，該整合被動裝置及該第一半導體晶粒放置於該互連層之相同側上；第二半導體晶粒，其電耦合至該等導電柱；第一囊封材料，其包圍該第一半導體晶粒、該整合被動裝置及該等導電柱，該等導電柱之各者之一頂部自該第一囊封材料暴露；及第二囊封材料，其包圍該第二半導體晶粒且覆蓋該第一囊封材料之頂表面。
  9. 一種半導體封裝，其包括：互連層； 多個導電柱，其等在該互連層上方；第一半導體晶粒，其與該等導電柱間隔開且接合至該互連層；第二半導體晶粒，其與該第一半導體晶粒及該等導電柱間隔開且接合至該互連層；第三半導體晶粒，其電耦合至該等導電柱；及第一介電材料，其囊封該第一半導體晶粒及該第二半導體晶粒，該第一介電材料覆蓋該第二半導體晶粒之上部表面且暴露該第一半導體晶粒之上部表面。
  10. 一種半導體封裝，其包括：互連層；多個導電柱，其等在該互連層上方；第一半導體晶粒，其與該等導電柱間隔開且接合至該互連層；第二半導體晶粒，其與該第一半導體晶粒及該等導電柱間隔開且接合至該互連層；連接件，其等在該等導電柱上方；第三半導體晶粒，其透過該等連接件電耦合至該等導電柱；介電材料，其囊封該第一半導體晶粒及該第二半導體晶粒，該介電材料覆蓋該第二半導體晶粒之上部表面且暴露該第一半導體晶粒之上部表面；及整合被動裝置，其在與該第一半導體晶粒相對之一側上接合至該互連層，該整合被動裝置與該第一半導體晶粒重疊。
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