TWI714120B - 封裝層電感器 - Google Patents

封裝層電感器 Download PDF

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Publication number
TWI714120B
TWI714120B TW108120157A TW108120157A TWI714120B TW I714120 B TWI714120 B TW I714120B TW 108120157 A TW108120157 A TW 108120157A TW 108120157 A TW108120157 A TW 108120157A TW I714120 B TWI714120 B TW I714120B
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Taiwan
Prior art keywords
dielectric layer
layer
inductor
chip
metal
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TW108120157A
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TW202002183A (zh
Inventor
艾倫 羅斯
艾力克 蘇寧
徐英智
尼克 薩姆拉
斯帝芬 魯蘇
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台灣積體電路製造股份有限公司
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Publication of TWI714120B publication Critical patent/TWI714120B/zh

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Abstract

一電感器形成於一積體電路(IC)裝置封裝結構中。該結構包含一囊封材料，其中一鐵磁心位於該囊封材料中。將複數個金屬層提供於該囊封材料中以形成圍繞該鐵磁心延伸之一電感器線圈來形成一電感器。

Description

封裝層電感器
本發明實施例係有關封裝層電感器。
磁性電感器用於諸多電器應用中。例如，一電壓調節器將一輸入電壓轉換成一不同輸出電壓。電源管理係各種積體電路應用中之一必要功能。一典型積體電路(IC)可包含由形成於一半導體晶粒上之大量互連組件形成之各種系統，且此等整合系統之電力需求可大不相同。
在一些電壓調節器中，一切換裝置之工作週期判定將多少電力輸出至一負載。脈寬調變控制輸出電壓之平均值。電壓調節器之輸出連接至充當一能量儲存元件之一電感器。諸多電壓調節器配置可用作IC，但電感器通常為連接至電源調節器IC之一離散組件。
本發明的一實施例揭露一種結構，其包括：一囊封材料；一鐵磁心，其位於該囊封材料中；複數個金屬層，其等位於該囊封材料中以形成圍繞該鐵磁心延伸之一電感器線圈來形成一電感器。
本發明的一實施例揭露一種方法，其包括：提供一囊封材料；將一鐵磁心嵌入該囊封材料中；將複數個金屬層嵌入該囊封材料中以圍繞該鐵磁心延伸而形成一電感器；將複數個互連層嵌入該囊封材料中，其中該複數個互連層經組態以將該電感器耦合至一IC晶片。
本發明的一實施例揭露一種方法，其包括：將一IC晶片嵌入一模塑料中；形成一第一介電層；在該第一介電層中形成一第一金屬層；在該第一介電層上方形成一第二介電層；在該第二介電層中形成一鐵磁心及複數個通路，其中該等通路位於該鐵磁心之第一側及第二側上；在該第二介電層上方形成一第三介電層；在該第三介電層中形成一第二金屬層，其中該第一金屬層、該第二金屬層及該等通路經電連接以圍繞該鐵磁心延伸而形成一電感器；及將該IC晶片電連接至該電感器。
以下揭露提供用於實施所提供標的之不同特徵之諸多不同實施例或實例。下文將描述組件及配置之特定實例以簡化本揭露。當然，此等僅為實例且不意在限制。例如，在以下描述中，使一第一構件形成於一第二構件上方或一第二構件上可包含其中形成直接接觸之該第一構件及該第二構件之實施例，且亦可包含其中額外構件可形成於該第一構件與該第二構件之間使得該第一構件及該第二構件可不直接接觸之實施例。另外，本揭露可在各種實例中重複元件符號及/或字母。此重複係為了簡單及清楚且其本身不指示所討論之各種實施例及/或組態之間之一關係。
此外，為便於描述，空間相對術語(諸如「底下」、「下方」、「下」、「上方」、「上」及其類似者)可在本文中用於描述一元件或構件與另外(若干)元件或構件之關係，如圖中所繪示。空間相對術語除涵蓋圖中所描繪之定向之外，亦意欲涵蓋裝置在使用或操作中之不同定向。可依其他方式定向設備(旋轉90度或依其他定向)，且亦可因此解譯本文中所使用之空間相對描述詞。
隨著半導體技術的演變，半導體晶片/晶粒變得越來越小。同時，需要將更多功能整合至半導體晶粒中。因此，半導體晶粒需要使越來越多I/O襯墊堆積至更小面積中，且I/O襯墊之密度隨時間快速提高。因此，半導體晶粒之封裝變得越來越困難，此會負面影響封裝之良率。
在一些封裝技術中，在鋸切一晶圓上之晶粒之前封裝晶粒。此封裝技術具有若干有利特徵，諸如較大產量及較低成本。此外，需要較少底膠或模塑料。然而，就此類型之封裝技術而言，各晶粒之I/O襯墊受限於各自晶粒之表面正上方之區域。然而，晶粒之限制面積限制I/O襯墊之數目，其可歸因於I/O襯墊之節距。若減小襯墊之節距，則焊料區域會彼此橋接以引起電路失效。另外，在固定焊球大小要求下，焊球必須具有一特定大小，此繼而限制可堆積於一晶粒之表面上之焊球之數目。
整合扇出(InFO)封裝允許I/O襯墊及焊球比一晶粒之矽面積上方可容納之I/O襯墊及焊球多。就InFO封裝而言，將一或多個晶粒嵌入一封裝材料(諸如模塑料)中，且在該封裝材料中形成重佈層。此允許信號扇出至大於晶粒之矽面積之區域，其中可將I/O襯墊及焊球重佈至矽晶粒覆蓋區外之扇出區域以增加封裝級接針計數。
諸多電子電路需要電感器。電子系統通常包含由安裝於一基板上之大量互連組件形成之諸多系統，且此等整合系統之電力需求可大不相同。因此，需要調節電力以滿足此等不同電力需求。圖1係繪示根據本揭露之態樣之一IC裝置10之一實例的一方塊圖。圖1中所展示之實例包含一電壓調節器電路12及一封裝結構101中之一電感器100。在一些實施例中，使用InFO封裝技術來建構結構101。在電壓調節器12中，一切換裝置之工作週期判定將多少電力輸出至一負載14。脈寬調變控制輸出電壓之平均值。電壓調節器之輸出連接至充當一能量儲存元件之電感器100。
電感器100形成於IC裝置10之InFO層中。一些已知電感器應用中所使用之離散電感器可超過歸因於產品之較高整合度而需要之高效能電源管理所需之覆蓋區。通常形成於一或多個金屬層上之螺旋電感器亦要面對大覆蓋區及大電阻問題。因而，其可具有電壓轉換器之有限功能。空心螺線管電感器要面對比磁性增強螺線管低之單位面積電感值。
形成於IC裝置10之InFO層中之電感器100允許電阻比矽製造之後段製程(BEOL)階段中所建構之類似大小電感器之電阻低。此外，本文中所揭露之電感器之一些實例可具有比空心電感器高之一單元面積電感。再者，形成於InFO層中之揭露電感器減少由定位於矽程序之金屬層中之嵌入電感器引起之磁性干擾，此係因為電感器被放置成進一步遠離相關聯矽晶片之密集電力輸送網路。
圖2係繪示IC裝置10之一實例之進一步態樣的一方塊圖。裝置10包含依諸如InFO之一封裝技術建構之電感器100，使得電感器100形成且嵌入於一囊封材料110中。圖2中所展示之實施例具有實施各種電子電路(諸如電壓調節器12)之一或多個完全製造IC晶片120。各種囊封材料層110位於IC晶片120上方。在一些實施例中，在封裝程序之前測試IC晶片120。接著，根據InFO封裝程序由用於結構支撐之一模塑料122包圍此等IC晶片。
圖3係大體上繪示用於產生裝置10之一實例性程序200之態樣的一流程圖。在區塊210中，提供囊封材料110，且在區塊212中，將一鐵磁心嵌入囊封材料110中。在區塊214中，由囊封材料中圍繞鐵磁心延伸之複數個金屬層形成一電感器線圈以形成電感器100。如下文將進一步討論，在一些揭露實例中，在形成鐵磁心之前形成電感器線圈之部分，且在一些實例中，使電感器線圈或電感器線圈之部分與鐵磁心同時形成。此外，在區塊216中，在囊封材料中形成複數個互連層，該複數個互連層經組態以將電感器100耦合至(若干) IC晶片120。
圖4係繪示形成於囊封材料110中之電感器之進一步態樣的一3D透視圖。圖4中所展示之結構101繪示形成於囊封材料110中之兩個電感器100之實例。電感器100各包含一鐵磁心140。形成電感器線圈之金屬層包含位於磁心140下方之第一金屬層134及位於磁心140上方之第二金屬層144。填充金屬之通路142定位於磁心140之兩側上且連接第一金屬層134及第二金屬層144以形成圍繞磁心140延伸之電感器線圈。
圖5至圖11繪示根據揭露實施例之用於製造裝置結構10之一方法之一實例，其中依諸如InFO之一封裝技術建構電感器100。在圖5中，提供一或多個完全製造之IC晶片120，且在後續程序中將各種封裝層沈積於IC晶片120之頂部上。在一些實施方案中，已在將後續層沈積於IC晶片120上之前測試及驗證IC晶片120為功能正常的。由用於結構支撐之一模塑料122包圍晶片120。模塑料122可為一基於聚合物之材料，且可包含(例如)一模塑料、一模塑底膠、一環氧樹脂及/或一樹脂。在一些實例中，囊封材料122之頂面與IC晶片120之頂端齊平，其可透過諸如化學機械拋光(CMP)之程序來達成。
在圖6中，將一層介電材料126沈積於模塑料122及IC晶片120上。在介電層126中形成通孔128，且使用金屬來填充通孔128以提供至IC晶片120之導電連接。介電層126可由諸如PBO、聚醯亞胺等等之聚合物或替代地由諸如氮化矽、氧化矽等等之無機材料形成。可藉由諸如旋塗、化學氣相沈積(CVD)、層壓等等或其等之一組合之任何可接受沈積程序來形成介電層126。
如圖7中所展示，在含有填充金屬之通路128層之介電層126之後形成包含重佈線(RDL) 130之一封裝層金屬層。RDL 130包含介電層126上方之金屬跡線(金屬線)且連接至通路128。可透過介電質沈積及蝕刻及接著金屬層建構中常用之金屬沈積來形成RDL。作為用於形成金屬線130及通路128之一實例，在介電層126上方形成一晶種層(圖中未展示)。在一些實施例中，晶種層係一金屬層，其可為一單一層或包括由不同材料形成之複數個子層之一複合層。在一些實施例中，晶種層包括鈦層及鈦層上方之銅層。可使用(例如)物理氣相沈積(PVD)等等來形成晶種層。接著，在晶種層上形成及圖案化一光阻劑。可藉由旋塗等等來形成光阻劑且可使其暴露於光以用於圖案化。光阻劑之圖案對應於RDL 128、130之圖案。圖案化形成穿過光阻劑以暴露晶種層之開口。在光阻劑之開口中及晶種層之暴露部分上形成一導電材料。可藉由諸如電鍍或無電電鍍等等之鍍覆來形成導電材料。導電材料可包括如銅、鈦、鎢、鋁等等之一金屬。接著，移除光阻劑及其上未形成導電材料之晶種層之部分。可藉由諸如使用氧電漿等等之一可接受灰化或剝離程序來移除光阻劑。一旦移除光阻劑，則(諸如)藉由使用一可接受蝕刻程序(諸如藉由濕式或乾式蝕刻)來移除晶種層之暴露部分。晶種層之剩餘部分及導電材料形成RDL通路128及RDL線130。
在圖8中，基本上重複上述步驟以形成進一步金屬層。更特定而言，形成另一介電層126，且形成進一步RDL通路132及金屬線134。圖案化圖8中所展示之RDL 134以形成嵌入裝置10之封裝層之囊封材料中之電感器線圈之底部部分。因此，如上文結合圖3所提及，在形成電感器之鐵磁心之前形成電感器線圈之部分。
現參考圖9，在形成金屬層134 (其形成電感器線圈之下部分)之後，沈積另一介電層126且依上述方式沈積諸如CZT之一鐵磁材料140以形成電感器100之磁心。形成大體上定位成與形成電感器磁心之鐵磁材料140平行之通路142。因而，此層中之通路142與金屬層134一起形成電感器線圈之部分。換言之，如上文結合圖3所提及，在所繪示之實例中，使電感器線圈之額外部分與電感器之鐵磁心同時形成。
進一步重複此等程序，且圖10展示額外介電層126，其中沈積形成電感器100之上部分之另一金屬層144。在金屬層144之頂部上形成額外通路146以提供至結構101之外部之導電互連。因此，圖10繪示包含金屬線130及通路128之RDL，金屬線130及通路128提供形成於囊封層110中之IC晶片120與電感器100之間之電連接。金屬線134及144與通路142一起形成圍繞鐵磁電感器磁心140延伸之電感器線圈，且通路146提供至囊封層110之上表面之導電互連。可在電感器金屬層上方及/或電感器金屬層下方新增或移除額外金屬層，且亦可將用於建構電感器100之金屬層用於無需電感器之結構101之區段上之路由或其他目的。
在圖11中，將導電連接器148新增至結構10，接著可將結構10安裝於一封裝結構150中。導電連接器148可為BGA連接器、焊球、金屬柱、受控倒疊晶片連接(C4)凸塊、微凸塊、無電鍍鎳-無電鍍鈀-浸金技術(ENEPIG)形成之凸塊等等。導電連接器148可包含諸如焊料、銅、鋁、金、鎳、銀、鈀、錫等等或其等之一組合之一導電材料。在一些實施例中，藉由首先透過諸如蒸鍍、電鍍、印刷、焊料轉移、植球等等之常用方法形成一層焊料來形成導電連接器148。一旦在結構上形成一層焊料，則可執行一回焊以將材料塑形為所要凸塊形狀。在其他實施例中，導電連接器148可為藉由濺鍍、印刷、電鍍、無電電鍍、CVD等等來形成之金屬柱(諸如一銅柱)。金屬柱可不含焊料且具有實質上垂直側壁。
在其他實例中，首先(諸如)藉由一異質裝置及模組整合(HDMI)程序來建構與IC晶片120分離之封裝結構101。接著，在一單獨處理步驟中整合/附接IC晶片120。在此等實例中，使用一可再用載體來累積基本上依與先前揭露方法相反之順序構建之封裝結構101。圖12至圖17繪示此一程序之一實例。
現參考圖12，提供一可再用載體160。在一些實例中，可在載體160上形成一釋放層(圖中未展示)。可再用載體160可為一玻璃載體基板、一陶瓷載體基板等等。此外，載體160可為一晶圓，使得多個封裝可同時形成於載體160上。釋放層可由一基於聚合物之材料形成，其可與載體160一起自將在後續步驟中形成之上覆結構移除。在一些實施例中，釋放層係在被加熱時喪失其黏著性之一基於環氧樹脂之熱釋放材料，諸如一光熱轉換(LTHC)釋放塗層。在其他實施例中，釋放層可為在暴露於UV光時喪失其黏著性之一紫外線(UV)膠。釋放層可施配為一液體且經固化，可為層疊至載體160上之一層疊膜，等等。
將上文所描述之一層介電材料126沈積於載體160上。接著，蝕刻介電材料126以形成填充有金屬之通路146。如同上述早先實例，結合圖12至圖17所指涉之介電層126可由諸如PBO、聚醯亞胺等等之聚合物或替代地由諸如氮化矽、氧化矽等等之無機材料形成。另外，可藉由諸如旋塗、CVD、層疊等等或其等之一組合之任何可接受沈積程序來形成圖12至圖17中所展示之介電層126。應注意，因為層依與圖5至圖10中所展示之程序相反之一順序形成，所以通路146提供至封裝結構101之外表面之互連，如圖11中所展示。
在圖13中，沈積另一介電層126，且透過介電質沈積及蝕刻及接著金屬沈積來形成金屬層144。金屬層144經圖案化以含有電感器100之下部分。
作為用於形成金屬層144及介電層中之其他金屬構件之一實例，在介電層126上方形成一晶種層(圖中未展示)。在一些實施例中，晶種層係一金屬層，其可為一單一層或包括由不同材料形成之複數個子層之一複合層。在一些實施例中，晶種層包括鈦層及鈦層上方之銅層。可使用(例如) PVD等等來形成晶種層。接著，在晶種層上形成及圖案化一光阻劑。可藉由旋塗等等來形成光阻劑且可使其暴露於光以用於圖案化。光阻劑之圖案對應於金屬層144之圖案。圖案化形成穿過光阻劑以暴露晶種層之開口。在光阻劑之開口中及晶種層之暴露部分上形成一導電材料。可藉由諸如電鍍或無電電鍍等等之鍍覆來形成導電材料。導電材料可包括如銅、鈦、鎢、鋁等等之一金屬。接著，移除光阻劑及其上未形成導電材料之晶種層之部分。可藉由諸如使用氧電漿等等之一可接受灰化或剝離程序來移除光阻劑。一旦移除光阻劑，則(諸如)藉由使用一可接受蝕刻程序(諸如藉由濕式或乾式蝕刻)來移除晶種層之暴露部分。晶種層之剩餘部分及導電材料形成金屬層144。
如圖14中所展示，沈積另一介電層126且沈積諸如CZT之鐵磁材料140以形成電感器100之磁心。亦形成通路142，其位於沈積鐵磁材料140之兩側上以進一步形成電感器線圈。在圖15中，形成金屬層134，其藉由通路142連接至金屬層144以形成圍繞鐵磁心材料140延伸之電感器線圈以形成電感器100。可依上述方式形成金屬層及通路。
圖16繪示介電層126中之額外非電感器金屬及通路層132、130及128。此等RDL層提供至結構101之外部上表面之互連，如圖16中所展示。測試探針162除將形成於封裝結構101中之電感器100連接至IC晶片120之外，亦可耦合至此等互連以在將結構101連接至IC晶片120之前測試電感器100、金屬連接器及形成於封裝囊封物110中之其他電結構。根據圖12至圖16中所展示之程序來產生之封裝結構101允許在附接至IC晶片120之前測試(若干)電感器100以及封裝101之其他態樣。此可提供一較高總產品良率，因為僅將具有工作電感器100之封裝附接至IC晶片120。
因此，一旦測試過封裝結構101，則將其附接至一或多個IC晶片120，且移除載體160，如圖17中所展示。晶片120由用於結構支撐之一模塑料122包圍。模塑料122可為一基於聚合物之材料且可包含(例如)一模塑料、一模塑底膠、一環氧樹脂及/或一樹脂。在一些實例中，囊封材料122之頂面與IC晶片120之頂端齊平，其可透過(例如)一CMP程序來達成。新增導電連接器148，接著可依上文結合圖11所描述之方式將含有嵌入囊封材料110中之電感器100之封裝結構101附接至一封裝基板150。如同上文所討論之實例，可在形成電感器100之金屬層上方/下方新增/移除額外金屬層。此外，可將用於形成電感器100之金屬層用於無需電感器之封裝結構101之區段中之路由或其他目的。
圖18至圖20繪示其中將電感器100實施為一整合被動裝置(IPD)之另一實例。此等IPD裝置可包含(例如)藉由熟悉技術者熟知之BEOL (後段製程)半導體製程來形成之一「晶片上」電感器。再者，首先建構與IC晶片120分離之圖18及圖19中所揭露之實例，諸如一HDMI程序。接著，在一單獨處理步驟中整合/附接IC晶片120。
在圖18中，提供諸如上述可再用載體之一可再用載體160。在一些實例中，可在載體160上形成一釋放層(圖中未展示)。可再用載體160可為一玻璃載體基板、一陶瓷載體基板等等。此外，載體160可為一晶圓，使得多個封裝可同時形成於載體160上。釋放層可由一基於聚合物之材料形成，其可與載體160一起自將在後續步驟中形成之上覆結構移除。在一些實施例中，釋放層係在被加熱時喪失其黏著性之一基於環氧樹脂之熱釋放材料，諸如一LTHC釋放塗層。在其他實施例中，釋放層可為在暴露於UV光時喪失其黏著性之一UV膠。釋放層可施配為一液體且經固化，可為層疊至載體160上之一層疊膜，等等。如結合早先所揭露之實例所揭露般沈積複數個介電層126。更明確而言，圖18至圖20之實例中所展示之介電層126可由諸如PBO、聚醯亞胺等等之聚合物或替代地由諸如氮化矽、氧化矽等等之無機材料形成。可藉由諸如旋塗、CVD、層疊等等或其等之一組合之任何可接受沈積程序來形成圖18至圖20中所展示之介電層126。
在介電囊封材料110中形成包含金屬線170及通路172之金屬RDL結構。在一些實例中，藉由其中在介電層126上方形成一晶種層(圖中未展示)之一程序來形成金屬線170及通路172。在一些實施例中，晶種層係一金屬層，其可為一單一層或包括由不同材料形成之複數個子層之一複合層。在一些實施例中，晶種層包括鈦層及鈦層上方之銅層。可使用(例如) PVD等等來形成晶種層。接著，在晶種層上形成及圖案化一光阻劑。可藉由旋塗等等來形成光阻劑且可使其暴露於光以用於圖案化。光阻劑之圖案對應於待形成之金屬構件之圖案。圖案化形成穿過光阻劑以暴露晶種層之開口。在光阻劑之開口中及晶種層之暴露部分上形成一導電材料。可藉由諸如電鍍或無電電鍍等等之鍍覆來形成導電材料。導電材料可包括如銅、鈦、鎢、鋁等等之一金屬。接著，移除光阻劑及其上未形成導電材料之晶種層之部分。可藉由諸如使用氧電漿等等之一可接受灰化或剝離程序來移除光阻劑。一旦移除光阻劑，則(諸如)藉由使用一可接受蝕刻程序(諸如藉由濕式或乾式蝕刻)來移除晶種層之暴露部分。晶種層之剩餘部分及導電材料形成金屬線170及通路172。
接著，如圖19中所展示，在由電感器製造之一IPD 180兩旁放置互連件170、172之此等區塊。將互連結構170、172連接至IPD電感器180，且在一些實例中，可在最後組裝之前測試互連結構170、172。一旦測試過包含IPD電感器180之封裝結構101，則將其附接至一或多個IC晶片120，且移除載體160，如圖20中所展示。
形成於封裝結構(諸如InFO層)中之本文中所揭露之電感器允許電阻低於類似大小電感器。此外，此等電感器亦具有比空心電感器高之一單元面積電感。另外，所揭露之實施例減少由定位於矽程序之金屬層中之嵌入電感器引起之磁性干擾，此係因為電感器被放置成進一步遠離相關聯矽晶片之密集電力輸送網路。此外，由於使電感器製造與下伏晶片製造分開，所以可將此等電感器新增至由諸多不同程序產生之晶片。此降低電感器開發之總成本且提高製造之靈活性。
所揭露之實施例包含一種電感器，其形成於包含一囊封材料之一封裝結構中，其中一鐵磁心位於該囊封材料中。在該囊封材料中提供複數個金屬層以形成圍繞該鐵磁心延伸之一電感器線圈來形成一電感器。
根據進一步所揭露之實施例，一種形成一電感器之方法包含：提供一囊封材料；將一鐵磁心嵌入該囊封材料中；及將複數個金屬層嵌入該囊封材料中以圍繞該鐵磁心延伸而形成一電感器。此外，將複數個互連層嵌入該囊封材料中，其中該複數個互連層經組態以將該形成電感器耦合至一IC晶片。
根據進一步所揭露之實施例，一種形成一電感器之方法包含：將一IC晶片嵌入一模塑料中。形成一第一介電層，且在該第一介電層中形成一第一金屬層。在該第一介電層上方形成一第二介電層，且在該第二介電層中形成一鐵磁心及複數個通路。該等通路位於該鐵磁心之第一側及第二側上。在該第二介電層上方形成一第三介電層，且在該第三介電層中形成一第二金屬層。該第一金屬層、該第二金屬層及該等通路經電連接以圍繞該鐵磁心延伸而形成一電感器。將該IC晶片電連接至該電感器。
上文已概述若干實施例之特徵，使得熟悉技術者可較佳理解本揭露之態樣。熟悉技術者應瞭解，其可易於將本揭露用作用於設計或修改用於實施相同目的及/或達成本文中所引入之實施例之相同優點之其他程序及結構的一基礎。熟悉技術者亦應認知，此等等效建構不應背離本揭露之精神及範疇，且其可在不背離本揭露之精神及範疇之情況下對本文作出各種改變、替換及更改。
10‧‧‧積體電路(IC)裝置 12‧‧‧電壓調節器電路 14‧‧‧負載 100‧‧‧電感器 101‧‧‧封裝結構 110‧‧‧囊封材料/囊封層 120‧‧‧IC晶片 122‧‧‧模塑料/囊封材料 126‧‧‧介電層 128‧‧‧通孔 130‧‧‧重佈線(RDL)/金屬線 132‧‧‧RDL通路/通路層 134‧‧‧第一金屬層/金屬線 140‧‧‧鐵磁心 142‧‧‧通路 144‧‧‧第二金屬層/金屬線 146‧‧‧通路 148‧‧‧導電連接器 150‧‧‧封裝基板 160‧‧‧載體 162‧‧‧測試探針 170‧‧‧金屬線/互連結構 172‧‧‧通路/互連結構 180‧‧‧整合被動裝置(IPD)電感器 200‧‧‧程序 210‧‧‧區塊 212‧‧‧區塊 214‧‧‧區塊 216‧‧‧區塊
自結合附圖來閱讀之[實施方式]最佳理解本揭露之態樣。應注意，根據行業標準做法，各種構件未按比例繪製。事實上，為使討論清楚，可任意增大或減小各種構件之尺寸。
圖1係繪示根據一些實施例之積體電路(IC)裝置之一實例之態樣的一方塊圖。
圖2係繪示根據一些實施例之包含一電感器之一封裝結構之一實例的一方塊圖。
圖3係繪示根據一些實施例之用於在一封裝結構中形成一電感器之一方法之一實例的一程序流程圖。
圖4係概念上繪示根據一些實施例之形成於一囊封材料中之一電感器之一實例之態樣的一3D透視圖。
圖5至圖11繪示根據一些實施例之用於在一IC裝置封裝結構中形成一電感器之一方法之一實例。
圖12至圖17繪示根據一些實施例之用於在一IC裝置封裝結構中形成一電感器之一方法之另一實例。
圖18至圖20繪示根據一些實施例之用於在一IC裝置封裝結構中形成一電感器之一方法之另一實例。
100‧‧‧電感器
101‧‧‧封裝結構
110‧‧‧囊封材料/囊封層
134‧‧‧第一金屬層/金屬線
140‧‧‧鐵磁心
142‧‧‧通路
144‧‧‧第二金屬層/金屬線

Claims (10)

  1. 一種封裝結構其包括：一囊封材料；一鐵磁心，其位於該囊封材料中；複數個金屬層，其等位於該囊封材料中以形成圍繞該鐵磁心延伸之一電感器線圈來形成一電感器；複數個互連層，位於該囊封材料中；一積體電路(IC)晶片，其封裝於一模塑料中；及一封裝基板，其中該模塑料附接至該囊封材料，該囊封材料設置於該封裝基板與該IC晶片之間，以及該封裝基板與該模塑料之間，及其中該IC晶片藉由該等互連層來耦合至該電感器，且該IC晶片之一頂部表面與該模塑料之一頂部表面直接接觸該囊封材料。
  2. 如請求項1之封裝結構，其中該囊封材料包括：一第一介電層，其使該複數個金屬層之一第一者位於其內；一第二介電層，其位於該第一介電層上方，該第二介電層使該鐵磁心位於其內且界定該鐵磁心之第一側及第二側上之複數個通路；一第三介電層，其位於該第二介電層上方且使該複數個金屬層之一第二者位於其內； 其中該複數個通路電連接該第一金屬層及該第二金屬層。
  3. 如請求項1之封裝結構，其中該囊封材料設置於該封裝基板上。
  4. 如請求項1之封裝結構，其中該電感器包含一整合被動裝置(integrated passive device，IPD)。
  5. 一種形成封裝結構之方法，其包括：提供一囊封材料；將一鐵磁心嵌入該囊封材料中；將複數個金屬層嵌入該囊封材料中以圍繞該鐵磁心延伸而形成一電感器；將複數個互連層嵌入該囊封材料中，其中該複數個互連層經組態以將該電感器耦合至一IC晶片；提供封裝於一模塑料中之一IC晶片；藉由該複數個互連層來將該電感器耦合至該IC晶片；及將該囊封材料設置於一封裝基板上，其中該囊封材料設置於該封裝基板與該IC晶片之間，以及該封裝基板與該模塑料之間，且該IC晶片之一頂部表面與該模塑料之一頂部表面直接接觸該囊封材料。
  6. 如請求項5之方法，其進一步包括：形成一第一介電層；在該第一介電層中形成該複數個金屬層之一第一者； 在該第一介電層上方形成一第二介電層；在該第二介電層中形成該鐵磁心；在該第二介電層中形成複數個通路；在該第二介電層上方形成一第三介電層；在該第三介電層中形成該複數個金屬層之一第二者；及其中該第一金屬層、該第二金屬層及該等通路經電連接以形成圍繞該鐵磁心延伸之一電感器線圈。
  7. 如請求項6之方法，其進一步包括：形成一第四介電層；及於該第四介電層內形成一重佈線(redistribution layer，RDL)，且該重佈線連接至該IC晶片。
  8. 一種形成封裝結構之方法，其包括：將一IC晶片嵌入一模塑料中；形成一第一介電層；在該第一介電層中形成一第一金屬層；在該第一介電層上方形成一第二介電層；在該第二介電層中形成一鐵磁心及複數個通路，其中該等通路位於該鐵磁心之第一側及第二側上；在該第二介電層上方形成一第三介電層；在該第三介電層中形成一第二金屬層，其中該第一金屬層、該第二金屬層及該等通路經電連接以圍繞該鐵磁心延伸而形成一 電感器；將該IC晶片電連接至該電感器；及將該第一介電層、該第一金屬層、該第二介電層、該鐵磁心、該複數個通路、該第三介電層與該第二金屬層設置於一封裝基板上，其中該第一介電層、該第一金屬層、該第二介電層、該鐵磁心、該複數個通路、該第三介電層與該第二金屬層設置於該封裝基板與該IC晶片之間，以及該封裝基板與該模塑料之間，且該IC晶片之一頂部表面與該模塑料之一頂部表面直接接觸該第一介電層。
  9. 如請求項8之方法，其中在該模塑料上方形成該第一介電層。
  10. 如請求項8之方法，其中在形成該電感器之後將嵌入該模塑料中之該IC晶片附接至該第一介電層。
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