CN110610926A - 半导体结构以及形成半导体结构的方法 - Google Patents
半导体结构以及形成半导体结构的方法 Download PDFInfo
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- CN110610926A CN110610926A CN201910106363.6A CN201910106363A CN110610926A CN 110610926 A CN110610926 A CN 110610926A CN 201910106363 A CN201910106363 A CN 201910106363A CN 110610926 A CN110610926 A CN 110610926A
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Abstract
根据本发明的实施例,提供了半导体结构和形成半导体结构的方法,其中,在IC器件封装结构中形成电感器。结构包括密封材料,其中,铁磁芯位于密封材料中。在密封材料中提供多个金属层,从而形成围绕铁磁芯延伸的电感线圈以形成电感器。
Description
技术领域
本发明涉及半导体领域,并且更具体地,涉及半导体结构以及形成半导体结构的方法。
背景技术
磁电感器用于许多电子应用中。例如,电压调节器将输入电压转换为不同的输出电压。电源管理是各种集成电路应用中的必要功能。典型的集成电路(IC)可以包括由形成在半导体管芯上的大量互连组件形成的各种系统,并且用于这种集成系统的功率要求可能差别很大。
在一些电压调节器中,开关器件的占空比确定向负载输出多少功率。脉冲宽度调制控制输出电压的平均值。电压调节器的输出连接至用作能量存储元件的电感器。许多电压调节器布置可用作IC,但电感器通常是连接至功率调节器IC的离散组件。
发明内容
根据本发明的实施例,提供了一种半导体结构,包括:密封材料;铁磁芯,位于所述密封材料中;多个金属层,位于所述密封材料中,形成围绕所述铁磁芯延伸的电感线圈以形成电感器。
根据本发明的实施例,还提供了一种形成半导体结构的方法,包括:提供密封材料;将铁磁芯嵌入在所述密封材料内;将多个金属层嵌入在所述密封材料内,所述多个金属层围绕所述铁磁芯延伸以形成电感器;将多个互连层嵌入在所述密封材料内,其中,所述多个互连层被配置为将所述电感器连接至IC芯片。
根据本发明的实施例,还提供了一种形成半导体结构的方法,包括:将IC芯片嵌入在模塑料内;形成第一介电层;在所述第一介电层中形成第一金属层;在所述第一介电层上方形成第二介电层;在所述第二介电层中形成铁磁芯和多个通孔,其中,所述通孔位于所述铁磁芯的第一侧和第二侧上;在所述第二介电层上方形成第三介电层;在所述第三介电层中形成第二金属层,其中,所述第一金属层、所述第二金属层和所述通孔电连接以围绕所述铁磁芯延伸并且形成电感器;以及将所述IC芯片电连接至所述电感器。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各个方面。应该指出,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1是根据一些实施例的示出示例性集成电路(IC)器件的各个方面的框图。
图2是根据一些实施例的示出包括电感器的示例性封装结构的框图。
图3是根据一些实施例的示出用于在封装结构中形成电感器的示例性方法的工艺流程图。
图4是根据一些实施例的示出形成在密封材料中的示例性电感器的各个方面的3D立体图。
图5至图11示出了根据一些实施例的用于在IC器件封装结构中形成电感器的示例性方法。
图12至图17示出了根据一些实施例的用于在IC器件封装结构中形成电感器的另一示例性方法。
图18至图20示出了根据一些实施例的用于在IC器件封装结构中形成电感器的又一示例性方法。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上),而本文使用的空间相对描述符可以同样地作出相应的解释。
随着半导体技术的发展,半导体芯片/管芯变得越来越小。同时,需要将更多功能集成到半导体管芯中。因此,半导体管芯需要将越来越多的I/O焊盘封装至更小的区域,并且I/O焊盘的密度随着时间迅速提升。因此,半导体管芯的封装变得更加困难,这可能不利地影响封装的良率。
在一些封装技术中,晶圆上的管芯在它们被锯切之前封装。这种封装技术具有一些有利特征,诸如更高的产量和更低的成本。此外,需要较少的底部填充物或模塑料。然而,利用这种类型的封装技术,每个管芯的I/O焊盘限于相应管芯的表面正上方的区域。然而,管芯的有限区域可能由于I/O焊盘的间距而限制了I/O焊盘的数量。如果减小焊盘的间距,则焊料区域可能彼此桥接,导致电路故障。此外,在固定的球尺寸要求下,焊球必须具有一定的尺寸,这进而限制了可以封装在管芯表面上的焊球的数量。
集成扇出(InFO)封装件允许比可容纳在管芯的硅区域上方具有更多I/O焊盘和焊球。对于InFO封装件,将一个或多个管芯嵌入在封装材料(诸如模塑料)内,并且在封装材料中形成再分布层。这允许信号扇出至大于管芯的硅区域的区域,其中,I/O焊盘和球可以重新分布至硅管芯覆盖区外部的扇出区域,以增加封装级的引脚数。
许多电子电路需要电感器。电子系统通常包括由安装在衬底上的大量互连组件形成的许多系统,并且这种集成系统的功率要求可能差别很大。因此,功率调节对于满足这种变化的功率要求是必要的。图1是根据本发明的各个方面的示出示例性IC器件10的框图。图1所示的实例包括电压调节器电路12,其具有位于封装结构101中的电感器100。在一些实施例中,结构101使用InFO封装技术构造。在电压调节器12中,开关器件的占空比确定向负载14输出多少功率。脉冲宽度调制控制输出电压的平均值。电压调节器的输出连接至用作能量存储元件的电感器100。
电感器100形成在IC器件10的InFO层中。一些已知电感器应用中使用的离散电感器可能超过由于产品中更高的集成度而必需的高性能电源管理所需的覆盖区。通常形成在一个或多个金属层上的螺旋电感器也可能具有大的覆盖区,并且也具有大的电阻。因此,它们在电压转换器中可能具有有限的功能。与磁增强螺线管相比,空心螺线管电感器可能每单位面积具有较低的电感值。
形成在IC器件10的InFO层中的电感器100允许比在硅制造的后段制程(BEOL)阶段中构造的类似尺寸的电感器具有更低的电阻。此外,与空心电感器相比,本文公开的电感器的一些实例可以每单位面积具有更高的电感。此外,公开的形成在InFO层中的电感器减少了由位于硅工艺的金属层中的嵌入式电感器引起的磁干扰,因为电感器放置为更远离相关硅芯片的密集功率传输网络。
图2是示出示例性IC器件10的其它方面的框图。器件10包括以诸如InFO的封装技术构造的电感器100,从而使得电感器100形成并且嵌入在密封材料110内。图2所示的实施例具有一个或多个完全制造的IC芯片120,IC芯片120实现各种电子电路,诸如电压调节器12。密封材料110的各个层均位于IC芯片120上方。在一些实施例中,在封装工艺之前测试IC芯片120。然后,这些IC芯片由模塑料122包围,以用于符合InFO封装工艺的结构支撑。
图3是总体上示出用于生产器件10的示例性工艺200的各个方面的流程图。在框210中,提供密封材料110,并且在框212中,将铁磁芯嵌入在密封材料110内。在框214中,由密封材料中的多个金属层形成围绕铁磁芯延伸的电感线圈,以形成电感器100。如下面进一步讨论的,在一些公开的实例中,部分电感线圈在铁磁芯的形成之前形成,并且在一些实例中,电感线圈或部分电感线圈与铁磁芯同时形成。此外,在框216中,在密封材料中形成多个互连层,多个互连层被配置为将电感器100连接至IC芯片120。
图4是示出形成在密封材料110中的电感器100的其它方面的3D立体图。图4所示的结构101示出了形成在密封材料110中的两个示例性电感器100。电感器100的每个均包括铁磁芯140。形成电感线圈的金属层包括位于芯140下方的第一金属层134和位于芯140上方的第二金属层144。金属填充的通孔142位于芯140的任一侧上并且连接第一金属层134和第二金属层144以形成围绕芯140延伸的电感线圈。
图5至图11示出了根据公开的实施例的用于制造器件结构10的示例性方法,其中,电感器100以诸如InFO的封装技术构造。在图5中,提供了一个或多个完全制造的IC芯片120,并且在随后的工艺中,各个封装层沉积在它们的顶部上。在一些实施方式中,IC芯片120已经在其上沉积随后的层之前进行了测试和验证。该芯片120由模塑料122包围以用于结构支撑。例如,模塑料122可以是基于聚合物的材料,并且可以包括模塑料、模塑底部填充物、环氧树脂和/或树脂。在一些实例中,密封材料122的顶面与IC芯片120的顶端齐平,这可以通过诸如化学机械抛光(CMP)的工艺实现。
在图6中,在模塑料122和IC芯片120上沉积介电材料层126。在介电层126中形成导通孔128,并且用金属填充导通孔128以提供至IC芯片120的导电连接。介电层126可以由诸如PBO、聚酰亚胺等的聚合物形成,或可选地由诸如氮化硅、氧化硅等的无机材料形成。可以通过诸如旋涂、化学汽相沉积(CVD)、层压等或它们的组合的任何可接受的沉积工艺形成介电层126。
如图7所示,包含金属填充的通孔128层的介电层126随后是包括再分布线(RDL)130的封装层金属层。RDL 130包括位于通孔128上方并且连接至通孔128的金属迹线(金属线)。可以通过介电沉积和蚀刻以及随后的典型的金属层构造的金属沉积来形成RDL。作为形成金属线130和通孔128的实例,在介电层126上方形成晶种层(未示出)。在一些实施例中,晶种层是金属层,其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和位于钛层上方的铜层。可以使用例如物理汽相沉积(PVD)等形成晶种层。然后,在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成,并且可以暴露于光以用于图案化。光刻胶的图案对应于RDL 128、130的图案。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。然后,去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶。一旦去除光刻胶,则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成RDL通孔128和RDL线130。
在图8中,基本重复上述步骤以形成其它金属层。更具体地,形成另一介电层126,并且形成另外的RDL通孔132和金属线134。图案化图8所示的RDL 134以形成嵌入在器件10的封装层的密封材料内的电感线圈的底部分。因此,如上面结合图3所述,电感线圈的部分在形成电感器的铁磁芯之前形成。
现在参照图9,在形成金属层134(形成电感线圈的下部分)之后,沉积另一介电层126并且以上述方式沉积诸如CZT的铁磁材料140以形成电感器100的芯。形成通孔142,其通常与形成电感器芯的铁磁材料140平行。因此,该层中的通孔142与金属层134一起形成电感线圈的一部分。换句话说,在示出的实例中,如上面结合图3所述,电感线圈的附加部分与电感器的铁磁芯同时形成。
进一步重复这些工艺,并且图10示出了附加的介电层126,其中,沉积形成电感器100的上部分的另一金属层144。在金属层144的顶部上形成附加通孔146以提供至结构101的外部的导电互连。因此,图10示出了包括金属线130和通孔128的RDL,金属线130和通孔128提供了IC芯片120和形成在密封层110中的电感器100之间的电连接。金属线134和144以及通孔142形成围绕铁磁电感器芯140延伸的电感线圈,并且通孔146提供至密封剂110的上表面的导电互连。可以在电感器金属层之上和/或之下添加或去除附加金属层,并且用于构造电感器100的金属层也可以用于结构101的不需要电感器的部分上的布线或其它目的。
在图11中,将导电连接件148添加至器件10,然后可以将导电连接件148安装在封装衬底150中。导电连接件148可以是BGA连接件、焊球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯浸金技术(ENEPIG)形成的凸块等。导电连接件148可以包括诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合的导电材料。在一些实施例中,可以通过首先由诸如蒸发、电镀、印刷、焊料转移、球植等常用的方法形成焊料层来形成导电连接件148。一旦已经在结构上形成焊料层,则可以实施回流以将材料成形为期望的凸块形状。在其它实施例中,导电连接件148是通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。金属柱可以是无焊料的并且具有基本垂直的侧壁。
在其它实例中,封装结构101最初与IC芯片120分开构造,诸如通过异构器件和模块集成(HDMI)工艺。然后在单独的工艺步骤中集成/附接IC芯片120。在这样的实例中,使用可重复使用的载体来构建封装结构101,封装结构101基本以与先前公开的方法相反的顺序构建。图12至图17示出了这种工艺的实例。
现在参照图12,提供了可重复使用的载体160。在一些实例中,可以在载体160上形成释放层(未示出)。可重复使用的载体160可以是玻璃载体衬底、陶瓷载体衬底等。此外,载体160可以是晶圆,从而使得可以同时在载体160上形成多个封装件。释放层可以由基于聚合物的材料形成,释放层可以与载体160一起从将在随后的步骤中形成的上面的结构去除。在一些实施例中,释放层是诸如光热转换(LTHC)释放涂层的基于环氧树脂的热释放材料,该材料在加热时失去其粘合性。在其它实施例中,释放层可以是紫外(UV)胶,当暴露于UV光时失去其粘合性。释放层可以液体形式分配并且被固化,可以是层压在载体160上的层压膜,或可以是类似的。
在载体160上沉积上述介电材料层126。然后蚀刻介电材料126以形成通孔146,用金属填充该通孔146。与上述早先的实例一样,结合图12至图17参照的介电层126可以由诸如PBO、聚酰亚胺等的聚合物形成,或可选地由诸如氮化硅、氧化硅等的无机材料形成。另外,可以通过诸如旋涂、CVD、层压等或它们的组合的任何可接受的沉积工艺形成图12至图17所示的介电层126。注意,通孔146提供至图11所示的封装结构101的外表面的互连,因为该层以与图5至图10所示的工艺相反的顺序形成。
在图13中,沉积其它介电层126,并且通过介电沉积和蚀刻以及随后的金属沉积来形成金属层144。图案化金属层144以包含电感器100的下部分。
作为在介电层中形成金属层144和其它金属部件的实例,在介电层126上方形成晶种层(未示出)。在一些实施例中,晶种层是金属层,其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。然后,在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成,并且可以暴露于光以用于图案化。光刻胶的图案对应于金属层144的图案。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。然后,去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶。一旦去除光刻胶,则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成金属层144。
如图14所示,沉积另一介电层126,并且沉积诸如CZT的铁磁材料140以形成电感器100的芯。也形成通孔142,通孔142位于沉积的铁磁材料140的任一侧上,以进一步形成电感线圈。在图15中,形成金属层134,金属层134通过通孔142连接至金属层144,以形成围绕铁磁芯材料140延伸的电感线圈,从而形成电感器100。可以以上述方式形成金属层和通孔。
图16示出了介电层126中的附加非电感金属132以及通孔层130和128。如图16所示,这些RDL层提供至结构101的外部上表面的互连。除了将形成在封装结构101中的电感器100连接至IC芯片120之外,测试探针162可以连接至这些互连件以测试电感器100、金属连接件和形成在封装密封剂110中的其它电结构,然后将结构101连接至IC芯片120。根据图12至图16所示的工艺产生的封装结构101允许在附接至IC芯片120之前测试电感器100以及封装件101的其它方面。这可以提供更高的整体产品良率,因为仅具有工作电感器100的封装件附接至IC芯片120。
因此,如图17所示,一旦测试封装结构101,则将其附接至一个或多个IC芯片120,并且去除载体160。芯片120由模塑料122包围以用于结构支撑。例如,模塑料122可以是基于聚合物的材料,并且可以包括模塑料、模塑底部填充物、环氧树脂和/或树脂。在一些实例中,密封材料122的顶面与IC芯片120的顶端齐平,这可以通过例如CMP工艺实现。以上面结合图11描述的方式,添加导电连接件148,并且然后可以将包含嵌入在密封材料110内的电感器100的封装结构101附接至封装衬底150。如上面讨论的实例,可以在形成电感器100的金属层之上/之下添加/去除附加金属层。此外,形成电感器100使用的金属层可以用于封装结构101的不需要电感器的部分中的布线或其它目的。
图18至图20示出了另一实例,其中,电感器100实现为集成无源器件(IPD)。这种IPD器件可以包括例如由BEOL(后段制程)半导体制造工艺形成的“片上”电感器,如本领域技术人员所熟知的。此外,图18和图19中公开的实例最初与IC芯片120分开构造,诸如HDMI工艺。然后在单独的工艺步骤中集成/附接IC芯片120。
在图18中,提供了诸如上述的可重复使用的载体160。在一些实例中,可以在载体160上形成释放层(未示出)。可重复使用的载体160可以是玻璃载体衬底、陶瓷载体衬底等。此外,载体160可以是晶圆,从而使得可以同时在载体160上形成多个封装件。释放层可以由基于聚合物的材料形成,释放层可以与载体160一起从将在随后的步骤中形成的上面的结构去除。在一些实施例中,释放层是诸如LTHC释放涂层的基于环氧树脂的热释放材料,该材料在加热时失去其粘合性。在其它实施例中,释放层可以是UV胶,当暴露于UV光时失去其粘合性。释放层可以以液体形式分配并且被固化,可以是层压在载体160上的层压膜,或可以是类似的。如结合先前公开的实例所公开的,沉积多个介电层126。更具体地,图18至图20的实例中所示的介电层126可以由诸如PBO、聚酰亚胺等的聚合物形成,或可选地由诸如氮化硅、氧化硅等的无机材料形成。可以通过诸如旋涂、CVD、层压等或它们的组合的任何可接受的沉积工艺形成图18至图20所示的介电层126。
在介电密封材料110中形成包括金属线170和通孔172的金属RDL结构。在一些实例中,金属线170和通孔172通过在介电层126上方形成晶种层(未示出)的工艺形成。在一些实施例中,晶种层是金属层,其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。然后,在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成,并且可以暴露于光以用于图案化。光刻胶的图案对应于待形成的金属部件的图案。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。然后,去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶。一旦去除光刻胶,则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成金属线170和通孔172。
如图19所示,然后将这些互连块170、172放置在利用电感器制造的IPD 180旁边。互连结构170、172连接至IPD电感器180,并且在一些实例中,可以在最终组装之前测试互连结构170、172。如图20所示,一旦测试了包括IPD电感器180的封装结构101,则将其附接至一个或多个IC芯片120,并且去除载体160。
在诸如InFO层的封装结构中形成本文公开的电感器,允许比类似尺寸的电感器具有更低的电阻。此外,与空心电感器相比,这些电感器每单位面积也具有更高的电感。此外,公开的实施例减少了由位于硅工艺的金属层中的嵌入式电感器引起的磁干扰,因为电感器放置为更远离相关硅芯片的密集功率传输网络。更进一步地,通过将电感器制造与下面的芯片制造分离,可以将这些电感器添加至许多不同工艺代的芯片中。这减小了电感器开发的总成本并且增加了制造的灵活性。
公开的实施例包括形成在封装结构中的电感器,该封装结构包括密封材料,其中,铁磁芯位于密封材料中。在密封材料中提供多个金属层,从而形成围绕铁磁芯延伸的电感线圈,以形成电感器。
根据进一步公开的实施例,用于形成电感器的方法包括提供密封材料,将铁磁芯嵌入在密封材料内,以及将多个金属层嵌入在密封材料内,多个金属层围绕铁磁芯延伸,以形成电感器。多个互连层进一步嵌入在密封材料内,其中,多个互连层被配置为将形成的电感器连接至IC芯片。
根据进一步公开的实施例,形成电感器的方法包括将IC芯片嵌入在模塑料内。形成第一介电层,并且在第一介电层中形成第一金属层。在第一介电层上方形成第二介电层,并且在第二介电层中形成铁磁芯和多个通孔。通孔位于铁磁芯的第一侧和第二侧上。在第二介电层上方形成第三介电层,并且在第三介电层中形成第二金属层。第一金属层、第二金属层和通孔电连接以围绕铁磁芯延伸以形成电感器。IC芯片电连接至电感器。
根据本发明的实施例,提供了一种半导体结构,包括:密封材料;铁磁芯,位于所述密封材料中;多个金属层,位于所述密封材料中,形成围绕所述铁磁芯延伸的电感线圈以形成电感器。
根据本发明的实施例,所述密封材料包括:第一介电层,所述第一介电层中具有所述多个金属层的第一金属层;第二介电层,位于所述第一介电层上方,所述第二介电层中具有铁磁芯并且限定所述铁磁芯的第一侧和第二侧上的多个通孔;第三介电层,位于所述第二介电层上方并且所述第三介电层中具有所述多个金属层的第二金属层;其中,所述多个通孔电连接所述第一金属层和所述第二金属层。
根据本发明的实施例,还包括位于所述密封材料中的多个互连层。
根据本发明的实施例,还包括:IC芯片,封装在模塑料中;其中,所述模塑料附接至所述密封材料;以及其中,所述IC芯片通过所述互连层连接至所述电感器。
根据本发明的实施例,还包括:封装衬底;其中,所述密封材料安装在所述封装衬底上。
根据本发明的实施例,所述电感器包括集成无源器件(IPD)。
根据本发明的实施例,还提供了一种形成半导体结构的方法,包括:提供密封材料;将铁磁芯嵌入在所述密封材料内;将多个金属层嵌入在所述密封材料内,所述多个金属层围绕所述铁磁芯延伸以形成电感器;将多个互连层嵌入在所述密封材料内,其中,所述多个互连层被配置为将所述电感器连接至IC芯片。
根据本发明的实施例,还包括:形成第一介电层;在所述第一介电层中形成所述多个金属层的第一金属层;在所述第一介电层上方形成第二介电层;在所述第二介电层中形成所述铁磁芯;在所述第二介电层中形成多个通孔;在所述第二介电层上方形成第三介电层;在所述第三介电层中形成所述多个金属层的第二金属层;以及其中,所述第一金属层、所述第二金属层和所述通孔电连接以形成围绕所述铁磁芯延伸的电感线圈。
根据本发明的实施例,嵌入所述多个互连层包括:形成第四介电层;在所述第四介电层中形成再分布金属层(RDL),所述再分布金属层(RDL)被配置为将所述电感器连接至IC芯片。
根据本发明的实施例,还包括:提供封装衬底;以及将密封层安装在所述封装衬底上。
根据本发明的实施例,还包括:提供封装在模塑料中的IC芯片;以及通过所述多个互连层将所述电感器连接至所述IC芯片。
根据本发明的实施例,密封层形成在所述模塑料上方。
根据本发明的实施例,还包括在所述模塑料上方形成所述密封层之前测试所述IC芯片。
根据本发明的实施例,还包括:提供载体;以及其中,所述密封材料形成在所述载体上。
根据本发明的实施例,在形成嵌入在所述密封材料内的所述电感器之后,将所述IC芯片连接至所述多个互连层。
根据本发明的实施例,还包括在将所述IC芯片连接至所述多个互连层之后,将所述密封材料与所述载体分离。
根据本发明的实施例,还包括:形成多个介电层;在所述多个介电层中形成多个再分布金属层(RDL);将IPD电感器嵌入在所述密封材料内;以及将所述IPD电感器连接至所述多个再分布金属层。
根据本发明的实施例,还提供了一种形成半导体结构的方法,包括:将IC芯片嵌入在模塑料内;形成第一介电层;在所述第一介电层中形成第一金属层;在所述第一介电层上方形成第二介电层;在所述第二介电层中形成铁磁芯和多个通孔,其中,所述通孔位于所述铁磁芯的第一侧和第二侧上;在所述第二介电层上方形成第三介电层;在所述第三介电层中形成第二金属层,其中,所述第一金属层、所述第二金属层和所述通孔电连接以围绕所述铁磁芯延伸并且形成电感器;以及将所述IC芯片电连接至所述电感器。
根据本发明的实施例,所述第一介电层形成在模塑材料上方。
根据本发明的实施例,在形成所述电感器之后,将嵌入在所述模塑料内的所述IC芯片附接至所述第一介电层。
上面概述了若干实施例的特征,使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解,它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中它们可以做出多种变化、替换以及改变。
Claims (10)
1.一种半导体结构,包括:
密封材料;
铁磁芯,位于所述密封材料中;
多个金属层,位于所述密封材料中,形成围绕所述铁磁芯延伸的电感线圈以形成电感器。
2.根据权利要求1所述的半导体结构,其中,所述密封材料包括:
第一介电层,所述第一介电层中具有所述多个金属层的第一金属层;
第二介电层,位于所述第一介电层上方,所述第二介电层中具有铁磁芯并且限定所述铁磁芯的第一侧和第二侧上的多个通孔;
第三介电层,位于所述第二介电层上方并且所述第三介电层中具有所述多个金属层的第二金属层;
其中,所述多个通孔电连接所述第一金属层和所述第二金属层。
3.根据权利要求1所述的半导体结构,还包括位于所述密封材料中的多个互连层。
4.根据权利要求3所述的半导体结构,还包括:
IC芯片,封装在模塑料中;
其中,所述模塑料附接至所述密封材料;以及
其中,所述IC芯片通过所述互连层连接至所述电感器。
5.根据权利要求4所述的半导体结构,还包括:
封装衬底;
其中,所述密封材料安装在所述封装衬底上。
6.根据权利要求1所述的半导体结构,其中,所述电感器包括集成无源器件(IPD)。
7.一种形成半导体结构的方法,包括:
提供密封材料;
将铁磁芯嵌入在所述密封材料内;
将多个金属层嵌入在所述密封材料内,所述多个金属层围绕所述铁磁芯延伸以形成电感器;
将多个互连层嵌入在所述密封材料内,其中,所述多个互连层被配置为将所述电感器连接至IC芯片。
8.根据权利要求7所述的形成半导体结构的方法,还包括:
形成第一介电层;
在所述第一介电层中形成所述多个金属层的第一金属层;
在所述第一介电层上方形成第二介电层;
在所述第二介电层中形成所述铁磁芯;
在所述第二介电层中形成多个通孔;
在所述第二介电层上方形成第三介电层;
在所述第三介电层中形成所述多个金属层的第二金属层;以及
其中,所述第一金属层、所述第二金属层和所述通孔电连接以形成围绕所述铁磁芯延伸的电感线圈。
9.根据权利要求8所述的形成半导体结构的方法,其中,嵌入所述多个互连层包括:
形成第四介电层;
在所述第四介电层中形成再分布金属层(RDL),所述再分布金属层(RDL)被配置为将所述电感器连接至IC芯片。
10.一种形成半导体结构的方法,包括:
将IC芯片嵌入在模塑料内;
形成第一介电层;
在所述第一介电层中形成第一金属层;
在所述第一介电层上方形成第二介电层;
在所述第二介电层中形成铁磁芯和多个通孔,其中,所述通孔位于所述铁磁芯的第一侧和第二侧上;
在所述第二介电层上方形成第三介电层;
在所述第三介电层中形成第二金属层,其中,所述第一金属层、所述第二金属层和所述通孔电连接以围绕所述铁磁芯延伸并且形成电感器;以及
将所述IC芯片电连接至所述电感器。
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